Class / Patent application number | Description | Number of patent applications / Date published |
257677000 | Of specified material other than copper (e.g., Kovar (T.M.)) | 22 |
20080197467 | Conductive structure for a semiconductor integrated circuit and method for forming the same - A conductive structure for a semiconductor integrated circuit and method for forming the conductive structure are provided. The semiconductor integrated circuit has a pad and a passivation layer partially covering the pad to define a first opening portion having a first lateral size. The conductive structure electrically connects to the pad via the first opening portion. The conductive structure comprises a support layer defining a second opening portion. A conductor is formed in the second opening portion to serve as a bump having a planar top surface. | 08-21-2008 |
20080258281 | Process for Producing and Apparatus for Improving the Bonding Between a Plastic and a Metal - A semiconductor having a leadframe is disclosed. In one embodiment, a leadframe is disclosed to be fitted with a semiconductor chip and is to be encapsulated with a plastic compound has a metallic single-piece base body, to which an interlayer is applied. The interlayer has a surface including a matrix of islands of remaining material of substantially uniform height, with voids extending between said islands. | 10-23-2008 |
20080290487 | LEAD FRAME FOR SEMICONDUCTOR DEVICE - A lead frame for a semiconductor device includes at least one row of contact terminals and a die pad for receiving an integrated circuit die. An isolation material is located between the contact terminals and the die pad. The isolation material electrically isolates adjacent lead fingers from each other and from the die pad. The isolation material also holds the lead fingers in place during a wire bonding operation and thus the bottom of the lead frame does not have to be taped during the assembly process, which saves taping and detaping steps from being performed. The isolation material also prevents resin bleed problems that sometimes occur when using tape. If a sawing step is performed, the saw need only cut through the isolation material instead of a metal, and thus saw blade life is improved. | 11-27-2008 |
20090014855 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor integrated circuit device includes a die pad and a semiconductor chip mounted over the die pad, having a main surface with surface electrodes and a back surface. Suspension leads support the die pad, and leads are arranged around the semiconductor chip, each of the leads having inner and outer lead portions. A first plating layer is formed at a part of the inner lead portions and a second plating layer is formed over the outer lead portion. Wires electrically connect the surface electrodes with the inner lead portions through the first plating layer. A resin body seals the die pad, the chip, the wires and the inner lead portions. The second plating layer is comprised of different materials than the first plating layer, and is a Pb-free metal layer. | 01-15-2009 |
20090051022 | LEAD FRAME STRUCTURE - A lead frame structure includes a lead frame, a partial plated portion, a semiconductor element, a Pb-free solder and a mold resin. The partial plated portion is formed on a part of a surface of the lead frame. The partial plated portion is made of a noble metal. The semiconductor element is bonded with the partial plated portion through a Pb-free solder and is electrically connected to the lead frame through the Pb-free solder and the partial plated portion. The mold resin encloses the semiconductor element and the lead frame other than a coupling portion, which is to be electrically coupled to an external device. | 02-26-2009 |
20090057858 | Low cost lead frame package and method for forming same - According to one exemplary embodiment, a lead frame package includes a number of leads and a number of contacts, where each of the contacts is situated over one of the leads. The lead frame package further includes a semiconductor die including a number of bond pads. Each of the contacts is directly attached and bonded to one of the bond pads on the semiconductor die. Each of the contacts is situated over a top portion of one of the leads, where the top portion has a shorter length than a middle portion of each of the leads. Each of the contacts is connected to one of the bond pads on the semiconductor die without a wire bond. The semiconductor die does not include a redistribution layer situated over an active surface of the semiconductor die. | 03-05-2009 |
20090115040 | INTEGRATED CIRCUIT PACKAGE SYSTEM WITH ARRAY OF EXTERNAL INTERCONNECTS - An integrated circuit package system includes: forming an array of external interconnects with an intersecting region between the external interconnects; removing the intersecting region for forming an isolation hole between the external interconnects; mounting an integrated circuit die over the external interconnects; connecting an internal interconnect between the integrated circuit die and the external interconnects; and forming a package encapsulation over the integrated circuit die with the external interconnects partially exposed. | 05-07-2009 |
20090218666 | Power device package and method of fabricating the same - Provided are a power device package, which can be made compact by vertically stacking substrates on which semiconductor chips are mounted, and a method of fabricating the power device package. The power device package includes: a first substrate comprising a first surface and a second surface opposite to each other, and a first wiring pattern formed on the first surface; one or more power semiconductor chips mounted on the first surface of the first substrate and electrically connected to the first wiring pattern; a second substrate vertically spaced apart from the first substrate and comprising a second wiring pattern; one or more first control semiconductor chips mounted on the second substrate and electrically connected to the second wiring pattern; a lead frame electrically connected to the first wiring pattern and the second wiring pattern; and a sealing member sealing the first substrate, the power semiconductor chips, the second substrate, the first control semiconductor chips, and at least a part of the lead frame so as to expose the second surface of the first substrate. | 09-03-2009 |
20100025830 | A METHOD FOR FORMING AN ETCHED RECESS PACKAGE ON PACKAGE SYSTEM - An integrated circuit package system includes: providing a die attach paddle with interconnection pads connected to a bottom surface of the die attach paddle; connecting a first device to the interconnection pads with a bond wire; connecting a lead to the interconnection pad or to the first device; encapsulating the first device and the die attach paddle with an encapsulation having a top surface; and etching the die attach paddle leaving a recess in the top surface of the encapsulation. | 02-04-2010 |
20110193209 | SEMICONDUCTOR PACKAGE - The present invention relates to a semiconductor package, comprising a carrier, a semiconductor device, a first wire and a second wire. The carrier has a first electrically connecting portion and a second electrically connecting portion. The semiconductor device has a plurality of pads. The first wire electrically connects one of the pads of the semiconductor device and the first electrically connecting portion of the carrier, and the first wire has a first length. The second wire electrically connects one of the pads of the semiconductor device and the second electrically connecting portion of the carrier, and the second wire has a second length. The second length is larger than the first length, and the diameter of the second wire is larger than that of the first wire. Thus, the material usage for the wire is reduced, and the manufacturing cost is reduced. | 08-11-2011 |
20110215456 | THIN PACKAGE SYSTEM WITH EXTERNAL TERMINALS AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of a thin package system with external terminals includes: providing a leadframe; providing a template for defining an external bond finger; forming external bond fingers in the template on the leadframe; forming land pad terminals by a first multi-layer plating; providing a die; attaching the die to the land pad terminals above the leadframe with an adhesive on the leadframe; covering an encapsulant over at least portions of the die and the external bond fingers; and removing the leadframe leaving a surface of the adhesive coplanar with a surface of the encapsulant. | 09-08-2011 |
20110221052 | LEAD FRAME FOR SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING OF THE SAME - Provided are a semiconductor device lead frame and a method of manufacturing of the same that improve adhesive properties between plating layers when a plurality of plating layers are laminated, that control deterioration in wire bonding properties during the manufacturing process of a semiconductor device and worsening of solderability during packaging, and that effectively reduce manufacturing cost. Specifically, the lead frame ( | 09-15-2011 |
20120038036 | Structure for Multi-Row Leadframe and Semiconductor Package Thereof and Manufacture Method Thereof - The present invention relates to a multi-row leadframe for semiconductor packaging, characterized by: forming a plating pattern on a leadframe material (first step); forming a protective pattern on the plating pattern (second step); and forming a nano pattern by using the protective pattern as a mask (third step), whereby a protective pattern is formed on an upper surface of a plating pattern to increase reliability of a product by preventing damage to a plating layer caused by etching solution during pattern formation of leadframe and to thereby solve the problem of using the plating layer as an etching mask. | 02-16-2012 |
20120074553 | METHOD AND SYSTEM FOR IMPROVING RELIABILITY OF A SEMICONDUCTOR DEVICE - A method and a system for improving reliability of a semiconductor device are provided. In one embodiment, a semiconductor device is provided comprising a semiconductor chip, a metallization layer comprising a metallic material disposed over a surface of the semiconductor chip, and an alloy layer comprising the metallic material disposed over the metallization layer. | 03-29-2012 |
20120126385 | METHOD FOR SEMICONDUCTOR LEADFRAMES IN LOW VOLUME AND RAPID TURNAROUND - A leadframe for a QFN/SON semiconductor device comprising a strip of a first metal as the leadframe core with a plurality of leads and a pad. a layer of a second metal over both surfaces of the strip. There are sidewalls normal to the surfaces. The first metal exposed at the sidewalls and at portions of a surface of the pad. | 05-24-2012 |
20120146205 | Multi-Chip Module (MCM) Power Quad Flat No-Lead (PQFN) Semiconductor Package Utilizing a Leadframe for Electrical Interconnections - Some exemplary embodiments of a multi-chip module (MCM) power quad flat no-lead (PQFN) semiconductor package utilizing a leadframe for electrical interconnections have been disclosed. One exemplary embodiment comprises a PQFN semiconductor package comprising a leadframe, a driver integrated circuit (IC) coupled to the leadframe, a plurality of vertical conduction power devices coupled to the leadframe, and a plurality of wirebonds providing electrical interconnects, including at least one wirebond from a top surface electrode of one of the plurality of vertical conduction power devices to a portion of the leadframe, wherein the portion of the leadframe is electrically connected to a bottom surface electrode of another of the plurality of vertical conduction power devices. In this manner, efficient multi-chip circuit interconnections can be provided in a PQFN package using low cost leadframes. | 06-14-2012 |
20120313234 | QFN PACKAGE AND MANUFACTURING PROCESS THEREOF - The present invention provides a Quad Flat Non-leaded (QFN) package, which comprises a chip, a lead frame, a plurality of composite bumps and an encapsulant. The chip has a plurality of pads, and the lead frame has a plurality of leads. Each of the plurality of composite bumps has a first conductive layer and a second conductive layer. The first conductive layer is electrically connected between one of the pads and the second conductive layer, and the second conductive layer is electrically connected between the first conductive layer and one of the leads. The encapsulant encapsulates the chip, the leads and the composite bumps. Thereby, a QFN package with composite bumps and a semi-cured encapsulant is forming between the spaces of leads of lead frame before chip bonded to the lead frame are provided. | 12-13-2012 |
20130161807 | METHOD FOR JOINTING METAL MEMBER AND RESIN AND JOINTED BODY THEREOF - Reliability is improved by improving adhesiveness, crack resistance, and moisture resistance of a metal member-resin jointed body by enhancing adhesiveness between the metal member and the resin. | 06-27-2013 |
20130307133 | SEMICONDUCTOR DEVICE ASSEMBLY AND SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A method of manufacturing, at a reduced cost, a semiconductor device assembly and a semiconductor device, having a conductive support which is not eroded by an etchant for a lift-off layer even when the lift-off layer is made of a material for which no suitable selective etching solution has been found is provided. In the method of manufacturing the semiconductor device assembly, a plating step of forming a conductive support is carried out such that a first metal which is dissolved with an etchant is encapsulated in second metal which are not dissolved with the etchant, and through-holes for supplying etchant are formed in the second metal. | 11-21-2013 |
20130341780 | CHIP ARRANGEMENTS AND A METHOD FOR FORMING A CHIP ARRANGEMENT - A chip arrangement is provided. The chip arrangement including: a chip including at least one electrically conductive contact; a passivation material formed over the at least one electrically conductive contact; an encapsulation material formed over the passivation material; one or more holes formed through the encapsulation material and the passivation material, wherein the passivation material at least partially surrounds the one or more holes; and electrically conductive material provided within the one or more holes, wherein the electrically conductive material is electrically connected to the at least one electrically conductive contact. | 12-26-2013 |
20140001622 | CHIP PACKAGES, CHIP ARRANGEMENTS, A CIRCUIT BOARD, AND METHODS FOR MANUFACTURING CHIP PACKAGES | 01-02-2014 |
20140183716 | SILVER-TO-SILVER BONDED IC PACKAGE HAVING TWO CERAMIC SUBSTRATES EXPOSED ON THE OUTSIDE OF THE PACKAGE - A packaged power device involves no soft solder and no wire bonds. The direct-bonded metal layers of two direct metal bonded ceramic substrate assemblies, such as Direct Bonded Aluminum (DBA) substrates, are provided with sintered silver pads. Silver nanoparticle paste is applied to pads on the frontside of a die and the paste is sintered to form silver pads. Silver formed by an evaporative process covers the backside of the die. The die is pressed between the two DBAs such that direct silver-to-silver bonds are formed between sintered silver pads on the frontside of the die and corresponding sintered silver pads of one of the DBAs, and such that a direct silver-to-silver bond is formed between the backside silver of the die and a sintered silver pad of the other DBA. After leadforming, leadtrimming and encapsulation, the finished device has exposed ceramic of both DBAs on outside package surfaces. | 07-03-2014 |