Class / Patent application number | Description | Number of patent applications / Date published |
257653000 | WITH SPECIFIED SHAPE OF PN JUNCTION | 26 |
20090179309 | Power semiconductor component with trench- type second contact region - A power semiconductor component and method for producing it. The component has a semiconductor base body with a first doping and a pn junction formed by a contact region having a second doping with a doping profile in the base body. The second contact region is arranged at a second surface of the base body and extends into the base body. The base body has a trench-type cutout with an edge area and a base area, wherein the base area is formed as a second partial area of the second surface, and wherein the second contact region extends from the base area via the edge area as far as a first partial area. Furthermore, the pn junction has a curvature adjacent to the edge area. | 07-16-2009 |
20090218662 | SEMICONDUCTOR DEVICE - A semiconductor device includes: a first semiconductor region of a first conductive type; a second semiconductor region of the first conductive type formed on an upper surface of the first semiconductor region and having a lower impurity concentration than that of the first semiconductor region; a third semiconductor region of the first conductive type formed on the upper surface of the first semiconductor region and having a higher impurity concentration than that of the second semiconductor region; and a fourth semiconductor region of a second conductive type different from the first conductive type formed on upper surfaces of the second semiconductor region and the third semiconductor region. A PN junction is formed between the second semiconductor region and third semiconductor region and the fourth semiconductor region. The second semiconductor region is formed to surround the third semiconductor region. | 09-03-2009 |
20090230516 | PIN Diode with Improved Power Limiting - A PIN diode comprising an N-type substrate comprising a cathode of the PIN diode and having an intrinsic layer disposed upon the N-type substrate and having a top surface a P-type material disposed upon the top surface of the intrinsic layer comprising an anode of the PIN diode and a N-type material disposed over the sidewall of the cathode and over the sidewall and a portion of the top surface of the intrinsic material that is not occupied by the anode, wherein a horizontal gap is defined between the anode and the cathode through the intrinsic material, the gap being variable in width and/or the horizontal gap is less than the thickness of the intrinsic layer. | 09-17-2009 |
20100052116 | FABRICATION OF SELF-ASSEMBLED NANOWIRE-TYPE INTERCONNECTS ON A SEMICONDUCTOR DEVICE - The present invention relates to a semiconductor device with nanowire-type interconnect elements and a method for fabricating the same. The device comprises a metal structure with at least one self-assembled metal dendrite and forming an interconnect element ( | 03-04-2010 |
20100102419 | Epitaxy-Level Packaging (ELP) System - An epitaxy-level packaging grows an epitaxial film and transfers it to an assembly substrate. The film growth and transfer are made using an epitaxy lateral overgrowth technique. The formed epitaxial film on an assembly substrate can be further processed to form devices such as solar cell, light emitting diode, and other devices and assembled into higher integration of desired applications. | 04-29-2010 |
20100155911 | ESD Protection Diode in RF pads - A diode is provided. The diode includes first and second diffusion layers formed in a substrate, a first metal coupled to the first diffusion layer, and a second metal coupled to the second diffusion layer that has width that is smaller than a width of the second diffusion layer. | 06-24-2010 |
20110049683 | STRUCTURES, METHODS AND APPLICATIONS FOR ELECTRICAL PULSE ANNEAL PROCESSES - Structures and methods are provided for nanosecond electrical pulse anneal processes. The method of forming an electrostatic discharge (ESD) N+/P+ structure includes forming an N+ diffusion on a substrate and a P+ diffusion on the substrate. The P+ diffusion is in electrical contact with the N+ diffusion. The method further includes forming a device between the N+ diffusion and the P+ diffusion. A method of annealing a structure or material includes applying an electrical pulse across an electrostatic discharge (ESD) N+/P+ structure for a plurality of nanoseconds. | 03-03-2011 |
20110068439 | DOUBLE TRENCH RECTIFIER - A high power density or low forward voltage rectifier which utilizes at least one trench in both the anode and cathode. The trenches are formed in opposing surfaces of the substrate, to increase the junction surface area per unit surface area of the semiconductor die. This structure allows for increased current loads without increased horizontal die space. The increased current handling capability allows for the rectifier to operate at lower forward voltages. Furthermore, the present structure provides for increased substrate usage by up to 30 percent. | 03-24-2011 |
20120032312 | SEMICONDUCTOR SUBSTRATE, SEMICONDUCTOR DEVICE, AND METHOD OF PRODUCING SEMICONDUCTOR SUBSTRATE - A semiconductor substrate which allows desired electrical characteristics to be more easily acquired, a semiconductor device of the same, and a method of producing the semiconductor substrate. The method of producing this semiconductor substrate is provided with: a first epitaxial layer forming step (S | 02-09-2012 |
20120133031 | FABRICATION OF SELF-ASSEMBLED NANOWIRE-TYPE INTERCONNECTS ON A SEMICONDUCTOR DEVICE - Consistent with an example embodiment, there is a semiconductor device with nanowire-type interconnect elements. | 05-31-2012 |
20120223421 | DOUBLE TRENCH RECTIFIER - A high power density or low forward voltage rectifier which utilizes at least one trench in both the anode and cathode. The trenches are formed in opposing surfaces of the substrate, to increase the junction surface area per unit surface area of the semiconductor die. This structure allows for increased current loads without increased horizontal die space. The increased current handling capability allows for the rectifier to operate at lower forward voltages. Furthermore, the present structure provides for increased substrate usage by up to 30 percent. | 09-06-2012 |
20120248584 | NANO/MICRO-SIZED DIODE AND METHOD OF PREPARING THE SAME - A nano/micro-sized diode and a method of preparing the same, the diode including: a first electrode; a second electrode; and a diode layer that is disposed between the first electrode and the second electrode. The diode layer includes a first layer and a second layer. The first layer is disposed on the first electrode and has a first surface that is electrically connected to the first electrode, and an opposing second surface that has a protrusion. The second layer is disposed between the first layer and the second electrode and has a first surface having a recess that corresponds to the protrusion, and an opposing second surface that is electrically connected to the second electrode. | 10-04-2012 |
20120261804 | VERTICAL SUBSTRATE DIODE, METHOD OF MANUFACTURE AND DESIGN STRUCTURE - A diode structure, formed under a buried dielectric layer of a silicon on insulator (SOI), method of manufacturing the same and design structure thereof are provided. In an embodiment the p-n junction of the diode structure can be advantageously arranged in a vertical orientation. The cathode comprises an N+ epitaxial layer formed upon a P-type substrate. The anode comprises an active region of the P-substrate. Contacts to the cathode and anode are formed through the buried dielectric layer. Contact to the anode is accomplished via a deep trench filled with a conductive plug. The deep trench also provides electrical isolation for the cathode (as well as p-n junction). Advantageously, embodiments of the present invention may be formed during formation of other structures which also include trenches (for example, deep trench capacitors) in order to reduce process steps required to form the diode structure under the buried dielectric layer of the SOI substrate. | 10-18-2012 |
20140061874 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - An exemplary semiconductor device comprises a through silicon via penetrating a semiconductor substrate including a circuit pattern on one side of the substrate, a first doped layer formed in the other side, and a bump connected with the through silicon via. | 03-06-2014 |
20140124903 | STRUCTURES, METHODS AND APPLICATIONS FOR ELECTRICAL PULSE ANNEAL PROCESSES - Structures and methods are provided for nanosecond electrical pulse anneal processes. The method of forming an electrostatic discharge (ESD) N+/P+ structure includes forming an N+ diffusion on a substrate and a P+ diffusion on the substrate. The P+ diffusion is in electrical contact with the N+ diffusion. The method further includes forming a device between the N+ diffusion and the P+ diffusion. A method of annealing a structure or material includes applying an electrical pulse across an electrostatic discharge (ESD) N+/P+ structure for a plurality of nanoseconds. | 05-08-2014 |
20140246761 | FAST RECOVERY SWITCHING DIODE WITH CARRIER STORAGE AREA - A power device (such as a power diode) has a peripheral die area and a central area. The main PN junction of the device is formed by a P+ type region that extends down into an N− type layer. The central portion of the P+ type region has a plurality of openings so mesa structures of the underlying N− type material extend up to the semiconductor surface through the openings. Due to the mesa structures being located in the central portion of the die, there are vertically extending extensions of the PN junction in the central portion of the die. Minority carrier charge storage is more uniform per unit area across the surface of the die. Due to the form of the P+ type region and the mesa structures, the reverse recovery of the PN junction exhibits a soft characteristic. | 09-04-2014 |
20140246762 | SEMICONDUCTOR DEVICE HAVING DEEP WELLS AND FABRICATION METHOD THEREOF - Semiconductor devices and methods of fabricating the same are provided. An insulating film can be disposed on a semiconductor substrate, and insulating film patterns can be formed opening a plurality of areas with predetermined widths by patterning the insulating film. A plurality of ion implantation areas having a first conductivity type can be formed by implanting impurities into the plurality of open areas, and an oxide film pattern can be formed on each of the ion implantation areas. The insulating film patterns can be removed, and ion implantation areas having a second conductivity type can be formed by implanting impurities using the oxide film pattern as a mask. The semiconductor substrate can be annealed at a high temperature to form deep wells. | 09-04-2014 |
20140327118 | POWER SEMICONDUCTOR DEVICE AND FABRICATING METHOD THEREOF - A method of fabricating a power semiconductor device includes the following steps. Firstly, a substrate is provided. A first epitaxial layer is formed over the substrate. A first trench is formed in the first epitaxial layer. A second epitaxial layer is refilled into the first trench. The first epitaxial layer and the second epitaxial layer are collaboratively defined as a first semiconductor layer. A third epitaxial layer is formed over the substrate, and a second trench is formed in the third epitaxial layer. A first doping region is formed in a sidewall of the second trench. An insulation layer is refilled into the second trench. The insulation layer, the first doping region and the third epitaxial layer are collaboratively defined as a second semiconductor layer. The power semiconductor device fabricated by the fabricating method can withstand high voltage and has low on-resistance. | 11-06-2014 |
20160035716 | STRUCTURES, METHODS AND APPLICATIONS FOR ELECTRICAL PULSE ANNEAL PROCESSES - Structures and methods are provided for nanosecond electrical pulse anneal processes. The method of forming an electrostatic discharge (ESD) N+/P+ structure includes forming an N+ diffusion on a substrate and a P+ diffusion on the substrate. The P+ diffusion is in electrical contact with the N+ diffusion. The method further includes forming a device between the N+ diffusion and the P+ diffusion. A method of annealing a structure or material includes applying an electrical pulse across an electrostatic discharge (ESD) N+/P+ structure for a plurality of nanoseconds. | 02-04-2016 |
20160079441 | High Frequency Power Diode and Method for Manufacturing the Same - High frequency power diode including a semiconductor wafer having first and second main sides, a first layer of a first conductivity type formed on the first main side, a second layer of a second conductivity type formed on the second main side and a third layer of the second conductivity type formed between the first layer and the second layer. The first layer has a dopant concentration decreasing from 10 | 03-17-2016 |
20160093694 | METHODS AND APPARATUSES INCLUDING AN ACTIVE AREA OF A TAP INTERSECTED BY A BOUNDARY OF A WELL - Apparatuses and methods are disclosed. One such apparatus includes a well having a first type of conductivity formed within a semiconductor structure having a second type of conductivity. A boundary of the well intersects an active area of a tap to the well. | 03-31-2016 |
20160148992 | SEMICONDUCTOR DEVICE - A semiconductor device comprising a substrate is disclosed. The substrate comprises: a well of type one; a first doped region of type two, provided in the well of type one; a well of type two, adjacent to the well of type one; and a first doped region of type one, doped in the well of type two. The substrate comprises no isolating material provided in a current path formed by the first doped region of type two, the well of type one, the well of type two and the first doped region of type one. | 05-26-2016 |
20160379924 | EFFICIENT LAYOUT PLACEMENT OF A DIODE - A semiconductor device includes a plurality of first wires and a plurality of second wires. Each of the first wires forms a closed polygon and surrounds a center. Each of the second wires is forming the closed polygon and surrounding the center. The first and second wires are interlaced, and none of the first wires and second wires are coupled to each other. | 12-29-2016 |
20220140077 | SEMICONDUCTOR DEVICE - The semiconductor device has the main surface, the semiconductor substrate having the first impurity region formed on the main surface, the first electrode formed on the main surface having the first impurity region, the insulating film formed on the main surface such that surround the first electrode, the second electrode formed on the insulating film such that spaced apart from the first electrode and annularly surround the first electrode, and the semi-insulating film. The first electrode has the outer peripheral edge portion. The semi-insulating film is continuously formed from on the outer peripheral edge portion to on the second electrode. The outer peripheral edge portion includes the first corner portion. The second electrode has the second corner portion facing the first corner portion. The semi-insulating film on the insulating film is removed between the first corner and the second corner portion. | 05-05-2022 |
257654000 | Interdigitated pn junction or more heavily doped side of junction is concave | 2 |
20140035111 | LAYOUT CONFIGURATION FOR MEMORY CELL ARRAY - A layout configuration for a memory cell array includes at least a comb-like doped region having a first conductivity type and a fishbone-shaped doped region having a second conductivity type. The second conductivity type and the first conductivity type are complementary. Furthermore, the comb-like doped region and the fishbone-shaped doped region are interdigitated. | 02-06-2014 |
20150061089 | Vertical Semiconductor Device and Method of Manufacturing Thereof - A vertical semiconductor device has a semiconductor body with a first surface and a second surface substantially parallel to the first surface. A first metallization is arranged on the first surface. A second metallization is arranged on the second surface. In a sectional plane perpendicular to the first surface, the semiconductor body includes an n-doped first semiconductor region in ohmic contact with the second metallization, a plurality of p-doped second semiconductor regions in ohmic contact with the first metallization, and a plurality of p-doped embedded semiconductor regions. The p-doped second semiconductor regions substantially extend to the first surface, are spaced apart from one another and form respective first pn-junctions with the first semiconductor region. The p-doped embedded semiconductor regions are spaced apart from one another, from the p-doped second semiconductor regions, from the first surface and from the second surface, and form respective second pn-junctions with the first semiconductor region. | 03-05-2015 |