Entries |
Document | Title | Date |
20080203540 | STRUCTURE AND METHOD FOR DEVICE-SPECIFIC FILL FOR IMPROVED ANNEAL UNIFORMITY - Disclosed are embodiments of a wafer that incorporates fill structures with varying configurations to provide uniform reflectance. Uniform reflectance is achieved by distributing across the wafer fill structures having different semiconductor materials such that approximately the same ratio and density between the different semiconductor materials is achieved within each region and, optimally, each sub-region. Alternatively, it is achieved by distributing across the wafer fill structures, including one or more hybrid fill structure containing varying proportions of different semiconductor materials, such that approximately the same ratio between the different semiconductor materials is achieved within each region and, optimally, each sub-region. Alternatively, it is achieved by distributing across the wafer fill structures having semiconductor materials with different thicknesses such that approximately the same overall ratio between the semiconductor material with the different thicknesses is achieved within each region and, optimally, each sub-region. | 08-28-2008 |
20080237810 | Controlling substrate surface properties via colloidal coatings - Methods and apparatus to control surface properties via colloidal coatings are described. In one embodiment, colloidal coating may be used on a surface to enhance flow control. Other embodiments are also described. | 10-02-2008 |
20080272467 | Method for Forming Fine Pattern of Semiconductor Device - A method for forming a fine pattern of a semiconductor device includes forming a deposition film over a substrate having an underlying layer. The deposition film includes first, second, and third mask films. The method also includes forming a photoresist pattern over the third mask film, patterning the third mask film to form a deposition pattern, and forming an amorphous carbon pattern at sidewalls of the deposition pattern. The method further includes filling a spin-on-carbon layer over the deposition pattern and the amorphous carbon pattern, polishing the spin-on-carbon layer, the amorphous carbon pattern, and the photoresist pattern to expose the third mask pattern, and performing an etching process to expose the first mask film with the amorphous carbon pattern as an etching mask. The etching process removes the third mask pattern and the exposed second mask pattern. The method also includes removing the spin-on-carbon layer and the amorphous carbon pattern, and forming a first mask pattern with the second mask pattern as an etching mask. | 11-06-2008 |
20080290471 | Method For Making a Thin-Film Structure and Resulting Thin-Film Structure - A method for making a thin-film structure includes a thin film stabilized on a substrate. The structure of the thin film is defined by a material which includes at least one first chemical species. The method includes a step of inputting particles of the first chemical species into the thin film so as to compensate for the flow of vacancies from the surface of the film. | 11-27-2008 |
20090008750 | SEAL RING FOR SEMICONDUCTOR DEVICE - A semiconductor device having a seal ring structure with high stress resistance is provided. The semiconductor device is provided with a semiconductor layer including a plurality of semiconductor elements, an insulating film formed on the semiconductor layer, and a body that passes through the insulating film and surrounds the semiconductor elements as a whole. The body includes a plurality of walls that are spaced apart from each other in a circumferential direction and are arranged in parallel with one another, and a plurality of bridges, each of which intersects at least one of the plurality of walls. | 01-08-2009 |
20090051013 | SEMICONDUCTOR WAFER FOR SEMICONDUCTOR COMPONENTS AND PRODUCTION METHOD - A semiconductor wafer for semiconductor components and to a method for its production is disclosed. In one embodiment, the semiconductor wafer includes a front side with an adjoining near-surface active zone as basic material for semiconductor component structures. The rear side of the semiconductor wafer is adjoined by a getter zone for gettering impurity atoms in the semiconductor wafer. The getter zone contains oxygen precipitates. In the near-surface active zone, atoms of doping material are located on lattice vacancies. The atoms of doping material have a higher diffusion coefficient that the oxygen atoms. | 02-26-2009 |
20090065908 | METHODS OF FABRICATING A MICROMECHANICAL STRUCTURE - Methods of fabricating a microelectromechanical structure are provided. An exemplary embodiment of a method of fabricating a microelectromechanical structure comprises providing a substrate. A first patterned sacrificial layer is formed on portions of the substrate, the first patterned sacrificial layer comprises a bulk portion and a protrusion portion. A second patterned sacrificial layer is formed over the first sacrificial layer, covering the protrusion portion and portions of the bulk portion of the first patterned sacrificial layer, wherein the second patterned sacrificial layer does not cover sidewalls of the first patterned sacrificial layer. An element layer is formed over the substrate, covering portions of the substrate, the first patterned sacrificial layer and second patterned sacrificial layer. The first and second patterned sacrificial layers are removed, leaving a microstructure on the substrate. | 03-12-2009 |
20090085170 | INTERFACIAL ROUGHNESS REDUCING FILM, WIRING LAYER, SEMICONDUCTOR DEVICE, AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - An interfacial roughness reducing film which is in contact, on one side thereof, with an insulating film and in contact, on a side opposite from the one side, with wiring comprises a Si—O bond, and is formed using a composition containing a silicon compound that comprises at least one bond of Si—N bonds and Si—Cl bonds wherein the number of Si—N bonds and Si—Cl bonds combined per molecule of the compound is at least two. An interfacial roughness between the interfacial roughness reducing film and the wiring is smaller than that between the interfacial roughness reducing film and the insulating film. | 04-02-2009 |
20090096066 | Structure and Method for Device-Specific Fill for Improved Anneal Uniformity - Disclosed is a design structure embodiment of a wafer that incorporates fill structures with varying configurations to provide uniform reflectance. Uniform reflectance is achieved by distributing across the wafer fill structures having different semiconductor materials such that approximately the same ratio and density between the different semiconductor materials is achieved within each region and, optimally, each sub-region. Alternatively, it is achieved by distributing across the wafer fill structures, including one or more hybrid fill structure containing varying proportions of different semiconductor materials, such that approximately the same ratio between the different semiconductor materials is achieved within each region and, optimally, each sub-region. Alternatively, it is achieved by distributing across the wafer fill structures having semiconductor materials with different thicknesses such that approximately the same overall ratio between the semiconductor material with the different thicknesses is achieved within each region and, optimally, each sub-region. | 04-16-2009 |
20090102024 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING SAME - A semiconductor device has an IC chip with a thickness of equal to or less than 100 μm and includes a semiconductor substrate. A device forming region is within the depth of approximately equal to or less than 5 μm from a surface of the semiconductor substrate, and a total thickness of the semiconductor substrate is from 5 μm to 100 μm. A BMD layer for carrying out gettering of metal impurities is provided immediately under the device forming region. Since a gettering site is provided immediately under the device forming region, in a device or the like of which extreme thinness is required, degradation of device characteristics and reliability due to contamination of metal impurities can be prevented, and stabilize and improve the device yield. The present invention inhibits degradation of device characteristics and reliability caused by contamination of metal impurities, in a device of which lamination of device chips is required or in a device of which extreme chip thinness for an IC card and the like is required, in an attempt to cope with an enlarged capacity of the device. | 04-23-2009 |
20090108412 | SEMICONDUCTOR SUBSTRATE AND METHOD FOR MANUFACTURING A SEMICONDUCTOR SUBSTRATE - A semiconductor substrate includes: a silicon support substrate with a first crystal orientation; a silicon functional substrate which is formed on the silicon support substrate and which has a first crystalline region with a crystal orientation different from the first crystal orientation of the silicon support substrate and a second crystalline region with a crystal orientation equal to the first crystal orientation of the silicon support substrate; and a defect creation-preventing region formed at an interface between the first crystalline region and the second crystalline region of the silicon functional substrate so as to be at least elongated to a main surface of the silicon support substrate. | 04-30-2009 |
20090152685 | EPITAXIAL WAFER AND METHOD OF PRODUCING THE SAME - An epitaxial wafer comprises a silicon substrate, a gettering epitaxial film formed thereon and containing silicon and carbon, and a main silicon epitaxial film formed on the gettering epitaxial film, in which the gettering epitaxial film has a given carbon atom concentration and carbon atoms are existent between its silicon lattices. | 06-18-2009 |
20090166812 | SEMICONDUCTOR AND AN ARRANGEMENT AND A METHOD FOR PRODUCING A SEMICONDUCTOR - The present invention relates generally to semiconductors, material layers within semiconductors, a production method of semiconductors, and a manufacturing arrangement for producing semiconductors. A semiconductor according to the invention includes at least one layer with a surface, produced by laser ablation, wherein the uniform surface area to be produced includes at least an area 0.2 dm | 07-02-2009 |
20090218661 | SILICON SUBSTRATE AND MANUFACTURING METHOD THEREOF - A silicon substrate is manufactured from single-crystal silicon which is grown to have a carbon concentration equal to or higher than 1.0×10 | 09-03-2009 |
20090236699 | DISCREET PLACEMENT OF RADIATION SOURCES ON INTEGRATED CIRCUIT DEVICES - An integrated circuit and methods of forming and using the integrated circuit. The circuit includes: a radiation-emitting layer over a selected region of a top surface of an integrated circuit chip, the radiation emitting layer comprising a first polymer or resin and a first radioactive material, the region smaller than a whole of the top surface of the integrated circuit chip, the region including a circuit that is liable to temporary failure when struck by radiation generated by the first radioactive material. | 09-24-2009 |
20090267197 | SEMICONDUCTOR DEVICE FOR PREVENTING THE LEANING OF STORAGE NODES AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device for preventing the leaning of storage nodes and a method of manufacturing the same is described. The semiconductor device includes support patterns that are formed to support a plurality of cylinder type storage nodes. The support patterns are formed of a BN layer and have a hexagonal structure. The BN layer forming the support patterns has compressive stress as opposed to tensile stress and can therefore withstand cracking in the support patterns. | 10-29-2009 |
20090294918 | SEMICONDUCTOR WAFER - In a state where a semiconductor wafer is not acted upon by its own weight, a shear stress on a rear surface side portion of the semiconductor wafer is higher than that on a front surface side portion of the semiconductor wafer, in a compression direction. Thereby, sag of the semiconductor wafer is reduced when the semiconductor wafer is simple-supported in a horizontal state. | 12-03-2009 |
20100090320 | STRUCTURE AND METHOD FOR DEVICE-SPECIFIC FILL FOR IMPROVED ANNEAL UNIFORMITY - Disclosed are embodiments of a wafer that incorporates fill structures with varying configurations to provide uniform reflectance. Uniform reflectance is achieved by distributing across the wafer fill structures having different semiconductor materials such that approximately the same ratio and density between the different semiconductor materials is achieved within each region and, optimally, each sub-region. Alternatively, it is achieved by distributing across the wafer fill structures, including one or more hybrid fill structure containing varying proportions of different semiconductor materials, such that approximately the same ratio between the different semiconductor materials is achieved within each region and, optimally, each sub-region. Alternatively, it is achieved by distributing across the wafer fill structures having semiconductor materials with different thicknesses such that approximately the same overall ratio between the semiconductor material with the different thicknesses is achieved within each region and, optimally, each sub-region. | 04-15-2010 |
20100148321 | Micro-Electro-Mechanical-System Device with Particles Blocking Function and Method for Making Same - The present invention discloses a MEMS device with particles blocking function, and a method for making the MEMS device. The MEMS device comprises: a substrate on which is formed a MEMS device region; and a particles blocking layer deposited on the substrate. | 06-17-2010 |
20100181652 | SYSTEMS AND METHODS FOR STICTION REDUCTION IN MEMS DEVICES - Systems and methods for reducing stiction between elements of a microelectromechanical systems (MEMS) device during anodic bonding. The MEMS device includes a substrate cover with an optional conductor on its interior surface and the cover is anchored to a first portion of a sensing element. The MEMS device further includes a second portion of the sensing element separated from the substrate cover with a space and an antistiction element disposed between the second portion and cover. The antistiction element can be formed of a material type with high electrostatic resistance, to prevent stiction between MEMS device elements during anodic bonding. | 07-22-2010 |
20100181653 | METHOD FOR RECYCLING A SUBSTRATE, LAMINATED WATER FABRICATING METHOD AND SUITABLE RECYCLED DONOR SUBSTRATE - The invention relates to a method for recycling a substrate with a step-like residue in a first region of its surface, in particular along the edge of the substrate, which protrudes with respect to the surface of a remaining second region of the substrate, and wherein the first region comprises a modified zone, in particular an ion implanted zone, essentially in a plane corresponding to the plane of the surface of the remaining second region of the substrate and/or chamfered towards the edge of the substrate. To prevent the negative impact of contaminants in subsequent laminated wafer fabricating processes, the recycling method comprises a material removal step which is carried out such that the surface of the substrate in the first region is lying lower than the level of the modified zone before the material removal. The invention also relates to a laminated wafer fabricating method using the recycled substrate and to a recycled substrate in which the surface of a first region lies lower than the surface of the second region. | 07-22-2010 |
20100207254 | Strained semiconductor materials, devices and methods therefore - Various applications are directed to a material stack having a strained active material therein. In connection with an embodiment, an active material (e.g. a semiconductor material) is at least initially and partially released from and suspended over a substrate, strained, and held in place. The release and suspension facilitates the application of strain to the semiconductor material. | 08-19-2010 |
20100213580 | ACID-SENSITIVE, DEVELOPER-SOLUBLE BOTTOM ANTI-REFLECTIVE COATINGS - Acid-sensitive, developer-soluble bottom anti-reflective coating compositions are provided, along with methods of using such compositions and microelectronic structures formed thereof. The compositions preferably comprise a crosslinkable polymer dissolved or dispersed in a solvent system. The polymer preferably comprises recurring monomeric units having adamantyl groups. The compositions also preferably comprise a crosslinker, such as a vinyl ether crosslinking agent, dispersed or dissolved in the solvent system with the polymer. In some embodiments, the composition can also comprise a photoacid generator (PAG) and/or a quencher. The bottom anti-reflective coating compositions are thermally crosslinkable, but can be decrosslinked in the presence of an acid to be rendered developer soluble. | 08-26-2010 |
20100237475 | NEUTRALIZATION OF TRAPPED CHARGE IN A CHARGE ACCUMULATION LAYER OF A SEMICONDUCTOR STRUCTURE - A semiconductor structure. The semiconductor structure includes a semiconductor layer, a charge accumulation layer on top of the semiconductor layer, a doped region in direct physical contact with the semiconductor layer; and a device layer on and in direct physical contact with the charge accumulation layer. The charge accumulation layer includes trapped charges of a first sign. The doped region and the semiconductor layer forms a P-N junction diode. The P-N junction diode includes free charges of a second sign opposite to the first sign. The trapped charge in the charge accumulation layer exceeds a preset limit above which semiconductor structure is configured to malfunction. A first voltage is applied to the doped region. A second voltage is applied to the semiconductor layer. A third voltage is applied to the device layer. The third voltage exceeds the first voltage and the second voltage. | 09-23-2010 |
20100244203 | SEMICONDUCTOR STRUCTURE HAVING A PROTECTIVE LAYER - A semiconductor structure includes a substrate having a first nitride-based semiconductor layer. A pseudomorphic protective layer is formed on the first nitride-based semiconductor layer and a second nitride-based semiconductor layer is formed on the pseudomorphic protective layer. The pseudomorphic protective layer has a thickness that is less than a critical thickness so that it drives the material quality of the second nitride-based semiconductor layer to correspond with that of the first nitride-based semiconductor layer. | 09-30-2010 |
20100252917 | CARBOSILANE POLYMER COMPOSITIONS FOR ANTI-REFLECTIVE COATINGS - A silicon polymer material, which has a silicon polymer backbone with chromophore groups attached directly to at least a part of the silicon atoms, the polymer further exhibiting carbosilane bonds. The film forming composition and resulting coating properties can be tailored to suit the specific exposure wavelength and device fabrication and design requirements. By using two different chromophores the refractive index and the absorption co-efficient can be efficiently tuned. By varying the proportion of carbosilane bonds, and a desired Si-content of the anti-reflective coating composition can be obtained. | 10-07-2010 |
20100276788 | METHOD AND DEVICE OF PREVENTING DELAMINATION OF SEMICONDUCTOR LAYERS - Embodiments of the present invention describe a method and device of preventing delamination of semiconductor layers in a semiconductor device. The semiconductor device comprises a substrate with an interlayer dielectric (ILD). A protection layer is deposited on the ILD. Next, a getter layer is formed on the protection layer to remove any native oxides on the protection layer. A capping layer is then deposited on the getter layer to prevent oxidation of the getter layer. Next, a semiconductor layer is formed on the capping layer. An oxide layer is then deposited on the semiconductor layer. Subsequently, a buffered oxide etch solution is used to remove the oxide layer. By removing the native oxides on the protection layer, the getter layer prevents the reaction between the buffered oxide etch solution and the native oxides which may cause delamination of the semiconductor layer and protection layer. | 11-04-2010 |
20100276789 | SEMICONDUCTOR DEVICE HAVING MULTIPLE-LAYER HARD MASK WITH OPPOSITE STRESSES AND METHOD FOR FABRICATING THE SAME - A semiconductor device includes a hard mask including a first layer and a second layer in contact with each other and having opposite stress types, wherein a difference between initial stresses of the first layer and the second layer is increased so that after a thermal process, the difference between the final stresses of the first and second layer becomes smaller, to reduce the likelihood of peeling of the first or second layer. The initial stress of the first layer includes a compressive stress and the initial stress of the second layer includes a tensile stress. | 11-04-2010 |
20100314723 | MANUFACTURING OF OPTICAL STRUCTURES BY ELECTROTHERMAL FOCUSSING - This invention relates to methods and devices for the production of optical microstructures or domains in dielectric substrates based on electrothermal focussing. More specifically, the invention relates to a method of introducing a change of dielectric and/or optical properties in a region of an electrically insulating or electrically semiconducting substrate, and to substrates produced by such method. | 12-16-2010 |
20100320576 | Die-warpage compensation structures for thinned-die devices, and methods of assembling same - A back-side lamination (BSL) is applied after thinning a microelectronic die. The BSL is configured to be a thermal-expansion complementary structure to a metal wiring interconnect layout that is disposed on the active side of the microelectronic die. | 12-23-2010 |
20110006405 | SEMICONDUCTOR DEVICE, MANUFACTURE METHOD OF SEMICONDUCTOR DEVICE, AND ELECTRONIC APPARATUS - A semiconductor device includes a substrate, an electronic component and a resin member. The substrate has a first electrode. The electronic component is provided on the substrate, and has a second electrode electrically connected to the first electrode. The resin member alleviates an external stress to the second electrode of the electronic component. The resin member is disposed on the substrate at a region separated from the electronic component. | 01-13-2011 |
20110049682 | SYSTEM AND METHOD FOR SUBSTRATE WAFER BACK SIDE AND EDGE CROSS SECTION SEALS - Systems and methods for substrate wafer back side and edge cross section seals. In accordance with a first method embodiment, a silicon wafer of a first conductivity type is accessed. An epitaxial layer of the first conductivity type is grown on a front surface of the silicon wafer. The epitaxial layer is implanted to form a region of an opposite conductivity type. The growing and implanting are repeated to form a vertical column of the opposite conductivity type. The wafer may also be implanted to form a region of the opposite conductivity type vertically aligned with the vertical column. | 03-03-2011 |
20110084366 | Epitaxial Wafer and Production Method Thereof - The epitaxial layer defects generated from voids of a silicon substrate wafer containing added hydrogen are suppressed by a method for producing an epitaxial wafer by: | 04-14-2011 |
20110198736 | REACTIVE SITE DEACTIVATION AGAINST VAPOR DEPOSITION - Methods and structures relating to the formation of mixed SAMs for preventing undesirable growth or nucleation on exposed surfaces inside a reactor are described. A mixed SAM can be formed on surfaces for which nucleation is not desired by introducing a first SAM precursor having molecules of a first length and a second SAM precursor having molecules of a second length shorter than the first. Examples of exposed surfaces for which a mixed SAM can be provided over include reactor surfaces and select surfaces of integrated circuit structures, such as insulator and dielectric layers. | 08-18-2011 |
20110204489 | SILICON SUBSTRATE HAVING NANOSTRUCTURES AND METHOD FOR PRODUCING THE SAME AND APPLICATION THEREOF - A method for forming a silicon substrate having a multiple silicon nanostructures includes the steps of: providing a silicon substrate; forming an oxidization layer on the silicon substrate; immersing the silicon substrate in a fluoride solution including metal ions, thereby depositing a plurality of metal nanostructures on the silicon substrate; and immersing the silicon substrate in an etching solution to etch the silicon under the metal nanostructures, the unetched silicon forming the silicon nano structures. | 08-25-2011 |
20110215444 | PACKAGE SUBSTRATES, SEMICONDUCTOR PACKAGES HAVING THE SAME, AND METHODS OF FABRICATING THE SEMICONDUCTOR PACKAGES - A package substrate, a semiconductor package having the same, and a method for fabricating the semiconductor package. The semiconductor package includes a semiconductor chip, a package substrate, and a molding layer. The package substrate provides a region mounted with the semiconductor chip. The molding layer is configured to mold the semiconductor chip. The package substrate includes a first opening portion that provides an open region connected electrically to the semiconductor chip and extends beyond sides of the semiconductor chip to be electrically connected to the semiconductor chip. | 09-08-2011 |
20110241182 | DIE SEAL RING - An improved die seal ring is described which includes at least one break. In the region of the break in the die seal ring, the doping is modified so that the impedance of the electrical path across the break through the substrate is increased. Offsets in the break may also be used and the offset may be within a break in a track and/or between breaks in different tracks, where the die seal ring includes more than one track. | 10-06-2011 |
20110254138 | LOW-TEMPERATURE ABSORBER FILM AND METHOD OF FABRICATION - An improved low-temperature absorber, amorphous carbonitride (ACN) with an extinction coefficient (k) of greater than 0.15, and an emissivity of greater than 0.8 is disclosed. The ACN film can also be characterized as having a minimum of hydrocarbon content as observed by FTIR. The ACN film can be used as an effective absorbing layer that absorbs a wide range of electromagnetic radiation from different sources including lasers or flash lamps. A method of forming such an ACN film at a deposition temperature of less than, or equal to, 450° C. is also provided. | 10-20-2011 |
20120018855 | METHOD OF PRODUCING A HETEROSTRUCTURE WITH LOCAL ADAPTATION OF THE THERMAL EXPANSION COEFFICIENT - A method of producing a heterostructure by bonding at least one first substrate having a first thermal expansion coefficient onto a second substrate having a second thermal expansion coefficient, with the first thermal expansion coefficient being different from the second thermal expansion coefficient. Prior to bonding, trenches are formed in one of the two substrates from the bonding surface of the substrate. The trenches are filled with a material having a third thermal expansion coefficient lying between the first and second thermal expansion coefficients. | 01-26-2012 |
20120061806 | SYSTEMS AND METHODS FOR DRYING A ROTATING SUBSTRATE - A method of drying a surface of a substrate is provided. The method includes supporting a substrate; rotating the substrate about a rotational center point; applying a liquid to the substrate via a liquid dispenser; applying a drying fluid to the substrate via a drying fluid dispenser; moving the drying fluid dispenser and the liquid dispenser in a direction toward an edge region of the substrate, the drying fluid being applied closer to the rotational center point than the fluid; upon the liquid being applied to the edge region of the substrate, discontinuing application of the liquid while continuing the manipulation of the drying fluid dispenser; and upon the drying fluid being applied to the edge region of the substrate, continuing to apply the drying fluid for a predetermined period of time. | 03-15-2012 |
20120074532 | SEMICONDUCTOR PACKAGE WITH INTEGRATED METAL PILLARS AND MANUFACTURING METHODS THEREOF - A semiconductor package includes a substrate and a semiconductor device. The semiconductor device includes a body having a center, a layer disposed adjacent to the body, and a plurality of conductive pillars configured to electrically connect the semiconductor device to the substrate. The layer defines a plurality of openings. Each of the plurality of conductive pillars extends at least partially through a corresponding one of the plurality of openings. An offset between a first central axis of the each of the plurality of conductive pillars and a second central axis of the corresponding one of the plurality of openings varies with distance between the first central axis and the center of the body. The second central axis of the corresponding one of the plurality of openings is disposed between the first central axis of the each of the plurality of conductive pillars and the center of the body. | 03-29-2012 |
20120091566 | SEMICONDUCTOR APPARATUS AND METHOD OF FABRICATION FOR A SEMICONDUCTOR APPARATUS - The invention relates to a semiconductor apparatus and a method of fabrication for a semiconductor apparatus, whereby the semiconductor apparatus includes a semiconductor layer and a passivation layer arranged on a surface of the semiconductor layer and serving for passivating the semiconductor layer surface, whereby the passivation layer comprises a chemically passivating passivation sublayer and a field-effect-passivating passivation sublayer, which are arranged one above the other on the semiconductor layer surface. | 04-19-2012 |
20120119336 | METHOD FOR MANUFACTURING BONDED WAFER - A method for manufacturing a bonded wafer having a semiconductor film on a handle substrate involving the steps of: implanting ions into a semiconductor substrate to form an ion-implanted layer; subjecting the surface of at least one of the semiconductor substrate and the handle substrate to a surface activation treatment; bonding the surface of the semiconductor substrate to the surface of the handle substrate at a temperature from 50° C. to 350° C.; heating the bonded substrates at a maximum temperature from 200° C. to 350° C. to obtain a bonded body; and transferring a semiconductor film to the handle substrate by subjecting the bonded body to a temperature 30° C. to 100° C. higher than the bonding temperature, and irradiating the bonded body with visible light from a handle or semiconductor substrate side toward the ion-implanted layer of the semiconductor substrate to embrittle the interface of the ion-implanted layer. | 05-17-2012 |
20120175750 | GEOMETRY OF CONTACT SITES AT BRITTLE INORGANIC LAYERS IN ELECTRONIC DEVICES - An electronic device ( | 07-12-2012 |
20120193765 | EMISSIVITY PROFILE CONTROL FOR THERMAL UNIFORMITY - A substrate for processing in a heating system is disclosed. The substrate includes a bottom portion for absorbing heat from a radiating heat source, the bottom portion having a first region having a first emissivity and a second region having a second emissivity less than the first emissivity. The first region and the second region promote thermal uniformity of the substrate by compensating for thermal non-uniformity of the radiating heat source. | 08-02-2012 |
20120199955 | PACKAGE CARRIER AND MANUFACTURING METHOD THEREOF - A manufacturing method of a package carrier is provided. A first opening communicating an upper surface and a lower surface of a substrate is formed. A heat-conducting element having a top surface and a bottom surface is configured in the first opening and fixed into the first opening via an insulation material. A first insulation layer and a first metal layer are laminated onto the upper surface. A second insulation layer and a second metal layer are laminated onto the lower surface. A second opening and a third opening respectively exposing portions of the top and the bottom surfaces are formed. At least one through via passing through the first metal layer, the first insulation layer, the substrate, the second insulation layer and the second metal layer is formed. A third metal layer covering the first and second metal layers and an inner wall of the through via is formed. | 08-09-2012 |
20120199956 | METHOD FOR RECYCLING A SOURCE SUBSTRATE - The present invention relates to process for recycling a source substrate that has a surface region and regions in relief on the surface region, with the regions in relief corresponding to residual regions of a layer of the source substrate that were not being separated from the rest of the source substrate during a prior removal step. The process includes selective electromagnetic irradiation of the source substrate at a wavelength such that the damaged material of the surface region absorbs the electromagnetic irradiation. The present invention also relates to a recycled source substrate and to a process for transferring a layer from a source substrate recycled for this purpose. | 08-09-2012 |
20120205784 | GROWING COMPRESSIVELY STRAINED SILICON DIRECTLY ON SILICON AT LOW TEMPERATURES - Compressively strained silicon is epitaxially grown directly onto a silicon substrate at low temperature using hydrogen to engineer the strain level. Hydrogen dilution may be varied during such growth to provide a strain gradient. | 08-16-2012 |
20120280368 | LAMINATED STRUCTURE FOR SEMICONDUCTOR DEVICES - Articles are described utilizing laminated glass substrates, for example, ion-exchanged glass substrates, with flexible glass or polymers and with semiconductor devices which may be sensitive to alkali migration are described along with methods for making the articles. | 11-08-2012 |
20120280369 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE, SUBSTRATE PROCESSING APPARATUS, AND SEMICONDUCTOR DEVICE - There is provided a method for manufacturing a semiconductor device, comprising simultaneously or alternately exposing a substrate, which has two or more kinds of thin films having different elemental components laminated or exposed; and performing different modification treatments to the thin films respectively. | 11-08-2012 |
20120299160 | Method of Forming Contacts for Devices with Multiple Stress Liners - Disclosed herein is a method of forming a semiconductor device. In one example, the method includes performing a first process operation to form a first etch stop layer above a first region of a semiconducting substrate where a first type of transistor device will be formed, and forming a first stress inducing layer at least above the first etch stop layer in the first region, wherein the first stress inducing layer is adapted to induce a stress in a channel region of the first type of transistor. The method further includes, after forming the first etch stop layer, performing a second process operation form a second etch stop layer above a second region of the substrate where a second type of transistor device will be formed, and forming a second stress inducing layer at least above the second etch stop layer in the second region, wherein the second stress inducing layer is adapted to induce a stress in a channel region of the second type of transistor. In one particular example, the first and second etch stop layers may have the same approximate thickness. | 11-29-2012 |
20130134560 | SEMICONDUCTOR STRUCTURE COMPRISING MOISTURE BARRIER AND CONDUCTIVE REDISTRIBUTION LAYER - A semiconductor structure includes semiconductor devices on a substrate, a moisture barrier on the substrate surrounding the semiconductor devices, and a metal conductive redistribution layer formed over the moisture barrier. The metal conductive redistribution layer and the moisture barrier define a closed compartment containing the semiconductor devices. | 05-30-2013 |
20130200501 | IN-SITU ACTIVE WAFER CHARGE SCREENING BY CONFORMAL GROUNDING - Embodiments of the invention relate generally to semiconductor wafer technology and, more particularly, to the use of conformal grounding for active charge screening on wafers during wafer processing and metrology. A first aspect of the invention provides a method of reducing an accumulated surface charge on a semiconductor wafer, the method comprising: grounding a layer of conductive material adjacent a substrate of the wafer; and allowing a mirrored charge substantially equal in magnitude and opposite in sign to the accumulated surface charge to be induced along the conductive material. | 08-08-2013 |
20130214394 | SEMICONDUCTOR DEVICE - A field plate of a semiconductor device is provided with i) an insulating film that is formed on a surface of the semiconductor substrate, and includes a plurality of first regions, one for each of a plurality of FLR layers, that contact the layers and are arranged at intervals in a radial direction, and a plurality of second regions, one for each of the first regions, that are adjacent to the first regions in the radial direction, and ii) a plurality of first conductive films that are formed, one for each of the layers, inside of the insulating film, are arranged at intervals in the radial direction along the layers when a semiconductor substrate is viewed from above, and that are electrically connected to the layers. A thickness of at least a portion of the second regions is thicker than a thickness of the first regions. | 08-22-2013 |
20130221496 | METALLIC CARRIER FOR LAYER TRANSFER AND METHODS FOR FORMING THE SAME - Embodiments relate to semiconductor structures and methods of forming them. In some embodiments, the methods may be used to fabricate a semiconductor substrate by forming a weakened zone in a donor structure at a predetermined depth to define a transfer layer between an attachment surface and the weakened zone and a residual donor structure between the weakened zone and a surface opposite the attachment surface. A metallic layer is formed on the attachment surface and provides an ohmic contact between the metallic layer and the transfer layer, a matched Coefficient of Thermal Expansion (CTE) for the metallic layer that closely matches a CTE of the transfer layer, and sufficient stiffness to provide structural support to the transfer layer. The transfer layer is separated from the donor structure at the weakened zone to form a composite substrate comprising the transfer layer the metallic layer. | 08-29-2013 |
20130221497 | METHOD FOR THE PRODUCTION OF A SUBSTRATE COMPRISING EMBEDDED LAYERS OF GETTER MATERIAL - A method for producing a substrate with buried layers of getter material, including: making a first stack including one layer of a first getter material, arranged on a first support; making a second stack including one layer of a second getter material, arranged on a second support; and bringing the first stack into contact with the second stack and performing thermocompression, the layers of the first and of the second getter material being arranged between the first and the second support, at a temperature greater than or equal to a lowest temperature among thermal activation temperatures of the first and of the second getter material, to bond the layers of the first and second getter materials together. | 08-29-2013 |
20130228900 | Gate conductor with a diffusion barrier - A gate conductor structure is provided having a barrier region between a N-type device and a P-type device, wherein the barrier region minimizes or eliminates cross-diffusion of dopant species across the barrier region. The barrier region comprises at least one sublithographic gap in the gate conductor structure. The sublithographic gap is formed by using self-assembling copolymers to form a sublithographic patterned mask over the gate conductor structure. According to one embodiment, at least one sublithographic gap is a slit or line that traverses the width of the gate conductor structure. The sublithographic gap is sufficiently deep to minimize or prevent cross-diffusion of the implanted dopant from the upper portion of the gate conductor. According to another embodiment, the sublithographic gaps are of sufficient density that cross-diffusion of dopants is reduced or eliminated during an activation anneal such that changes in Vt are minimized. | 09-05-2013 |
20130234298 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME - According to an embodiment, a method for manufacturing a semiconductor device includes a placement step and a bonding step. The placement step faces a semiconductor active portion toward a support substrate portion via a bonding portion disposed between the semiconductor active portion and the support substrate portion. The bonding portion includes a bonding layer and a light absorption layer, absorptance of the light absorption layer for laser light being higher than or equal to absorptance of the bonding layer for the laser light. The bonding step bonds the semiconductor active portion and the support substrate portion by irradiating the light absorption layer with the laser light through the support substrate portion and melting the bonding layer by thermal conduction from the light absorption layer heated by the laser light. | 09-12-2013 |
20130277810 | METHOD FOR FORMING HEAT SINK WITH THROUGH SILICON VIAS - Semiconductor devices are formed with through silicon vias extending into the semiconductor substrate from a backside surface for improved heat dissipation. Embodiments include forming a cavity in a backside surface of a substrate, the substrate including a gate stack on a frontside surface, and filling the cavity with a thermally conductive material. | 10-24-2013 |
20130285217 | SUBSTRATE TREATING METHOD, TEMPORARY FIXING COMPOSITION AND SEMICONDUCTOR DEVICE - The invention provides a substrate treating method which can favorably prevent damages to a substrate when the substrate is separated from a support, thus achieving a high yield. The substrate treating method includes, in the sequence set forth, a step | 10-31-2013 |
20130328174 | Edge Protection of Bonded Wafers During Wafer Thinning - A method of edge protecting bonded semiconductor wafers. A second semiconductor wafer and a first semiconductor wafer are attached by a bonding layer/interface and the second semiconductor wafer undergoes a thinning process. As a part of the thinning process, a first protective layer is applied to the edges of the second and first semiconductor wafers. A third semiconductor wafer is attached to the second semiconductor wafer by a bonding layer/interface and the third semiconductor wafer undergoes a thinning process. As a part of the thinning process, a second protective layer is applied to the edges of the third semiconductor wafer and over the first protective layer. The first, second and third semiconductor wafers form a wafer stack. The wafer stack is diced into a plurality of 3D chips while maintaining the first and second protective layers. | 12-12-2013 |
20130328175 | METHOD FOR THE HYDROGEN PASSIVATION OF SEMICONDUCTOR LAYERS - The present invention relates to a method for the hydrogen passivation of semiconductor layers, wherein the passivation is effected by using an arc plasma source, to the passivated semiconductor layers produced according to the method, and to the use thereof. | 12-12-2013 |
20140001605 | MANUFACTURING METHOD OF EPITAXIAL SILICON WAFER, AND EPITAXIAL SILICON WAFER | 01-02-2014 |
20140048911 | LATERAL SEMICONDUCTOR DEVICE - A lateral semiconductor device includes a semiconductor layer, an insulating layer, and a resistive field plate. The semiconductor layer includes a first semiconductor region and a second semiconductor region at a surface portion, and the second semiconductor region makes a circuit around the first semiconductor region. The insulating layer is formed on a surface of the semiconductor layer and is disposed between the first and second semiconductor regions. The resistive field plate is formed on a surface of the insulating layer. Between the first and second semiconductor regions, a first section and a second section are adjacent to each other along a circumferential direction around the first semiconductor region. The resistive field plate includes first and second resistive field plate sections respectively formed in the first and second sections, and the first and second resistive field plate sections are separated from each other. | 02-20-2014 |
20140077342 | SEMICONDUCTOR DEVICE HAVING BURIED LAYER AND METHOD FOR FORMING THE SAME - Semiconductor devices having a buried layer and methods for forming the same are disclosed. In an exemplary method, a hard mask layer can be provided on a semiconductor substrate. The hard mask layer can have a plurality of through-openings. A plurality of deep trenches can be formed in the semiconductor substrate using the hard mask layer as a mask. A bottom of each of the plurality of deep trenches in the semiconductor substrate can be doped to form a plurality of heavily-doped regions. One or more of the plurality of heavily-doped regions can be connected to form the buried layer in the semiconductor substrate. There is thus no need to use an epitaxial process to form active regions. In addition, lateral isolation structures can be simultaneously formed in the semiconductor substrate. | 03-20-2014 |
20140117509 | Metal Deposition with Reduced Stress - Various techniques, methods and devices are disclosed where metal is deposited on a substrate, and stress caused by the metal to the substrate is limited, for example to limit a bending of the wafer. | 05-01-2014 |
20140291815 | PROCESSING A WAFER FOR AN ELECTRONIC CIRCUIT - According to a disclosed embodiment, there is provided a method of processing a silicon wafer for use in a substrate for an electronic circuit, comprising: impregnating the silicon wafer with impurities that form one or more deep energy levels within the band gap of silicon, wherein at least one of said deep energy levels is positioned at least 0.3 eV away from the conduction band if the level is a donor level or at least 0.3 eV away from the valence band if the level is an acceptor level; and pre-processing the silicon wafer, prior to or after said impregnation step, so that precipitation of oxide during, after, or during and after, said impregnating step is suppressed. | 10-02-2014 |
20140299975 | Method and Board for Growing High-Quality Graphene Layer Using High Pressure Annealing - This invention relates to a method and board for forming a graphene layer, and more particularly, to a method of forming a high-quality graphene layer using high pressure annealing and to a board used therein. The method of forming the graphene layer includes forming a reaction barrier layer on a substrate layer, forming a metal catalyst layer which functions as a catalyst for forming the graphene layer on the reaction barrier layer, subjecting a board including a stack of the layers to high pressure annealing, and growing the graphene layer on the metal catalyst layer. This board is subjected to high pressure annealing before growth of the graphene layer, and the reaction barrier layer is formed using a material having high adhesion energy to the metal catalyst layer so as to suppress migration of metal catalyst atoms. | 10-09-2014 |
20140312470 | SEAL RING STRUCTURE WITH CAPACITOR - A semiconductor device includes a semiconductor substrate of a first conductivity type having a chip region enclosed by a seal ring region. An insulating layer is on the semiconductor substrate. A seal ring structure is embedded in the insulating layer corresponding to the seal ring region. And, a plurality of doping regions are located beneath the first seal ring structure. | 10-23-2014 |
20140332934 | SUBSTRATES FOR SEMICONDUCTOR DEVICES - A method of manufacturing a composite substrate for a semiconductor device, the method comprising: selecting a substrate wafer comprising: a first layer of single crystal material suitable for epitaxial growth of a compound semiconductor thereon and having a thickness of 100 μm or less;a second layer having a thickness of no less than 0.5 μm and formed of a material having a lower thermal expansion coefficient than the first layer of single crystal material and/or is formed of a material which has a higher fracture strength than that of the first layer of single crystal material; and a third layer forming a handling wafer on which the first and second layers are disposed, wherein the substrate wafer has an aspect ratio, defined by a ratio of thickness to width, of no less than 0.25/100; growing a first polycrystalline CVD diamond layer on the first layer of single crystal material using a chemical vapour deposition technique to form a composite comprising the substrate wafer bonded to the polycrystalline diamond layer via the first layer of single crystal material, wherein during growth of the first polycrystalline CVD diamond layer a temperature difference at a growth surface between an edge and a centre point thereof is maintained to be no more than 80° C.; and removing the second and third layers of the substrate wafer to form a composite substrate comprising the polycrystalline diamond layer directly bonded to the first layer of single crystal material. | 11-13-2014 |
20150021746 | BACKSCATTERING FOR LOCALIZED ANNEALING - A method of fabricating an electronic apparatus includes forming an active layer over a wafer, forming a backscatter layer over the wafer, and directing radiation toward the wafer to anneal the active layer. The backscatter layer is not transparent to the radiation, more reflective than absorptive of the radiation, and positioned such that the backscatter layer inhibits exposure of the wafer to the radiation apart from the active layer. | 01-22-2015 |
20150028456 | Semiconductor Device, a Semiconductor Wafer Structure, and a Method for Forming a Semiconductor Wafer Structure - Embodiments relate to a semiconductor device, a semiconductor wafer structure, and a method for manufacturing or forming a semiconductor wafer structure. The semiconductor device includes a semiconductor substrate with a first region having a first conductivity type and a second region having a second conductivity type. The semiconductor device further includes an oxide structure with interrupted areas and a metal layer structure being in contact with the second region at least at the interrupted areas of the oxide. | 01-29-2015 |
20150028457 | EPITAXIAL SUBSTRATE, SEMICONDUCTOR DEVICE, AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - The present invention includes: a silicon-based substrate; and an epitaxial growth layer that has a configuration in which first and second nitride semiconductor layers having different lattice constants and thermal expansion coefficients are alternately laminated, and is arranged on the silicon-based substrate so that a film thickness thereof is gradually reduced at an outer edge portion. As a result, there are provided an epitaxial substrate and a semiconductor device in which generation of cracks at the outer edge portion is suppressed, and a method for manufacturing the semiconductor device. | 01-29-2015 |
20150054141 | METHOD FOR FORMING INTEGRATED CIRCUITS ON A STRAINED SEMICONDUCTOR SUBSTRATE - An electronic circuit on a strained semiconductor substrate, includes: electronic components on a first surface of a semiconductor substrate; and at least portions of a layer of a porous semiconductor material on the side of a second surface of the semiconductor substrate, opposite to the first surface, to bend the semiconductor substrate. | 02-26-2015 |
20150069584 | SEMICONDUCTOR STRUCTURE - A semiconductor structure includes a carrier, a first protective layer, a second protective layer, and a third protective layer. A first surface of the first protective layer comprises a first anti-stress zone. A first extension line from a first bottom edge intersects with a second extension line from a second bottom edge to form a first base point. A first projection line is formed on the first surface, an extension line of the first projection line intersects with the second bottom edge to form a first intersection point, a second projection line is formed on the first surface, and an extension line of the second projection line intersects with the first bottom edge to form a second intersection point. A zone by connecting the first base point, the first intersection point and the second intersection point is the first anti-stress zone. | 03-12-2015 |
20150102470 | Semiconductor Film with Adhesion Layer and Method for Forming the Same - Presented herein is a method for forming a semiconductor film using an adhesion layer, comprising providing an oxide layer disposed over a substrate, forming at least one adhesion layer over the oxide layer, and forming a film layer over the at least one adhesion layer in a same process step as the forming the at least one adhesion layer. Forming the at least one adhesion layer further comprises at least forming a first adhesion layer over the oxide layer and forming a second adhesion layer over the first adhesion layer. Forming the first adhesion layer comprises providing the terminating gas at a substantially constant first flow rate, and wherein the forming the second adhesion layer comprises ramping a flow rate of the terminating gas to a zero flow rate from the first flow rate. | 04-16-2015 |
20150102471 | SEMICONDUCTOR-ON-INSULATOR STRUCTURE AND METHOD OF FABRICATING THE SAME - Methods for forming a layer of semiconductor material are provided. A substrate is provided. An amorphous layer is formed over the substrate, where the amorphous layer includes a semiconductor or a semiconductor alloy. A seed wafer is bonded to the amorphous layer, where the seed wafer includes a crystalline semiconductor structure. A solid-phase epitaxial (SPE) growth process is performed to crystallize the amorphous layer, where the SPE growth process uses the crystalline semiconductor structure of the seed wafer as a crystal template. The seed wafer is debonded from the structure. | 04-16-2015 |
20150357293 | SEMICONDUCTOR DEVICE - A semiconductor device is a semiconductor device in which one chip region is formed through divided exposure. An interlayer insulating film has a via and an interconnection trench in an element formation region and has a guard ring hole in a guard ring region. An interconnection conductive layer is formed in the via and the interconnection trench. A guard ring conductive layer is formed in the guard ring hole. A minimum dimension of a width of the guard ring conductive layer is greater than a minimum dimension of a width of the interconnection conductive layer in the via. | 12-10-2015 |
20150364324 | NANOCRYSTAL THIN FILM FABRICATION METHODS AND APPARATUS - Nanocrystal thin film devices and methods for fabricating nanocrystal thin film devices are disclosed. The nanocrystal thin films are diffused with a dopant such as Indium, Potassium, Tin, etc. to reduce surface states. The thin film devices may be exposed to air during a portion of the fabrication. This enables fabrication of nanocrystal-based devices using a wider range of techniques such as photolithography and photolithographic patterning in an air environment. | 12-17-2015 |