Class / Patent application number | Description | Number of patent applications / Date published |
257595000 | VOLTAGE VARIABLE CAPACITANCE DEVICE | 48 |
20080265372 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - The bottom side of an N type silicon substrate is connected to a power supply terminal, a second P type epitaxial layer is formed on all sides of the N type silicon substrate, and a device forming portion is provided on the second P type epitaxial layer. A first P type epitaxial layer and an interlayer insulating film are provided on the device forming portion and an N well and a P well are formed on the top surface of the first P type epitaxial layer. The second P type epitaxial layer is connected to a ground terminal via the first P type epitaxial layer, the P well, a p | 10-30-2008 |
20080265373 | SEMICONDUCTOR DEVICE - An epitaxial layer is formed in a main surface of a semiconductor substrate of a first conductivity type. The epitaxial layer is partitioned into a first area and a second area by a device isolation area. A PN junction portion, which has a semiconductor layer of a second conductivity type and configures a variable capacitance element, is provided at the surface of the epitaxial layer of the first area. A PN junction portion, which has a semiconductor layer of the second conductivity type whose low portion is formed closer to the semiconductor substrate than the semiconductor layer of the second conductivity type configuring the above variable capacitive PN junction and which is configured as a fixed capacitance, is provided at the surface of the epitaxial layer of the second area. | 10-30-2008 |
20100006981 | CAPACITANCE ARRANGEMENT AND METHOD RELATING THERETO - A capacitance arrangement comprising at least one parallel-plate capacitor comprising a first electrode means, a dielectric layer and a second electrode means partly overlapping each other. A misalignment limit is given. Said first electrode means comprises a first and a second electrode arranged symmetrically with respect to a longitudinal axis, said first and second electrodes have a respective first edge, which face each other, are linear and parallel such that a gap is defined there between. Said second electrode means comprises a third electrode with a first section and a second section disposed on opposite sides of said gap interconnected by means of an intermediate section, which is delimited by a function depending on a first parameter and a second parameter. One of said two parameters is adapted to be selected hence allowing calculation of the other parameter to determine the shape and size of the second electrode means. | 01-14-2010 |
20100019351 | VARACTORS WITH ENHANCED TUNING RANGES - A varactor may have a first terminal connected to a gate. The gate may be formed from a p-type polysilicon gate conductor. The gate may also have a gate insulator formed from a layer of insulator such as silicon oxide. The gate insulator may be located between the gate conductor and a body region. Source and drain contact regions may be formed in a silicon body region. The body region and the source and drain may be doped with n-type dopant. The varactor may have a second terminal connected to the n-type source and drain. A control voltage may be used to adjust the level of capacitance produced by the varactor between the first and second terminals. A positive control voltage may produce a larger capacitance than a negative control voltage. Application of the negative control voltage may produce a depletion layer in the p+ polysilicon gate layer. | 01-28-2010 |
20100176489 | Microelectromechanical systems structures and self-aligned harpss fabrication processes for producing same - Disclosed are one-port and two-port microelectromechanical structures including variable capacitors, switches, and filter devices. High aspect-ratio micromachining is used to implement low-voltage, large value tunable and fixed capacitors, and the like. Tunable capacitors can move in the plane of the substrate by the application of DC voltages and achieve greater than 240 percent of tuning. Exemplary microelectromechanical apparatus comprises a single crystalline silicon substrate, and a conductive structure laterally separated from the single crystalline silicon substrate by first and second high aspect ratio gaps of different size, wherein at least one of the high aspect ratio gaps has an aspect ratio of at least 30:1, and is vertically anchored to the single crystalline silicon substrate by way of silicon nitride. | 07-15-2010 |
20110031588 | VARACTOR STRUCTURE AND METHOD - An improved varactor diode ( | 02-10-2011 |
20110062555 | SEMICONDUCTOR STRUCTURE HAVING VARACTOR WITH PARALLEL DC PATH ADJACENT THERETO - A semiconductor structure includes a semiconductor substrate having a first region of a first polarity and a second region of a second polarity adjacent to the first region; and a first terminal including: a first deep trench located in the first region, a first node dielectric abutting all but an upper portion of sidewalls and a bottom of the first deep trench; a first conductive inner electrode inside the first node dielectric and electrically insulated from the first region by the first node dielectric; and a first electrical contact electrically coupling the first conductive inner electrode to the first region. | 03-17-2011 |
20110108952 | MEMORY CAPACITOR MADE FROM FIELD CONFIGURABLE ION-DOPED MATERIALS - A memory capacitor based on a field configurable ion-doped polymer is reported. The device can be dynamically and reversibly programmed to analog capacitances with low-voltage (<5 V) pulses. After the device is programmed to a specific value, its capacitance remains nonvolatile. The field configurable capacitance is attributed to the modification of ionic dopant concentrations in the polymer. The ion and dipole concentrations in the ion conductive layer can be modified when the voltage biases applied to the electrodes exceeds a threshold value and can operate as a conventional capacitor when a voltage less than the threshold value is applied. The ion conductive layer will remain at a stable value after the device is modified without applying external voltage. The device has a nonvolatile memory function even when the external voltage is turned off. The memory capacitors may be used for analog memory, nonlinear analog and neuromorphic circuits. | 05-12-2011 |
20110260293 | VARIABLE CAPACITANCE DEVICE AND METHOD OF FABRICATING THE SAME - Provided is a variable capacitance device including a nanomaterial layer made of a plurality of kinds of nanomaterials having characteristics different from each other, a first conductive layer electrically connected to at least a part of the nanomaterial layer, and a second conductive layer facing the nanomaterial layer and the first conductive layer through an insulating film. | 10-27-2011 |
20110278700 | INTERNAL MATCHING TRANSISTOR - An internal matching transistor comprises: a conductive base material including a groove, a first region, and a second region which is located opposite to the first region across the groove; a transistor bonded onto the first region of the base material; an internal matching circuit bonded onto the second region of the base material; a wire connecting the transistor to the internal matching circuit across above the groove; and a conductive or non-conductive material located between the wire and the groove, wherein capacitance between the wire and the base material is adjusted by the material. | 11-17-2011 |
20120032304 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - It is an object of the present invention to manufacture a micromachine having a plurality of structural bodies with different functions and to shorten the time required for sacrifice layer etching in a process of manufacturing the micromachine. Another object of the present invention is to prevent a structural layer from being attached to a substrate after the sacrifice layer etching. In other words, an object of the present invention is to provide an inexpensive and high-value-added micromachine by improving throughput and yield. The sacrifice layer etching is conducted in multiple steps. In the multiple steps of the sacrifice layer etching, a part of the sacrifice layer that does not overlap with the structural layer is removed by the earlier sacrifice layer etching and a part of the sacrifice layer that is under the structural layer is removed by the later sacrifice layer etching. | 02-09-2012 |
20120205781 | SEMICONDUCTOR STRUCTURE HAVING VARACTOR WITH PARALLEL DC PATH ADJACENT THERETO - A semiconductor structure includes a semiconductor substrate having a first region of a first polarity and a second region of a second polarity adjacent to the first region; and a first terminal including: a first deep trench located in the first region, a first node dielectric abutting all but an upper portion of sidewalls and a bottom of the first deep trench; a first conductive inner electrode inside the first node dielectric and electrically insulated from the first region by the first node dielectric; and a first electrical contact electrically coupling the first conductive inner electrode to the first region. | 08-16-2012 |
20130140678 | INSULATOR LAYER BASED MEMS DEVICES - The present invention relates to using an insulator layer between two metal layers of a semiconductor die to provide a micro-electromechanical systems (MEMS) device, such as an ohmic MEMS switch or a capacitive MEMS switch. In an ohmic MEMS switch, the insulator layer may be used to reduce metal undercutting during fabrication, to prevent electrical shorting of a MEMS actuator to a MEMS cantilever, or both. In a capacitive MEMS switch, the insulator layer may be used as a capacitive dielectric between capacitive plates, which are provided by the two metal layers. A fixed capacitive element may be provided by the insulator layer between the two metal layers. In one embodiment of the present invention, an ohmic MEMS switch, a capacitive MEMS switch, a fixed capacitive element, or any combination thereof may be integrated into a single semiconductor die. | 06-06-2013 |
20130200494 | VARIABLE CAPACITANCE CHAMBER COMPONENT INCORPORATING A SEMICONDUCTOR JUNCTION AND METHODS OF MANUFACTURING AND USING THEREOF - A replaceable chamber element for use in a plasma processing system, such as a plasma etching system, is described. The replaceable chamber element includes a chamber component configured to be exposed to plasma in a plasma processing system, wherein the chamber component is fabricated to include a semiconductor junction, and wherein a capacitance of the chamber component is varied when a voltage is applied across the semiconductor junction. | 08-08-2013 |
20130320501 | VARACTORS INCLUDING INTERCONNECT LAYERS - In an embodiment of the present invention is provided a varactor comprising a substrate, a plurality of bottom electrodes positioned on a surface of the substrate separated to form a gap therein, a tunable dielectric material positioned on the surface of the substrate and within the gap, the tunable dielectric at least partially overlaying the plurality of electrodes, and a top electrode in contact with the tunable dielectric. | 12-05-2013 |
20140217552 | VARIABLE CAPACITANCE DEVICE - A variable capacitance device includes a fixed substrate, a movable portion, driving electrodes, an RF capacitance electrode and an insulating film. The movable portion faces the fixed substrate and can change a gap between the movable portion and the fixed substrate. The driving electrodes are formed on the fixed substrate so as to face the movable portion. The RF capacitance electrode is formed on the fixed substrate so as to face the movable portion and be spaced apart from the driving electrodes. The insulating film is formed between the movable portion and the driving electrodes. The level of a voltage applied to the driving electrodes and the level of a voltage applied to the movable portion are periodically switched and the level of a voltage applied to the RF capacitance electrode and the level of a voltage applied to the movable portion are always the same. | 08-07-2014 |
20140367831 | VARIABLE CAPACITANCE DEVICES - A variable capacitance device includes a capacitor having a first capacitance and a variable resistor coupled in series with the capacitor. The variable resistor includes a gate structure formed over a channel region defined in a doped well formed in a semiconductor substrate. A resistance of the variable resistor is based on a voltage applied to the gate structure, which adjusts a resistance of the channel and a capacitance of the variable capacitance device. | 12-18-2014 |
257596000 | With specified dopant profile | 11 |
20090001518 | Varactor - A varactor comprising a first layer separated from a second layer by an insulating layer, wherein the first layer is a first type of semiconductor material and the second layer is a second type of semiconductor material and the insulation layer is arranged to allow an accumulation region to be formed in the first layer and second layer when a positive bias is applied to the first layer and the second layer and a depletion region to be formed in the first layer and second layer when a negative bias is applied to the first layer and the second layer. | 01-01-2009 |
20090289329 | Differential Varactor - A high-Q differential varactor includes reduced inner spacing dimensions between differential fingers. | 11-26-2009 |
20100059859 | VARACTOR STRUCTURE AND METHOD - An improved varactor diode ( | 03-11-2010 |
20100059860 | COUNTER-DOPED VARACTOR STRUCTURE AND METHOD - An improved varactor diode ( | 03-11-2010 |
20110140240 | VARACTOR DIODES - An improved varactor diode is obtained by providing a substrate having a first surface and in which are formed a first N region having a first peak dopant concentration located at a first depth beneath the surface, and a first P region having a second peak dopant concentration greater than the first peak dopant concentration located at a second depth beneath the surface less than the first depth, and a second P region having a third peak dopant concentration greater than the second peak dopant concentration and located at a third depth at or beneath the surface less than the second depth, so that the first P region provides a retrograde doping profile whose impurity concentration increases with distance from the inward edge of the second P region up to the second peak dopant concentration. | 06-16-2011 |
20120146188 | PN-JUNCTION VARACTOR IN A BICMOS PROCESS AND MANUFACTURING METHOD OF THE SAME - A PN-junction varactor in a BiCMOS process is disclosed which comprises an N-type region, a P-type region and N-type pseudo buried layers. Both of the N-type and P-type regions are formed in an active area and contact with each other, forming a PN-junction; the P-type region is situated on top of the N-type region. The N-type pseudo buried layers are formed at bottom of shallow trench field oxide regions on both sides of the active area and contact with the N-type region; deep hole contacts are formed on top of the N-type pseudo buried layers in the shallow trench field oxide regions to pick up the N-type region. A manufacturing method of PN-junction varactor in a BiCMOS process is also disclosed. | 06-14-2012 |
20130313683 | SEMICONDUCTOR WIRE-ARRAY VARACTOR STRUCTURES - Semiconductor variable capacitor (varactor) devices are provided, which are formed with an array of radial p-n junction structures to provide improved dynamic range and sensitivity. For example, a semiconductor varactor device includes a doped semiconductor substrate having first and second opposing surfaces and an array of pillar structures formed on the first surface of the doped semiconductor substrate. Each pillar structure includes a radial p-n junction structure. A first metallic contact layer is conformally formed over the array of pillar structures on the first surface of the doped semiconductor substrate. A second metallic contact layer formed on the second surface of the doped semiconductor substrate. An insulating layer is formed on the doped semiconductor substrate surrounding the array of pillar structures. | 11-28-2013 |
20160133758 | DUAL STACK VARACTOR - Embodiments include apparatuses and methods related to vertically stacked varactors. Specifically two varactors may be constructed of vertically stacked layers including an anode layer, a contact layer, and a varactor layer. The two varactors may share one or more layers in common and may be electrically coupled to form a parallel varactor pair. In some embodiments the two varactors may share the anode layer in common, while in other embodiments the two varactors may share the contact layer in common. The parallel varactor pair may be advantageous in reducing die area for compound varactor circuits. | 05-12-2016 |
257597000 | Retrograde dopant profile (e.g., dopant concentration decreases with distance from rectifying junction) | 3 |
20080290465 | Varactor Element and Low Distortion Varactor Circuit Arrangement - A varactor element having a junction region, in which the depletion capacitance of the varactor element varies when a reverse bias voltage is applied to the varactor element. The varactor element has an exponential depletion capacitance-voltage relation, e.g. obtained by providing a predetermined doping profile in the junction region. The varactor element can be used in a narrow tone spacing varactor stack arrangement, in which two varactor elements are connected in an anti-series configuration. A low impedance path for base band frequency components between a control node and each of two RF connection nodes is provided, while for fundamental and higher order harmonic frequencies, a high impedance path is provided. | 11-27-2008 |
20090079032 | METHOD OF FORMING A HIGH CAPACITANCE DIODE AND STRUCTURE THEREFOR - In one embodiment, high doped semiconductor channels are formed in a semiconductor region of an opposite conductivity type to increase the capacitance of the device. | 03-26-2009 |
20140367832 | Three-terminal Variable Capacitor - A novel semiconductor variable capacitor is presented. The semiconductor structure is simple and is based on a semiconductor variable MOS capacitor structure suitable for integrated circuits, which has at least three terminals, one of which is used to modulate the equivalent capacitor area of the MOS structure by increasing or decreasing its DC voltage with respect to another terminal of the device, in order to change the capacitance over a wide ranges of values. Furthermore, the present invention decouples the AC signal and the DC control voltage minimizing the distortion and increasing the performance of the device, such as its control characteristic. The present invention is simple and only slightly dependent on the variations due to the fabrication process. It exhibits a high value of capacitance density and, if opportunely implemented, shows a quasi linear dependence of the capacitance value with respect to the voltage of its control terminal. | 12-18-2014 |
257598000 | With plural junctions whose depletion regions merge to vary voltage dependence | 4 |
20080246119 | LARGE TUNING RANGE JUNCTION VARACTOR - Large tuning range junction varactor includes first and second junction capacitors coupled in parallel between first and second varactor terminals. First and second plates of the capacitors are formed by three alternating doped regions in a substrate. The first and third doped regions are of the same type sandwiching the second doped region of the second type. A first input terminal is coupled to the first and third doped regions and a second terminal is coupled to the second doped region. At the interfaces of the doped regions are first and second depletion regions whose width can be varied by varying the voltage across the terminals from zero to full reverse bias. | 10-09-2008 |
20090079033 | LATERAL JUNCTION VARACTOR WITH LARGE TUNING RANGE - Large tuning range junction varactor includes first and second junction capacitors coupled in parallel between first and second varactor terminals. First and second plates of the capacitors are formed by three alternating doped regions in a substrate. The second and third doped regions are of the same type sandwiching the first doped region of the second type. A first varactor terminal is coupled to the second and third doped regions and a second varactor terminal is coupled to the first doped region. At the interfaces of the doped regions are first and second depletion regions, the widths of which can be varied by varying the voltage across the terminals from zero to full reverse bias. At zero bias condition, junction capacitance (C | 03-26-2009 |
20090315147 | SEMICONDUCTOR CHIP AND SEMICONDUCTOR DEVICE - A wire embedded in a semiconductor substrate is covered with an insulating film, and a bias voltage is applied to the semiconductor substrate or to the wire to form a depletion layer extending from an edge of the insulating film. Alternatively, a semiconductor layer having a different conductivity type from the semiconductor substrate is formed within the semiconductor substrate to surround the insulating film. | 12-24-2009 |
20100258910 | LATERAL JUNCTION VARACTOR WITH LARGE TUNING RANGE - Large tuning range junction varactor includes first and second junction capacitors coupled in parallel between first and second varactor terminals. First and second plates of the capacitors are formed by three alternating doped regions in a substrate. The second and third doped regions are of the same type sandwiching the first doped region of the second type. A first varactor terminal is coupled to the second and third doped regions and a second varactor terminal is coupled to the first doped region. At the interfaces of the doped regions are first and second depletion regions, the widths of which can be varied by varying the voltage across the terminals from zero to full reverse bias. At zero bias condition, junction capacitance (C | 10-14-2010 |
257599000 | With means to increase active junction area (e.g., grooved or convoluted surface) | 3 |
20090200642 | HIGHLY TUNABLE METAL-ON-SEMICONDUCTOR TRENCH VARACTOR - An array of deep trenches is formed in a doped portion of the semiconductor substrate, which forms a lower electrode. A dielectric layer is formed on the sidewalls of the array of deep trenches. The array of deep trenches is filled with a doped semiconductor material to form an upper electrode comprising a top plate portion and a plurality of extension portions into the array of trenches. In a depletion mode, the bias condition across the dielectric layer depletes majority carriers within the top electrode, thus providing a low capacitance. In an accumulation mode, the bias condition attracts majority carriers toward the dielectric layer, providing a high capacitance. Thus, the trench metal-oxide-semiconductor (MOS) varactor provides a variable capacitance depending on the polarity of the bias. | 08-13-2009 |
20160079444 | COMPOUND VARACTOR - Embodiments include apparatuses and methods related to a compound varactor. A first varactor in the compound varactor may include a collector layer and a first base layer that is arranged in a first plurality of parallel fingers. A second varactor in the compound varactor may include a second base layer arranged in a second plurality of parallel fingers, and the base layer may be coupled with the collector layer. In embodiments, the fingers of the base layers of the first varactor and the second varactor may be interleaved with one another. Other embodiments may be disclosed or claimed herein. | 03-17-2016 |
20160087111 | NANO STRUCTURED PARAELECTRIC OR SUPERPARAELECTRIC VARACTORS FOR AGILE ELECTRONIC SYSTEMS - An electronic device in the form a two-dimensional array of nanopillars extending generally normal to a substrate is provided. The nanopillars are made from a paraelectric or superparaelectric material. In addition, a linear dielectric medium is located between individual nanopillars. A two-dimensional array of paraelectric or superparaelectric nanopillars and a linear dielectric medium form the effective dielectric medium of a paraelectric or superparaelectric varactor. In some instances, the nanopillars are cylindrical nanopillars that have an average diameter and/or average height/length between 1-300 nanometers. In other instances, the nanopillars are quasi-nanoparticles that form self-aligned nano-junctions. In addition, each of the nanopillars has a single paraelectric or superparaelectric dipole domain therewithin. As such, each of the nanopillars can be void of crystallographic defects, polycrystallinity, interactions between ferroic domains, and defects due to ferroic domain walls. | 03-24-2016 |
257600000 | With physical configuration to vary voltage dependence (e.g., mesa) | 3 |
20100155897 | DEEP TRENCH VARACTORS - A deep trench varactor structure compatible with a deep trench capacitor structure and methods of manufacturing the same are provided. A buried plate layer is formed on a second deep trench, while the first trench is protected from formation of any buried plate layer. The inside of the deep trenches is filled with a conductive material to form inner electrodes. At least one doped well is formed outside and abutting portions of the first deep trench and constitutes at least one outer varactor electrode. Multiple doped wells may be connected in parallel to provide a varactor having complex voltage dependency of capacitance. The buried plate layer and another doped well connected thereto constitute an outer electrode of a linear capacitor formed on the second deep trench. | 06-24-2010 |
20140284767 | MEMS ELEMENT - According to one embodiment, there is disclosed a MEMS element. The MEMS element includes a lower electrode having a surface on which a plurality of minute convex portions are formed. A plurality of dielectric bumps are provided on the upper surface of the lower electrode and are thicker than heights of the convex portions. A dielectric layer is provided on the dielectric bumps and the lower electrode. An upper electrode is provided above the dielectric layer. The upper electrode is movable so as to vary capacitance between the upper electrode and the lower electrode. | 09-25-2014 |
20150035122 | Micro-Electro-Mechanical System (MEMS) Structures And Design Structures - Micro-Electro-Mechanical System (MEMS) structures, methods of manufacture and design structures are disclosed. The method includes forming at least one fixed electrode on a substrate. The method further includes forming a Micro-Electro-Mechanical System (MEMS) beam with a varying width dimension, as viewed from a top of the MEMS beam, over the at least one fixed electrode. | 02-05-2015 |
257601000 | Plural diodes in same non-isolated structure, or device having three or more terminals | 1 |
20080203537 | Differential Junction Varactor - Structure and methods for a differential junction varactor. The structure includes: a silicon first region formed in a silicon substrate, the first region of a first dopant type; and a plurality of silicon second regions in physical and electrical contact with the first region, the plurality of second regions spaced apart and not in physical contact with each other, the plurality of second regions of a second dopant type, the first dopant type different from the second dopant type; a cathode terminal electrically connected to the first region; a first anode terminal electrically connected to a first set of second regions of the plurality of second regions; and a second anode terminal electrically connected to a second set of second silicon regions of the plurality of second regions, second regions of the first set of second regions alternating with second regions of the second set of second regions. | 08-28-2008 |
257602000 | With specified housing or contact | 9 |
20080315362 | Micro-Electro-Mechanical System Varactor - A micro-electro-mechanical system varactor. The varactor includes a substrate, a lower bias conductor partially overlaying the substrate, a first signal conductor partially overlaying the substrate, a dielectric layer at least partially overlaying the first signal conductor, a support structure coupled to the substrate, and a flexible structure coupled to the support structure. The flexible structure is suspended over the substrate, includes an upper bias conductor overlaying at least part of the lower bias conductor and a top conductor overlaying at least part of the first signal conductor, configured to deflect in response to a bias voltage applied between the upper bias conductor and the lower bias conductor, and configured for separation between the top conductor and the dielectric layer by a varying separation distance dependent upon the bias voltage. | 12-25-2008 |
20090091000 | Varactores including interconnect layers - In an embodiment of the present invention is provided a varactor comprising a substrate, a plurality of bottom electrodes positioned on a surface of the substrate separated to form a gap therein, a tunable dielectric material positioned on the surface of the substrate and within the gap, the tunable dielectric at least partially overlaying the plurality of electrodes, and a top electrode in contact with the tunable dielectric. | 04-09-2009 |
20100237468 | ON-CHIP CAPACITORS WITH A VARIABLE CAPACITANCE FOR A RADIOFREQUENCY INTEGRATED CIRCUIT - On-chip capacitors with a variable capacitance, as well as design structures for a radio frequency integrated circuit, and method of fabricating and method of tuning on-chip capacitors. The on-chip capacitor includes first and second ports powered with opposite polarities, first and second electrodes, and first and second voltage-controlled units. Each of the first and second voltage-controlled units is switched between a first state in which the first and second electrodes are electrically isolated from the first and second ports and a second state. When the first voltage-controlled unit is switched to the second state, the first electrode is electrically connected with the first port. When the second voltage-controlled unit is switched to the second state the second electrode is electrically connected with the second port. The on-chip capacitor has a larger capacitance value when the first and second voltage-controlled units are in the second state. | 09-23-2010 |
20110147894 | LOW CAPACITANCE SEMICONDUCTOR DEVICE - A semiconductor device includes a diode, a passivation layer and a conductive layer. The diode includes an epitaxial layer on a semiconductor substrate, and first and second diode contacts on different planes. The passivation layer has a planar top surface, and includes multiple consecutive layers of a benzocyclobutene (BCB) material formed on the diode, an aggregate thickness of the passivation layer exceeding a thickness of the epitaxial layer. The conductive layer is formed on the top surface of passivation layer, the conductive layer connecting with the first and the second diodes contact through first and second openings in the passivation layer, respectively. The passivation layer enhances a capacitive isolation between the conductive layer and the diode. | 06-23-2011 |
20130113081 | QUANTUM CAPACITANCE GRAPHENE VARACTORS AND FABRICATION METHODS - A plate varactor includes a dielectric substrate and a first electrode embedded in a surface of the substrate. A capacitor dielectric layer is disposed over the first electrode, and a layer of graphene is formed over the dielectric layer to contribute a quantum capacitance component to the dielectric layer. An upper electrode is formed on the layer of graphene. Other embodiments and methods for fabrication are also included. | 05-09-2013 |
20130234293 | SEMICONDUCTOR CERAMIC AND METHOD FOR MANUFACTURING THE SAME, AND LAMINATED SEMICONDUCTOR CERAMIC CAPACITOR WITH VARISTOR FUNCTION AND METHOD FOR MANUFACTURING THE SAME - A semiconductor ceramic contains a donor element solid-solved in crystal grains of a SrTiO | 09-12-2013 |
20140332928 | Digital Semiconductor Variable Capacitor - A novel semiconductor variable capacitor is presented. The semiconductor structure is simple and is based on a semiconductor variable capacitor with MOS compatible structure suitable for integrated circuits, which has at least three terminals, one of which is used to modulate the capacitance value between the other two terminals of the device, by increasing or decreasing its DC voltage with respect to one of the main terminals of the device. Furthermore, the present invention decouples the AC signal and the DC control voltage preventing distortion of the RF signal. The present invention describes a controllable capacitor whose capacitance value is not necessarily linear with its control voltage, but although possibly abrupt in its characteristic, is utilized to manufacture a semiconductor variable capacitor with digital control to improve its noise and linearity performance while maintaining high quality factor. | 11-13-2014 |
20150325573 | DUAL STACK VARACTOR - Embodiments include apparatuses and methods related to vertically stacked varactors. Specifically two varactors may be constructed of vertically stacked layers including an anode layer, a contact layer, and a varactor layer. The two varactors may share one or more layers in common. In some embodiments the two varactors may share the anode layer in common, while in other embodiments the two varactors may share the contact layer in common. | 11-12-2015 |
20160126017 | STRESS CONTROL DURING PROCESSING OF A MEMS DIGITAL VARIABLE CAPACITOR (DVC) - The present invention generally relates to a MEMS digital variable capacitor (DVC) ( | 05-05-2016 |