Class / Patent application number | Description | Number of patent applications / Date published |
257586000 | With non-planar semiconductor surface (e.g., groove, mesa, bevel, etc.) | 28 |
20080203536 | BIPOLAR TRANSISTOR USING SELECTIVE DIELECTRIC DEPOSITION AND METHODS FOR FABRICATION THEREOF - A bipolar transistor structure and related methods for fabrication thereof are provided. A vertical spacer layer is selectively deposited after implanting an extrinsic base region into a semiconductor substrate while using an ion implantation mask located upon a screen dielectric layer located upon the semiconductor substrate. A portion of the ion implantation mask may remain embedded and aligned within a sidewall of an aperture within the vertical spacer layer. The selective deposition of the vertical spacer layer allows for a reduced thermal budget and reduced process complexity when fabricating the bipolar transistor. | 08-28-2008 |
20080315361 | Semiconductor Device and Method of Manufacturing the Same - The invention relates to a semiconductor device ( | 12-25-2008 |
20090121319 | POWER SEMICONDUCTOR DEVICES WITH MESA STRUCTURES AND BUFFER LAYERS INCLUDING MESA STEPS - A bipolar junction transistor includes a collector having a first conductivity type, a drift layer having the first conductivity type on the collector, a base layer on the drift layer and having a second conductivity type opposite the first conductivity type, a lightly doped buffer layer having the first conductivity type on the base layer and forming a p-n junction with the base layer, and an emitter mesa having the first conductivity type on the buffer layer and having a sidewall. The buffer layer includes a mesa step adjacent to and spaced laterally apart from the sidewall of the emitter mesa, and a first thickness of the buffer layer beneath the emitter mesa is greater than a second thickness of the buffer layer outside the mesa step. | 05-14-2009 |
20090179303 | Vertical Bipolar Transistor - A vertical heterobipolar transistor comprising a substrate of semiconductor material of a first conductivity type and an insulation region provided therein, a first semiconductor electrode arranged in an opening of the insulation region and comprising monocrystalline semiconductor material of a second conductivity type, which is either in the form of a collector or an emitter, and which has a first heightwise portion and an adjoining second heightwise portion which is further away from the substrate interior in a heightwise direction, wherein only the first heightwise portion is enclosed by the insulation region in lateral directions perpendicular to the heightwise direction, a second semiconductor electrode of semiconductor material of the second conductivity type, which is in the form of the other type of semiconductor electrode, a base of monocrystalline semiconductor material of the first conductivity type, and a base connection region having a monocrystalline portion which in a lateral direction laterally surrounds the second heightwise portion, which is further towards the substrate interior as viewed from the base, of the first semiconductor electrode, and which rests with its underside directly on the insulation region. | 07-16-2009 |
20100032804 | HIGH VOLTAGE BIPOLAR TRANSISTOR AND METHOD OF FABRICATION - High voltage bipolar transistors built with a BiCMOS process sequence exhibit reduced gain at high current densities due to the Kirk effect. Threshold current density for the onset of the Kirk effect is reduced by the lower doping density required for high voltage operation. The widened base region at high collector current densities due to the Kirk effect extends laterally into a region with a high density of recombination sites, resulting in an increase in base current and drop in the gain. The instant invention provides a bipolar transistor in an IC with an extended unsilicided base extrinsic region in a configuration that does not significantly increase a base-emitter capacitance. Lateral extension of the base extrinsic region may be accomplished using a silicide block layer, or an extended region of the emitter-base dielectric layer. A method of fabricating an IC with the inventive bipolar transistor is also disclosed. | 02-11-2010 |
20100127352 | SELF-ALIGNED BIPOLAR TRANSISTOR STRUCTURE - A bipolar transistor structure comprises a semiconductor substrate having a first conductivity type, a collector region having a second conductivity type that is opposite the first conductivity type formed in a substrate active device region defined by isolation dielectric material formed in an upper surface of the semiconductor substrate, a base region that includes an intrinsic base region having the first conductivity type formed over the collector region and an extrinsic base region having the second conductivity type formed over the isolation dielectric material, and a sloped in-situ doped emitter plug having the second conductivity type formed on the intrinsic base region. | 05-27-2010 |
20100187656 | Bipolar Junction Transistors and Methods of Fabrication Thereof - Design and methods for fabricating bipolar junction transistors are described. In one embodiment, a semiconductor device includes a first fin comprising a first emitter region, a first base region, and a first collector region. The first emitter region, the first base region, and the first collector region form a bipolar junction transistor. A second fin is disposed adjacent and parallel to the first fin. The second fin includes a first contact to the first base region. | 07-29-2010 |
20110012232 | BIPOLAR TRANSISTOR - An improved device ( | 01-20-2011 |
20110115054 | SEMISPHERICAL INTEGRATED CIRCUIT STRUCTURES - A diode comprises a substrate formed of a first material having a first doping polarity. The substrate has a planar surface and at least one semispherical structure extending from the planar surface. The semispherical structure is formed of the first material. A layer of second material is over the semispherical structure. The second material comprises a second doping polarity opposite the first doping polarity. The layer of second material conforms to the shape of the semispherical structure. A first electrical contact is connected to the substrate, and a second electrical contact is connected to the layer of second material. Additional semiconductor structures are formed by fabricating additional layers over the original layers. | 05-19-2011 |
20110133312 | POWER DEVICE - The present invention is a power device includes, a first conductive type semiconductor substrate, a second conductive type base region formed on a surface of the semiconductor substrate, a second conductive type collector region formed on a rear surface of the semiconductor substrate, a first conductive type emitter region formed on a surface of the base region, a trench gate formed via a gate insulating film in a first trench groove formed in the base region so as to penetrate the emitter region, a dent formed in the base region in proximity to the emitter region, a second conductive type contact layer formed on an inner wall of the dent, having a higher dopant density than that of the base region, a dummy trench formed via a dummy trench insulating film in a second trench groove formed at a bottom of the dent, and an emitter electrode electrically connected to the emitter region, the contact layer and the dummy trench, wherein the trench gate and the dummy trench reach the semiconductor substrate. | 06-09-2011 |
20110147893 | BIPOLAR TRANSISTORS WITH HUMP REGIONS - By providing a novel bipolar device design implementation, a standard CMOS process can be used unchanged to fabricate useful bipolar transistors and other bipolar devices having adjustable properties by partially blocking the P or N well doping used for the transistor base. This provides a hump-shaped base region with an adjustable base width, thereby achieving, for example, higher gain than can be obtained with the unmodified CMOS process alone. By further partially blocking the source/drain doping step used to form the emitter of the bipolar transistor, the emitter shape and effective base width can be further varied to provide additional control over the bipolar device properties. The embodiments thus include prescribed modifications to the masks associated with the bipolar device that are configured to obtain desired device properties. The CMOS process steps and flow are otherwise unaltered and no additional process steps are required. | 06-23-2011 |
20120104554 | FLEXIBLE AND ON WAFER HYBRID PLASMA-SEMICONDUCTOR TRANSISTORS - Preferred embodiment flexible and on wafer hybrid plasma semiconductor devices have at least one active solid state semiconductor region; and a plasma generated in proximity to the active solid state semiconductor region(s). Doped solid state semiconductor regions are in a thin flexible solid state substrate, and a flexible non conducting material defining a microcavity adjacent the semiconductor regions. The flexible non conducting material is bonded to the thin flexible solid state substrate, and at least one electrode is arranged with respect to said flexible substrate to generate a plasma in said microcavity, where the plasma will influence or perform a semiconducting function in cooperation with said solid state semiconductor regions. A preferred on-wafer device is formed on a single side of a silicon on insulator wafer and defines the collector (plasma cavity), emitter and base regions on a common side, which provides a simplified and easy to manufacture structure. A preferred embodiment array of flexible hybrid plasma transistors of the invention is an n+pn PBJT fabricated between two flexible sheets. One or both of the flexible sheets is transparent. The overall array structure is planar, and the planarized structure is sealed between the two flexible sheets. Visible or ultraviolet light is emitted during operation by plasma collectors in the array. In preferred embodiments, individual PBJTs in the array serve as sub-pixels of a full-color display. | 05-03-2012 |
20120175738 | METHODS OF FABRICATING BIPOLAR TRANSISTOR FOR IMPROVED ISOLATION, PASSIVATION AND CRITICAL DIMENSION CONTROL - A first (e.g. replaceable or disposable) dielectric spacer formed on a sidewall of a dummy emitter mandrel is removed after a raised extrinsic base layer and covering dielectric layer are formed. Thereafter, a second dielectric spacer is formed within the opening that results. As a result, the second dielectric spacer, which is not subjected to RIE processing, provides a desired level of isolation and tighter emitter final critical dimension than that which could be achieved through the technique described in the prior art. In a particular embodiment, an additional layer of silicon nitride is disposed over a passivation oxide layer as a sacrificial layer which protects the passivation oxide layer from being reduced in thickness and/or being undercut during the RIE process and one or more cleaning processes conducted after the RIE process. | 07-12-2012 |
20120248575 | SEMICONDUCTOR DEVICE WITH MULTILAYER CONTACT AND METHOD OF MANUFACTURING THE SAME - The present invention provides a semiconductor with a multilayered contact structure. The multilayered structure includes a metal contact placed on an active region of a semiconductor and a metal contact extension placed on the metal contact. | 10-04-2012 |
20130147017 | BIPOLAR JUNCTION TRANSISTORS WITH A LINK REGION CONNECTING THE INTRINSIC AND EXTRINSIC BASES - Methods for fabricating bipolar junction transistors, bipolar junction transistors made by the methods, and design structures for a bipolar junction transistor. The bipolar junction transistor includes a dielectric layer on an intrinsic base and an extrinsic base at least partially separated from the intrinsic base by the dielectric layer. An emitter opening extends through the extrinsic base and the dielectric layer. The dielectric layer is recessed laterally relative to the emitter opening to define a cavity between the intrinsic base and the extrinsic base. The cavity is filled with a semiconductor layer that physically links the extrinsic base and the intrinsic base together. | 06-13-2013 |
20130277804 | BIPOLAR JUNCTION TRANSISTORS WITH REDUCED BASE-COLLECTOR JUNCTION CAPACITANCE - Methods for fabricating a device structure such as a bipolar junction transistor, device structures for a bipolar junction transistor, and design structures for a bipolar junction transistor. The device structure includes a collector region formed in a substrate, an intrinsic base coextensive with the collector region, an emitter coupled with the intrinsic base, a first isolation region surrounding the collector region, and a second isolation region formed at least partially within the collector region. The first isolation region has a first sidewall and the second isolation region having a second sidewall peripherally inside the first sidewall. A portion of the collector region is disposed between the first sidewall of the first isolation region and the second sidewall of the second isolation region. | 10-24-2013 |
20130299944 | Methods and Apparatus for Bipolar Junction Transistors and Resistors - Methods and apparatus for bipolar junction transistors (BJTs) are disclosed. A BJT comprises a collector made of p-type semiconductor material, a base made of n-type well on the collector; and an emitter comprising a p+ region on the base and a SiGe layer on the p+ region. The BJT can be formed by providing a semiconductor substrate comprising a collector, a base on the collector, forming a sacrificial layer on the base, patterning a first photoresist on the sacrificial layer to expose an opening surrounded by a STI within the base; implanting a p-type material through the sacrificial layer into an area of the base, forming a p+ region from the p-type implant; forming a SiGe layer on the etched p+ region to form an emitter. The process can be shared with manufacturing a polysilicon transistor up through the step of patterning a first photoresist on the sacrificial layer. | 11-14-2013 |
20140319654 | FLEXIBLE AND ON WAFER HYBRID PLASMA-SEMICONDUCTOR TRANSISTORS - Preferred embodiment flexible and on wafer hybrid plasma semiconductor devices have at least one active solid state semiconductor region; and a plasma generated in proximity to the active solid state semiconductor region(s). A preferred device is a hybrid plasma semiconductor device having base, emitting and microcavity collector regions formed on a single side of a device layer. Visible or ultraviolet light is emitted during operation by plasma collectors in the array. In preferred embodiments, individual PBJTs in the array serve as sub-pixels of a full-color display. | 10-30-2014 |
20140327111 | TRENCH ISOLATION STRUCTURES AND METHODS FOR BIPOLAR JUNCTION TRANSISTORS - Device structures, fabrication methods, and design structures for a bipolar junction transistor. A first isolation region is formed in a substrate to define a lateral boundary for an active device region and an intrinsic base layer is formed on the substrate. The intrinsic base layer has a section overlying the active device region. After the intrinsic base layer is formed, the first isolation region is partially removed adjacent to the active device region to define a trench that is coextensive with the substrate in the active device region and that is coextensive with the first isolation region. The trench is at least partially filled with a dielectric material to define a second isolation region. | 11-06-2014 |
20140339677 | HYBRID PLASMA-SEMICONDUCTOR TRANSISTORS, LOGIC DEVICES AND ARRAYS - A hybrid plasma semiconductor device has a thin and flexible semiconductor base layer. An emitter region is diffused into the base layer forming a pn-junction. An insulator layer is upon one side the base layer and emitter region. Base and emitter electrodes are isolated from each other by the insulator layer and electrically contact the base layer and emitter region through the insulator layer. A thin and flexible collector layer is upon an opposite side of the base layer. A microcavity is formed in the collector layer and is aligned with the emitter region. Collector electrodes are arranged to sustain a microplasma within the microcavity with application of voltage to the collector electrodes. A depth of the emitter region and a thickness of the base layer are set to define a predetermined thin portion of the base layer as a base region between the emitter region and the microcavity. Microplasma generated in the microcavity serves as a collector. Logic devices are provided in multiple sub collector and sub emitter microplasma devices formed in thin and flexible or not flexible semiconductor materials. | 11-20-2014 |
20150008562 | PNP BIPOLAR JUNCTION TRANSISTOR FABRICATION USING SELECTIVE EPITAXY - Lateral PNP bipolar junction transistors and design structures for a lateral PNP bipolar junction transistor. An emitter and a collector of the lateral PNP bipolar junction transistor are comprised of p-type semiconductor material that is formed by a selective epitaxial growth process. The source and drain each directly contact a top surface of a device region used to form the emitter and collector. A base contact may be formed on the top surface and overlies an n-type base defined within the device region. The emitter is laterally separated from the collector by the base contact. Another base contact may be formed in the device region that is separated from the other base contact by the base. | 01-08-2015 |
20150311283 | BIPOLAR JUNCTION TRANSISTORS WITH REDUCED BASE-COLLECTOR JUNCTION CAPACITANCE - Device structures for a bipolar junction transistor. The device structure includes a collector region, an intrinsic base formed on the collector region, an emitter coupled with the intrinsic base and separated from the collector by the intrinsic base, and an isolation region extending through the intrinsic base to the collector region. The isolation region is formed with a first section having first sidewalls that extend through the intrinsic base and a second section with second sidewalls that extend into the collector region. The second sidewalls are inclined relative to the first sidewalls. The isolation region is positioned in a trench that is formed with first and second etching process in which the latter etches different crystallographic directions of a single-crystal semiconductor material at different etch rates. | 10-29-2015 |
20150318384 | Bipolar Transistor - A bipolar transistor and a method for fabricating a bipolar transistor are disclosed. In one embodiment the bipolar transistor includes a semiconductor body including a collector region and a base region arranged on top of the collector region, the collector region being doped with dopants of a second doping type and the base region being at least partly doped with dopants of a first doping type and an insulating spacers arranged on top of the base region. The semiconductor body further includes a semiconductor layer including an emitter region arranged on the base region and laterally enclosed by the spacers, the emitter region being doped with dopants of the second doping type forming a pn-junction with the base region, wherein the emitter region is fully located above a horizontal plane through a bottom side of the spacers. | 11-05-2015 |
20150349100 | BIPOLAR TRANSISTOR - P-type second semiconductor layers each interposed between a corresponding pair of n-type first semiconductor layers reduce the apparent doping concentration in the entire collector layer without reducing the doping concentrations in the first semiconductor layers. This improves the linearity of capacitance characteristics and enables sufficient mass productivity to be achieved. Interposing each of the second semiconductor layers between the corresponding pair of the first semiconductor layers reduce the average carrier concentration over the entire collector layer, which allows a wide depletion layer to be formed inside the collector layer and, as a result, reduces base-collector capacitance. | 12-03-2015 |
20150357446 | BIPOLAR TRANSISTOR STRUCTURE AND A METHOD OF MANUFACTURING A BIPOLAR TRANSISTOR STRUCTURE - According to various embodiments, a bipolar transistor structure may include: a substrate; a collector region in the substrate; a base region disposed over the collector region, an emitter region disposed over the base region; a base terminal laterally electrically contacting the base region, wherein the base terminal includes polysilicon. | 12-10-2015 |
20150357447 | BIPOLAR TRANSISTOR WITH EXTRINSIC BASE REGION AND METHODS OF FABRICATION - The present disclosure relates to integrated circuit (IC) structures and methods of forming the same. An IC structure according to the present disclosure can include: a doped substrate region adjacent to an insulating region; a crystalline base structure including: an intrinsic base region located on and contacting the doped substrate region, the intrinsic base region having a first thickness; an extrinsic base region adjacent to the insulating region, wherein the extrinsic base region has a second thickness greater than the first thickness; a semiconductor layer located on the intrinsic base region of the crystalline base structure; and a doped semiconductor layer located on the semiconductor layer. | 12-10-2015 |
20160104770 | PROFILE CONTROL OVER A COLLECTOR OF A BIPOLAR JUNCTION TRANSISTOR - Device structures for a bipolar junction transistor. A layer is formed on a top surface of a substrate. A trench is formed in the layer and has a plurality of sidewalls with a width between an opposite pair of the sidewalls that varies with increasing distance from the top surface of the substrate. A collector pedestal of the bipolar junction transistor is formed in the trench. | 04-14-2016 |
20160380067 | SHAPED TERMINALS FOR A BIPOLAR JUNCTION TRANSISTOR - Device structure and fabrication methods for a bipolar junction transistor. An emitter layer is formed on a base layer and etched to form an emitter of the device structure. The emitter layer has a concentration of an element that varies as a function of the thickness of the emitter layer. The etch rate of the emitter layer varies as a function of the concentration of the element such that the emitter has a variable width over the thickness of the emitter layer. | 12-29-2016 |