Class / Patent application number | Description | Number of patent applications / Date published |
257513000 | Vertical walled groove | 22 |
20080217729 | Isolation structures for integrated circuit devices - An isolated CMOS pair of transistors formed in a P-type semiconductor substrate includes an N-type submerged floor isolation region and a filled trench extending downward from the surface of the substrate to the floor isolation region. Together the floor isolation region and the filled trench form an isolated pocket of the substrate which contains a P-channel MOSFET in an N-well and an N-channel MOSFET in a P-well. The substrate does not contain an epitaxial layer, thereby overcoming the many problems associated with fabricating the same. | 09-11-2008 |
20080237782 | Isolated rectifier diode - An isolated diode comprises a floor isolation region, a dielectric-filled trench and a sidewall region extending from a bottom of the trench at least to the floor isolation region. The floor isolation region, dielectric-filled trench and a sidewall region are comprised in one terminal (anode or cathode) of the diode and together form an isolated pocket in which the other terminal of the diode is formed. In one embodiment the terminals of the diode are separated by a second dielectric-filled trench and sidewall region. | 10-02-2008 |
20080237783 | Isolated bipolar transistor - A bipolar transistor is formed in an isolation structure comprising a floor isolation region, a dielectric filled trench above the floor isolation region and a sidewall isolation region extending downward from the bottom of the trench to the floor isolation region. This structure provides a relatively deep isolated pocket in a semiconductor substrate while limiting the depth of the trench that must be etched in the substrate. | 10-02-2008 |
20080237784 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE - A semiconductor device formed in a semiconductor substrate wherein the semiconductor substrate has a trench for isolating elements from each other, the trench has unevenness at the bottom thereof, and an insulator is buried in the trench. | 10-02-2008 |
20080251883 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes a semiconductor substrate formed with a plurality of first element isolation trenches having respective first opening widths and a plurality of second element isolation trenches having larger opening widths than the first opening widths, element isolation insulating films buried in the first element isolation trenches so that upper parts of the trenches have partial openings, respectively and buried in the second element isolation trenches respectively, and coating type oxide films formed so as to fill the openings of the first element isolation trenches, respectively. | 10-16-2008 |
20080265364 | Creation of Dielectrically Insulating Soi-Technlogical Trenches Comprising Rounded Edges for Allowing Higher Voltages - The aim of the invention is to integrate low-voltage logic elements and high-voltage power elements in one and the same silicon circuit. Said aim is achieved by dielectrically chip regions having different potentials from each other with the aid of isolation trenches ( | 10-30-2008 |
20080265365 | METHOD FOR PREVENTING THE FORMATION OF ELECTRICAL SHORTS VIA CONTACT ILD VOIDS - Densely spaced gates of field effect transistors usually lead to voids in a contact interlayer dielectric. If such a void is opened by a contact via and filled with conductive material, an electrical short between neighboring contact regions of neighboring transistors may occur. By forming a recess between two neighboring contact regions, the void forms at a lower level. Thus, opening of the void by contact vias is prevented. | 10-30-2008 |
20080283962 | SELF-ALIGNED AND EXTENDED INTER-WELL ISOLATION STRUCTURE - A pedestal is formed out of the pad layer such that two edges of the pedestal coincide with a border of the wells as implanted. An extended pedestal is formed over the pedestal by depositing a conformal dielectric layer. The area of the extended pedestal is exposed the semiconductor surface below is recessed to a recess depth. Other trenches including at least one intra-well isolation trench are lithographically patterned. After a reactive ion etch, both an inter-well isolation trench and at least one intra-well isolation trench are formed. The width of the inter-well isolation trench may be reduced due to the deeper bottom surface compared to the prior art structures. The boundary between the p-well and the n-well below the inter-well isolation structure is self-aligned to the middle of the inter-well isolation structure. | 11-20-2008 |
20080290448 | Semiconductor devices and methods of manufacture thereof - Semiconductor devices and methods of manufacture thereof are disclosed. In a preferred embodiment, a semiconductor device includes a workpiece and a trench formed within the workpiece. The trench has an upper portion and a lower portion, the upper portion having a first width and the lower portion having a second width, the second width being greater than the first width. A first material is disposed in the lower portion of the trench at least partially in regions where the second width of the lower portion is greater than the first width of the upper portion. A second material is disposed in the upper portion of the trench and at least in the lower portion of the trench beneath the upper portion. | 11-27-2008 |
20080290449 | Isolation structures for integrated circuits - A variety of isolation structures for semiconductor substrates include a trench formed in the substrate that is filled with a dielectric material or filled with a conductive material and lined with a dielectric layer along the walls of the trench. The trench may be used in combination with doped sidewall isolation regions. Both the trench and the sidewall isolation regions may be annular and enclose an isolated pocket of the substrate. The isolation structures are formed by modular implant and etch processes that do not include significant thermal processing or diffusion of dopants so that the resulting structures are compact and may be tightly packed in the surface of the substrate. | 11-27-2008 |
20080290450 | Isolation structures for integrated circuits - A variety of isolation structures for semiconductor substrates include a trench formed in the substrate that is filled with a dielectric material or filled with a conductive material and lined with a dielectric layer along the walls of the trench. The trench may be used in combination with doped sidewall isolation regions. Both the trench and the sidewall isolation regions may be annular and enclose an isolated pocket of the substrate. The isolation structures are formed by modular implant and etch processes that do not include significant thermal processing or diffusion of dopants so that the resulting structures are compact and may be tightly packed in the surface of the substrate. | 11-27-2008 |
20080290451 | Isolation structures for integrated circuits - A variety of isolation structures for semiconductor substrates include a trench formed in the substrate that is filled with a dielectric material or filled with a conductive material and lined with a dielectric layer along the walls of the trench. The trench may be used in combination with doped sidewall isolation regions. Both the trench and the sidewall isolation regions may be annular and enclose an isolated pocket of the substrate. The isolation structures are formed by modular implant and etch processes that do not include significant thermal processing or diffusion of dopants so that the resulting structures are compact and may be tightly packed in the surface of the substrate. | 11-27-2008 |
20080290452 | Trench-constrained isolation diffusion for integrated circuit die - A semiconductor substrate includes a pair of trenches filled with a dielectric material. Dopant introduced into the mesa between the trenches is limited from diffusing laterally when the substrate is subjected to thermal processing. Therefore, semiconductor devices can be spaced more closely together on the substrate, and the packing density of the devices can be increased. Also trench constrained doped region diffuse faster and deeper than unconstrained diffusions, thereby reducing the time and temperature needed to complete a desired depth diffusion. The technique may be used for semiconductor devices such as bipolar transistors as well as isolation regions that electrically isolate the devices from each other. In one group of embodiments, a buried layer is formed at an interface between an epitaxial layer and a substrate, at a location generally below the dopant in the mesa. When the substrate is subjected to thermal processing, the buried layer diffuses upward, the dopant in the mesa diffuses downward until the two dopants merge to form an isolation region or a sinker extending downward from the surface of the epitaxial layer to the buried layer. In another embodiment, dopant is implanted between dielectrically filled trenches at a high energy up to several MeV, then diffused, combining the benefits of deep implantation and trenched constrained diffusion to achieve deep diffusions with a minimal thermal budget. | 11-27-2008 |
20090045483 | Semiconductor devices having trench isolation regions and methods of manufacturing semiconductor devices having trench isolation regions - A semiconductor device may include a semiconductor substrate, trench region, buffer pattern, gap fill layer, and transistor. The trench region may be provided in the semiconductor substrate to define an active region. The buffer pattern and gap fill layer may be provided in the trench region. The buffer pattern and gap fill layer may fill the trench region. The gap fill layer may be densified by the buffer pattern. The transistor may be provided in the active region. A method of manufacturing a semiconductor device may include: forming a trench region in a semiconductor substrate; forming a buffer layer on an inner wall of the first trench region; forming a gap fill layer, filling the trench region; performing a thermal process to react the impurity with the oxygen, forming a buffer pattern; and forming a transistor in the active region. | 02-19-2009 |
20090065893 | SEMICONDUCTOR DEVICES AND FABRICATION METHODS THEREOF - A semiconductor device and fabrication method thereof is disclosed. The method includes the steps of providing a substrate with a trench and a stacked layer thereon, performing an epitaxy process to form an epitaxial layer in the trench, conformably depositing an oxide layer on the epitaxial layer, and removing a portion of the oxide layer and the epitaxial layer on the bottom of the trench. | 03-12-2009 |
20090174027 | INTEGRATED CIRCUIT INCLUDING ISOLATION REGIONS SUBSTANTIALLY THROUGH SUBSTRATE - An integrated circuit including a substrate and trench isolation regions. The substrate supports a device. The trench isolation regions are configured to laterally isolate the device. The trench isolation regions extend substantially through the substrate. | 07-09-2009 |
20090278227 | ISOLATION TRENCH STRUCTURE - Among structures, methods, devices, and systems for isolation trenches, a semiconductor device is provided that includes a substrate and an isolation trench structure. One such isolation trench structure includes a first isolation trench portion associated with a surface of the substrate and having a first pair of opposing sidewalls that are each substantially perpendicular to the surface of the substrate. A second isolation trench portion includes a second pair of sidewalls within the substrate that are each angled obliquely with respect to the surface of the substrate, where the second isolation trench portion has a separation between the second pair of sidewalls that decreases as a distance from the first isolation trench portion increases. A third isolation trench portion includes a third pair of sidewalls within the substrate that are each substantially perpendicular to the surface of the substrate. | 11-12-2009 |
20100025807 | Discrete Semiconductor Device and Method of Forming Sealed Trench Junction Termination - A discrete semiconductor device has a substrate with a first conductivity type of semiconductor material. A first semiconductor layer is formed over the substrate. The first semiconductor layer having the first conductivity type of semiconductor material. A second semiconductor layer over the first semiconductor layer. The second semiconductor layer has a second conductivity type of semiconductor material. A trench is formed through the second semiconductor layer and extends into the second semiconductor layer. The trench has a rounded or polygonal shape and vertical sidewalls. The trench is lined with an insulating layer and filled with an insulating material. A boundary between the first and second semiconductor layers forms a p-n junction. The trench surrounds the p-n junction to terminate the electric field of a voltage imposed on the second semiconductor layer. The discrete semiconductor device can also be a transistor, thyristor, triac, or transient voltage suppressor. | 02-04-2010 |
20100038746 | SEMICONDUCTOR STRUCTURE AND METHOD FOR MAKING ISOLATION STRUCTURE THEREIN - A method for an isolation structure is provided. First, a substrate with a shallow trench isolation is provided. Second, a patterned mask is formed on the substrate. Then, the substrate is etched using the patterned mask to respectively form a first deep trench and a second deep trench as well as a first undercut and a second undercut on opposite sides of the shallow trench isolation. Later, the first deep trench and the second deep trench are partially filled with Si. Afterwards, the first deep trench and the second deep trench are filled with an isolation material to form the isolation structure. | 02-18-2010 |
20110193191 | PROTECTIVE ELEMENT AND SEMICONDUCTOR DEVICE - A semiconductor device includes at least one semiconductor element having a semiconductor stack containing a channel layer and a cap layer and a lower electrode and an upper electrode formed over a semiconductor stack, and at least one protective element having the semiconductor stack in common with the semiconductor element for protecting the semiconductor element. The protective element includes a recessed portion that penetrates the cap layer in the direction of the thickness, an insulation region formed in the semiconductor stack from the bottom of the recessed portion | 08-11-2011 |
20130207229 | NOISE ISOLATION BETWEEN CIRCUIT BLOCKS IN AN INTEGRATED CIRCUIT CHIP - An integrated circuit includes a p-well block region having a low doping concentration formed in a region of a substrate for providing noise isolation between a first circuit block and a second circuit block. The integrated circuit further includes a guard region and a grounded, highly doped region for providing additional noise isolation. | 08-15-2013 |
20140159193 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A semiconductor device includes a first isolation layer formed in a trench in a substrate. The isolation layer includes a first oxide layer formed in the trench and a second oxide layer formed over the first oxide layer, wherein the first oxide layer and the second oxide layer have a same composition. | 06-12-2014 |