Entries |
Document | Title | Date |
20080197428 | Gate Electrode Structure, MOS Field Effect Transistors and Methods of Manufacturing the Same - A gate electrode structure comprises at least one bi-layer, wherein each bi-layer comprises a plating film and a stress amplifier film. The plating film includes a poly-crystalline material. The stress amplifier film determines the crystallization result of the poly-crystalline material, wherein a mechanical stress induced through the plating layer is amplified. Tensile or compressive strain may be induced in a crystalline substrate. Electron or hole mobility may be increased and on-resistance characteristics of a MOS field effect transistor may be improved. | 08-21-2008 |
20080197429 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SAME - A semiconductor device includes: a silicon oxide film; a metal silicate insulating film provided on the silicon oxide film and having a higher dielectric constant than the silicon oxide film; and a gate electrode provided on the metal silicate insulating film. A composition ratio of a metal element in the metal silicate insulating film on a side closer to the gate electrode is lower than a composition ratio of the metal element in the metal silicate insulating film on a side closer to the silicon oxide film. | 08-21-2008 |
20080211038 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - A method of fabricating a semiconductor device includes forming a preliminary gate pattern on a semiconductor substrate. The preliminary gate pattern includes a gate oxide pattern, a conductive pattern, and a sacrificial insulating pattern. The method further includes forming spacers on opposite sidewalls of the preliminary gate pattern, forming an interlayer dielectric pattern to expose the sacrificial insulating pattern, removing the sacrificial insulating pattern to form an opening to expose the conductive pattern, transforming the conductive pattern into a metal silicide layer and forming a metal barrier pattern along an inner profile of the opening and a metal conductive pattern to fill the opening including the metal barrier pattern. The metal silicide layer and the metal conductive pattern constitute a gate electrode. | 09-04-2008 |
20080211039 | Nonvolatile memory devices having metal silicide nanocrystals, methods of forming metal silicide nanocrystals, and methods of forming nonvolatile memory devices having metal silicide nanocrystals - A nonvolatile memory device includes a semiconductor substrate. A charge storage insulating film containing metal silicide nanocrystals is on the substrate. A gate electrode is on the charge storage insulating film. Related methods of forming metal silicide nanocrystals, and methods of forming nonvolatile memory devices including metal silicide nanocrystals, are also disclosed. | 09-04-2008 |
20080217707 | TRANSISTOR HAVING GATE AND BODY IN DIRECT SELF-ALIGNED CONTACT AND RELATED METHODS - A transistor having a directly contacting gate and body and related methods are disclosed. In one embodiment, the transistor includes a gate; a body; and a dielectric layer extending over the body to insulate the gate from the body along an entire surface of the body except along a portion of at least a sidewall of the body, wherein the gate is in direct contact with the body at the portion. One method may include providing the body; forming a sacrificial layer that contacts at least a portion of a sidewall of the body; forming a dielectric layer about the body except at the at least a portion; removing the sacrificial layer; and forming the gate about the body such that the gate contacts the at least a portion of the sidewall of the body. | 09-11-2008 |
20080230855 | Gate strip with reduced thickness - A semiconductor structure with reduced inter-diffusion is provided. The semiconductor structure includes a semiconductor substrate; a first well region in the semiconductor substrate; a second well region in the semiconductor substrate; an insulating region between and adjoining the first and the second well regions; a gate dielectric layer on the first and the second well regions; and a gate electrode strip on the gate dielectric and extending from over the first well region to over the second well region. The gate electrode strip includes a first portion over the first well region, a second portion over the second well region, and a third portion over the insulating region. A thickness of the third portion is substantially less than the thicknesses of the first and the second portions. | 09-25-2008 |
20080237749 | CMOS GATE CONDUCTOR HAVING CROSS-DIFFUSION BARRIER - A gate conductor is provided for a transistor pair including an n-type field effect transistor (“NFET”) having an NFET active semiconductor region and a p-type field effect transistor (“PFET”) having a PFET active semiconductor region, where the NFET and PFET active semiconductor regions are separated by an isolation region. An NFET gate extends in a first direction over the NFET active semiconductor region. A PFET gate extends in the first direction over the PFET active semiconductor region. A diffusion barrier is sandwiched between the NFET gate and the PFET gate. A continuous layer extends continuously in the first direction over the NFET gate and the PFET gate. The continuous layer contacts top surfaces of the NFET gate and the PFET gate and the continuous layer includes at least one of a semiconductor, a metal or a conductive compound including a metal. | 10-02-2008 |
20080237750 | Silicided metal gate for multi-threshold voltage configuration - A PMOS (p-channel metal oxide semiconductor) device having at low voltage threshold MOSFET (MOS field effect transistor) with an improved work function and favorable DIBL (drain-induced barrier lowering) and SCE (short channel effect) characteristics, and a method for making such a device. The PMOS device includes a gate structure that is disposed on a substrate and includes a silicided gate electrode. The silicide is preferably nickel-rich and includes a peak platinum concentration at or near the interface between the gate electrode and a dielectric layer that separates the gate electrode from the substrate. The platinum peak region is produced by a multi-step rapid thermal annealing or similar process. The PMOS device may also include two such MOSFETs, one of which is boron-doped and one of which is not. | 10-02-2008 |
20080237751 | CMOS Structure and method of manufacturing same - A CMOS structure includes a substrate ( | 10-02-2008 |
20080237752 | METHOD FOR MANUFACTURING SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - Disclosed is a technique for reducing the leak current by reducing contamination of metal composing a polymetal gate of a MISFET. Of a polycrystalline silicon film, a WN film, a W film, and a cap insulating film formed on a gate insulating film on a p-type well (semiconductor substrate), the cap insulating film, the W film, and the WN film are etched and the over-etching of the polycrystalline silicon film below them is performed. Then, a sidewall film is formed on sidewalls of these films. Thereafter, after etching the polycrystalline silicon film with using the sidewall film as a mask, a thermal treatment is performed in an oxidation atmosphere, by which a light oxide film is formed on the sidewall of the polycrystalline silicon film. As a result, the contamination on the gate insulating film due to the W and the W oxide can be reduced, and also, the diffusion of these materials into the semiconductor substrate (p-type well) and the resultant increase of the leak current can be prevented. | 10-02-2008 |
20080237753 | Methods of Fabricating Semiconductor Devices and Structures Thereof - Methods of forming spacers on sidewalls of features of semiconductor devices and structures thereof are disclosed. A preferred embodiment comprises a semiconductor device including a workpiece and at least one feature disposed over the workpiece. A first spacer is disposed on the sidewalls of the at least one feature, the first spacer comprising a first material. A first liner is disposed over the first spacer and over a portion of the workpiece proximate the first spacer, the first liner comprising the first material. A second spacer is disposed over the first liner, the second spacer comprising a second material. A second liner is disposed over the second spacer, the second liner comprising the first material. | 10-02-2008 |
20080246101 | METHOD OF POLY-SILICON GRAIN STRUCTURE FORMATION - A method for forming a poly-crystalline silicon film on a substrate by positioning a substrate within a processing chamber, heating the processing chamber to a first temperature between about 640° C. and about 720° C., stabilizing a deposition pressure between about 200 Torr and about 350 Torr, introducing a silicon precursor into the processing chamber to deposit a silicon film comprising an amorphous or hemisphere grain film, and heating the processing chamber to a second temperature between about 700° C. and about 750 C.° to anneal the amorphous or hemisphere grain film into a poly-crystalline nano-crystalline grain film. | 10-09-2008 |
20080246102 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device includes an Nch transistor having a first gate electrode and a Pch transistor having a second gate electrode. The first gate electrode and the second gate electrode are made of materials causing stresses of different magnitudes. | 10-09-2008 |
20080251864 | STACKED POLY STRUCTURE TO REDUCE THE POLY PARTICLE COUNT IN ADVANCED CMOS TECHNOLOGY - A method for implementing a stacked gate, comprising forming a gate dielectric on a semiconductor body, forming a first layer of gate electrode material on the gate dielectric, forming a second layer of gate electrode material on the first layer of gate electrode material, wherein the grain size distribution of the first layer of gate electrode material is different than the grain size distribution of the second layer of gate electrode material, implanting the first and second gate electrode materials, patterning the first and the second gate electrodes and the gate dielectric, and forming source and drain regions. | 10-16-2008 |
20080258244 | SEMICONDUCTOR DEVICE - In one aspect of the present invention, a semiconductor device may include a semiconductor substrate, a gate dielectric layer provided on the semiconductor substrate, a source region provided in the semiconductor substrate, a drain region provided in the semiconductor substrate, and a gate electrode provided on the gate dielectric layer having a metal containing layer and a polycrystalline silicon layer having an impurity ion, the polycrystalline silicon layer provided on the metal containing layer so as to cover an upper surface and side surface of the metal containing layer. | 10-23-2008 |
20080258245 | Semiconductor Constructions and Transistor Gates - One aspect of the invention encompasses a method of forming a semiconductor structure. A patterned line is formed to comprise a first layer and a second layer. The first layer comprises silicon and the second layer comprises a metal. The line has at least one sidewall edge comprising a first-layer-defined portion and a second-layer-defined portion. A third layer is formed along the at least one sidewall edge. The third layer comprises silicon and is along both the first layered defined portion of the sidewall edge and the second-layered-defined portion of the sidewall edge. The silicon of the third layer is reacted with the metal of the second layer to form a silicide along the second layer defined portion of the sidewall edge. The silicon of the third layer is removed to leave the silicon of the first layer, the metal of the second layer, and the silicide. | 10-23-2008 |
20080265343 | FIELD EFFECT TRANSISTOR WITH INVERTED T SHAPED GATE ELECTRODE AND METHODS FOR FABRICATION THEREOF - A semiconductor structure includes an inverted T shaped gate electrode located over a channel region that separates a plurality of source and drain regions within a semiconductor substrate. The inverted T shaped gate electrode may comprise different gate electrode materials in a horizontal portion thereof and a vertical portion thereof. The semiconductor structure may be passivated with an inter-level dielectric (ILD) layer through which may be located and formed a plurality of vias that contact the plurality of source and drain regions. Due to the inverted T shaped gate electrode, the semiconductor structure exhibits a reduced gate electrode to via capacitance. | 10-30-2008 |
20080265344 | METHOD OF SIMULTANEOUSLY SILICIDING A POLYSILICON GATE AND SOURCE/DRAIN OF A SEMICONDUCTOR DEVICE, AND RELATED DEVICE - A method of simultaneously siliciding a polysilicon gate and source/drain of a semiconductor device, and related device. At least some of the illustrative embodiments are methods comprising forming a gate stack over a semiconductor substrate (the gate stack comprising a first polysilicon layer, a first nitride layer, and a second polysilicon layer), forming a second nitride layer over an active region in the semiconductor substrate adjacent to the gate stack, performing a chemical mechanical polishing that stops on the first nitride layer and on the second nitride layer, removing the first nitride layer and the second nitride layer, and performing a simultaneous silicidation of the first polysilicon layer and the active region. | 10-30-2008 |
20080265345 | Method of Forming a Fully Silicided Semiconductor Device with Independent Gate and Source/Drain Doping and Related Device - A method of forming a fully silicided semiconductor device with independent gate and source/drain doping and related device. At least some of the illustrative embodiments are methods comprising forming a gate stack over a substrate (the gate stack comprising a polysilicon layer and a blocking layer), and performing an ion implantation into an active region of the substrate adjacent to the gate stack (the blocking layer substantially blocks the ion implantation from the polysilicon layer). | 10-30-2008 |
20080272445 | LOW-K DISPLACER FOR OVERLAP CAPACITANCE REDUCTION - Source/drain extensions and source and drain regions are formed in a semiconductor substrate utilizing an optional temporary first gate spacer and a temporary second gate spacer. After forming a gate silicide and a source and drain silicide in a silicidation process, the optional temporary first gate spacer and a temporary second gate spacer are removed. Low-k dielectric material is disposed directly on the sidewalls of the gate electrode. The low-k dielectric material may form a portion of a lower gate spacer. Alternatively, the low-k dielectric material may form a layer that contacts and covers the source and drain regions. The low-k material displaces the optional temporary first gate spacer and the temporary second gate spacer to lower the overlap capacitance between the gate electrode and the source/drain extensions. A continuous mobile ion diffusion barrier dielectric layer is formed over the low-k material. | 11-06-2008 |
20080277745 | FIN FILLED EFFECT TRANSISTOR AND METHOD OF FORMING THE SAME - A fin field effect transistor and method of forming the same. The fin field effect transistor comprises a semiconductor substrate having a fin structure and between two trenches with top portions and bottom portions. The fin field effect transistor further comprises shallow trench isolations formed in the bottom portions of the trenches and a gate electrode over the fin structure and the shallow trench isolation, wherein the gate electrode is substantially perpendicular to the fin structure. The fin field effect transistor further comprises a gate dielectric layer along sidewalls of the fin structure and source/drain electrode formed in the fin structure. | 11-13-2008 |
20080283941 | FABRICATION OF TRANSISTORS WITH A FULLY SILICIDED GATE ELECTRODE AND CHANNEL STRAIN - An integrated circuit includes one or more transistors on or in a semiconductor substrate. At least one of the transistors includes a gate electrode and source and drain structures. The gate electrode has a fully silicided gate electrode layer with a ratio of Ni:Si ranging from about 2:1 to about 3:1. The source and drain structures are located in openings of the substrate and adjacent to the gate electrode. The source and drain structures are filled with SiGe to produce stress in the transistor channel region. | 11-20-2008 |
20080290427 | USE OF DOPANTS TO PROVIDE LOW DEFECT GATE FULL SILICIDATION - The invention provides a semiconductor device and method of manufacture therefore. The method for manufacturing the semiconductor device, in one embodiment, includes forming an NMOS gate structure over a substrate, wherein the NMOS gate structure includes an NMOS gate dielectric and an NMOS gate electrode. The method further includes forming n-type source/drain regions within the substrate proximate the NMOS gate structure, and forming a metal alloy layer over the NMOS gate electrode. The method additionally includes incorporating the metal alloy into the NMOS gate electrode to form an NMOS gate electrode fully silicided with the metal alloy. | 11-27-2008 |
20080290428 | USE OF ALLOYS TO PROVIDE LOW DEFECT GATE FULL SILICIDATION - The disclosure provides a semiconductor device and method of manufacture therefore. The method for manufacturing the semiconductor device, in one embodiment, includes forming a layer of gate electrode material over a layer of gate dielectric material, wherein the layer of gate dielectric material is positioned over a substrate. This method further includes patterning the layer of gate electrode material and the layer of gate dielectric material into an NMOS gate structure, wherein the NMOS gate structure includes an NMOS gate dielectric and an NMOS gate electrode. This method further includes forming n-type source/drain regions within the substrate proximate the NMOS gate structure, and siliciding the NMOS gate electrode to form a silicided gate electrode. This method additionally includes placing a p-type dopant within the layer of gate electrode material or the NMOS gate electrode prior to or concurrently with siliciding. | 11-27-2008 |
20080296705 | GATE AND MANUFACTURING METHOD OF GATE MATERIAL - A gate including a conductive buffer layer and a conductive layer is provided. The conductive buffer layer is disposed on a gate dielectric layer, and the average grain size of the conductive buffer layer is less than 100 nm. The conductive layer is disposed on the conductive buffer layer, and the average grain size of the conductive layer is greater than or equal to 100 nm. The disposition of the conductive buffer layer reduces the undesired effect caused by noise and dark current to the performance of the device. | 12-04-2008 |
20080296706 | COBALT DISILICIDE STRUCTURE - A structure. The structure may include a layer of cobalt disilicide that is substantially free of cobalt monosilicide and there is substantially no stringer of an oxide of titanium on the layer of cobalt disilicide. The structure may include a substrate that includes: an insulated-gate field effect transistor (FET) that includes a source, a drain, and a gate; a first layer of cobalt disilicide on the source, said first layer having substantially no cobalt monosilicide, and said first layer having substantially no stringer of an oxide of titanium thereon; a second layer of cobalt disilicide on the drain, said second layer having substantially no cobalt monosilicide having substantially no stringer of an oxide of titanium thereon; and a third layer of cobalt disilicide on the gate, said third layer having substantially no cobalt monosilicide and having substantially no stringer of an oxide of titanium thereon. | 12-04-2008 |
20080296707 | SEMICONDUCTOR TRANSISTORS WITH EXPANDED TOP PORTIONS OF GATES - A semiconductor transistor with an expanded top portion of a gate and a method for forming the same. The semiconductor transistor with an expanded top portion of a gate includes (a) a semiconductor region which includes a channel region and first and second source/drain regions; the channel region is disposed between the first and second source/drain regions, (b) a gate dielectric region in direct physical contact with the channel region, and (c) a gate electrode region which includes a top portion and a bottom portion. The bottom portion is in direct physical contact with the gate dielectric region. A first width of the top portion is greater than a second width of the bottom portion. The gate electrode region is electrically insulated from the channel region by the gate dielectric region. | 12-04-2008 |
20080303105 | DUAL GATE DIELECTRIC SRAM - An SRAM cell structure containing a PFET gate dielectric having a thicker effective oxide thickness (EOT) than an NFET gate dielectric and methods of manufacturing the same is provided. The PFET gate dielectric and the NFET gate dielectric may be silicon oxynitride layers, CVD oxide layers, or high-K dielectric layers having different thicknesses. The PFET gate dielectric may be a stack of two dielectric layers and the NFET gate dielectric may be one of the two dielectric layers. The greater EOT of the PFET gate dielectric produces reduction of the on-current of the pull-up PFETs for optimal SRAM performance. | 12-11-2008 |
20080308883 | MONITORING PATTERN FOR SILICIDE - Provided is a monitoring pattern for a silicide that may include a plurality of poly pads, a plurality of N-well regions and P-well regions, active regions, and a poly gate line. The plurality of poly pads are disposed on a semiconductor substrate. The plurality of N-well regions and P-well regions are disposed in a single line between the poly pads. The active regions are disposed on the N-well and the P-well regions. The poly gate line electrically connects the active regions to the poly pads and has a configuration permitting it to pass through the active regions a plurality of times. | 12-18-2008 |
20080315330 | SACRIFICIAL SELF-ALIGNED INTERCONNECT STRUCTURES - A sacrificial, self-aligned polysilicon interconnect structure is formed in a region of insulating material adjacent to an active region location and underlying a semiconductor device of a substrate assembly in order to electrically connect the active region and the semiconductor device. A preexisting geometry of the active region is maintained during etching of an interconnect structure hole in which the interconnect structure is formed and saves process steps. Under the method, a region of insulating material is formed immediately adjacent the active region location. A nitride layer is formed over the active region and protects the active region while an interconnect structure hole is etched partially into the region of insulating material adjacent the active region location with an etching process that is selective to the nitride layer. The interconnect structure hole is filled with polysilicon, the surface of the substrate assembly is planarized, and the nitride layer is removed. | 12-25-2008 |
20090008726 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device reducing interface resistance of n-type and p-type MISFETs are provided. According to the method, a gate dielectric film and a gate electrode of the n-type MISFET are formed on a first semiconductor region, a gate dielectric film and a gate electrode of the p-type MISFET are formed on a second semiconductor region, an n-type diffusion layer is formed by ion implantation of As into the first semiconductor region, a first silicide layer is formed by first heat treatment after a first metal containing Ni is deposited on the n-type diffusion layer, the first silicide layer is made thicker by second heat treatment after a second metal containing Ni is deposited on the first silicide layer and second semiconductor region, and third heat treatment is provided after formation of a second silicide layer and ion implantation of B or Mg into the second silicide layer. | 01-08-2009 |
20090008727 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - It is made possible to reduce the interface resistance at the interface between the nickel silicide film and the silicon. A semiconductor manufacturing method includes: forming an impurity region on a silicon substrate, with impurities being introduced into the impurity region; depositing a Ni layer so as to cover the impurity region; changing the surface of the impurity region into a NiSi | 01-08-2009 |
20090014818 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device includes a semiconductor substrate, a gate insulating film formed on the semiconductor substrate, a gate electrode formed on the gate insulating film, a first insulating film formed on a side surface of the gate electrode, a second insulating film covering a surface of the first insulating film and formed of a material different from a material of the first insulating film, and a third insulating film covering the semiconductor substrate, the gate electrode and the second insulating film and formed of a material different from the material of the second insulating film. | 01-15-2009 |
20090020837 | Semiconductor device and manufacturing method thereof - A long channel semiconductor device and a manufacturing method thereof are provided. The method for forming a long channel semiconductor device includes: providing a substrate; forming a trench in the substrate with a trench bottom defining a first channel length; forming a spacer on a sidewall of the trench; recessing the trench bottom to form a recessed bottom defining a second channel length longer than the first channel length; forming a gate dielectric layer on the recessed bottom; forming a gate conductor on the gate dielectric layer; and forming source/drain regions in the substrate adjacent to the spacer. | 01-22-2009 |
20090045472 | Methodology for Reducing Post Burn-In Vmin Drift - A semiconductor device includes source/drain regions formed in a substrate and having a concentration of nitrogen of at least about 5E18 cm | 02-19-2009 |
20090050984 | MOS STRUCTURES THAT EXHIBIT LOWER CONTACT RESISTANCE AND METHODS FOR FABRICATING THE SAME - MOS structures that exhibit lower contact resistance and methods for fabricating such MOS structures are provided. In one method, a semiconductor substrate is provided and a gate stack is fabricated on the semiconductor substrate. An impurity-doped region within the semiconductor substrate aligned with the gate stack is formed. Adjacent contact fins extending from the impurity-doped region are fabricated and a metal silicide layer is formed on the contact fins. A contact to at least a portion of the metal silicide layer on at least one of the contact fins is fabricated. | 02-26-2009 |
20090057788 | Angled implantation for removal of thin film layers - Embodiments of the invention provide a device with a reverse-tapered gate electrode and a gate dielectric layer with a length close to that of the gate length. In an embodiment, this may be done by altering portions of a blanket dielectric layer with one or more angled ion implants, then removing the altered portions of the blanket dielectric layer. | 03-05-2009 |
20090065880 | Semiconductor Device Made by Using a Laser Anneal to Incorporate Stress into a Channel Region - In one aspect there is provided a method of manufacturing a semiconductor device comprising forming gate electrodes over a semiconductor substrate, forming source/drains adjacent the gate electrodes, depositing a stress inducing layer over the gate electrodes. A laser anneal is conducted on at least the gate electrodes subsequent to depositing the stress inducing layer at a temperature of at least about 1100° C. for a period of time of at least about 300 microseconds, and the semiconductor device is subjected to a thermal anneal subsequent to conducting the laser anneal. | 03-12-2009 |
20090072330 | Semiconductor device and manufacturing method thereof - A semiconductor device includes a substrate, a p-channel MIS transistor formed on an n-type well on the substrate, having a first gate dielectric and a first gate electrode formed thereon and formed of a Ta—C alloy wherein a crystal orientation ratio of a TaC (111) face in a film thickness direction [TaC (111) face/{TaC (111) face+TaC (200) face}] is 80% or more, and an n-channel MIS transistor formed on a p-type well on the substrate, having a second gate dielectric and a second gate electrode formed thereon and formed of a Ta—C alloy wherein a crystal orientation ratio of a TaC (111) face in a film thickness direction [TaC (111) face/{TaC (111) face+TaC (200) face}] is 60% or less. | 03-19-2009 |
20090072331 | Semiconductor device and manufacturing method thereof - A semiconductor device includes a substrate, a p-channel MIS transistor formed on an n-type well on the substrate, having a first gate dielectric and a first gate electrode formed thereon and formed of a Ta—C alloy wherein a crystal orientation ratio of a TaC (111) face in a film thickness direction [TaC (111) face/{TaC (111) face+TaC (200) face}] is 80% or more, and an n-channel MIS transistor formed on a p-type well on the substrate, having a second gate dielectric and a second gate electrode formed thereon and formed of a Ta—C alloy wherein a crystal orientation ratio of a TaC (111) face in a film thickness direction [TaC (111) face/{TaC (111) face+TaC (200) face}] is 60% or less. | 03-19-2009 |
20090090986 | FULLY AND UNIFORMLY SILICIDED GATE STRUCTURE AND METHOD FOR FORMING SAME - Fully and uniformly silicided gate conductors are produced by deeply “perforating” silicide gate conductors with sub-lithographic, sub-critical dimension, nanometer-scale openings. A silicide-forming metal (e.g. cobalt, tungsten, etc.) is then deposited, polysilicon gates, covering them and filling the perforations. An anneal step converts the polysilicon to silicide. Because of the deep perforations, the surface area of polysilicon in contact with the silicide-forming metal is greatly increased over conventional silicidation techniques, causing the polysilicon gate to be fully converted to a uniform silicide composition. A self-assembling diblock copolymer is used to form a regular sub-lithographic nanometer-scale pattern that is used as an etching “template” for forming the perforations. | 04-09-2009 |
20090101994 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A semiconductor device and a method for fabricating the same are disclosed. The semiconductor device includes a semiconductor substrate having an active region and a device isolation region defining the active region, and a resistor string formed over the active region. | 04-23-2009 |
20090101995 | PROCESS FOR FABRICATION OF FINFETs - A method of fabricating a plurality of FinFETs on a semiconductor substrate in which the gate width of each individual FinFET is defined utilizing only a single etching process, instead of two or more, is provided. The inventive method results in improved gate width control and less variation of the gate width of each individual gate across the entire surface of the substrate. The inventive method achieves the above by utilizing a modified sidewall image transfer (SIT) process in which an insulating spacer that is later replaced by a gate conductor is employed and a high-density bottom up oxide fill is used to isolate the gate from the substrate. | 04-23-2009 |
20090108378 | STRUCTURE AND METHOD FOR FABRICATING SELF-ALIGNED METAL CONTACTS - A semiconductor structure including at least one transistor is provided which has a stressed channel region that is a result of having a stressed layer present atop a gate conductor that includes a stack comprising a bottom polysilicon (polySi) layer and a top metal semiconductor alloy (i.e., metal silicide) layer. The stressed layer is self-aligned to the gate conductor. The inventive structure also has a reduced external parasitic S/D resistance as a result of having a metallic contact located atop source/drain regions that include a surface region comprised of a metal semiconductor alloy. The metallic contact is self-aligned to the gate conductor. | 04-30-2009 |
20090108379 | SEMICONDUCTOR DEVICE AND FABRICATION METHOD FOR THE SAME - The semiconductor device includes: a transistor having a gate electrode formed on a semiconductor substrate and first and second source/drain regions formed in portions of the semiconductor substrate on both sides of the gate electrode; a gate interconnect formed at a position opposite to the gate electrode with respect to the first source/drain region; and a first silicon-germanium layer formed on the first source/drain region to protrude above the top surface of the semiconductor substrate. The gate interconnect and the first source/drain region are connected via a local interconnect structure that includes the first silicon-germanium layer. | 04-30-2009 |
20090115002 | Semiconductor Device - There is provided a semiconductor device including: a first field effect transistor region including a gate insulating film, a gate electrode and gate sidewalls formed in a P channel forming region; and a second field effect transistor region including a gate insulating film, a gate electrode and gate sidewalls formed in an N channel forming region on a semiconductor substrate, wherein in the first and second field effect transistor regions, the gate electrodes are composed primarily of a silicide of metal M represented as M(x)Si(1−x)(005-07-2009 | |
20090115003 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A method for fabricating a semiconductor device includes forming a stacked layer including a tungsten layer, forming a hard mask pattern over the stacked layer, and oxidizing a surface of the hard mask pattern to form a stress buffer layer. A portion of the stacked layer uncovered by the hard mask pattern is removed using the hard mask pattern and the stress buffer layer as an etch mask, thereby forming a first resultant structure. A capping layer is formed over the first resultant structure, the capping layer is etched to retain the capping layer on sidewalls of the first resultant structure, and the remaining portion of the stacked layer uncovered by the hard mask pattern is removed. | 05-07-2009 |
20090121298 | FIELD EFFECT TRANSISTOR - A transistor. The transistor including: a well region in a substrate; a gate dielectric layer on a top surface of the well region; a polysilicon gate electrode on a top surface of the gate dielectric layer; spacers formed on opposite sidewalls of the polysilicon gate electrode; source/drain regions formed on opposite sides of the polysilicon gate electrode in the well region; a first doped region in the polysilicon gate electrode, the first doped region extending into the polysilicon gate electrode from a top surface of the polysilicon gate electrode; and a buried second doped region in the polysilicon gate electrode. | 05-14-2009 |
20090152652 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE AND THE SEMICONDUCTOR DEVICE - Described herein is a method of manufacturing a semiconductor device realizing higher performance by reducing contact resistance of an electrode. In the method, a gate insulating film, a gate electrode are formed on a semiconductor substrate. A first metal is deposited substrate, and a metal semiconductor compound layer is formed on the surface of the semiconductor substrate by making the first metal and the semiconductor substrate react each other by a first heat treatment. Ions having a mass equal to or larger than atomic weight of Si are implanted into the metal semiconductor compound layer. A second metal is deposited on the metal semiconductor compound layer. An interface layer is formed by making the second metal segregated at an interface between the metal semiconductor compound layer and the semiconductor substrate by diffusing the second metal through the metal semiconductor compound layer by a second heat treatment. | 06-18-2009 |
20090159992 | SEMICONDUCTOR DEVICE HAVING A POLYSILICON ELECTRODE - A method of manufacturing a semiconductor device such as a MOS transistor. The device comprises a polysilicon gate ( | 06-25-2009 |
20090159993 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A semiconductor device and/or a method for manufacturing a semiconductor device. A method may include at least one of the following: Forming a first oxide layer on a silicon substrate. Depositing a polysilicon layer on the first oxide layer. Forming a pattern on the polysilicon layer and the first oxide layer to expose a portion of the silicon substrate forming a polysilicon layer pattern and a first oxide layer pattern. Forming a second oxide layer on the entire surface of the silicon substrate. Forming a pattern on the second oxide layer to expose a portion of the silicon substrate. Growing a silicon on the exposed silicon substrate to form a silicon epitaxial layer. Removing the second oxide layer formed on the polysilicon layer pattern. | 06-25-2009 |
20090166769 | METHODS FOR FABRICATING PMOS METAL GATE STRUCTURES - Methods of forming a microelectronic structure are described. Those methods may include forming a gate dielectric layer on a substrate, forming a metal gate layer on the gate dielectric layer, and then forming a polysilicon layer on the metal gate layer in situ, wherein the metal gate layer is not exposed to air. | 07-02-2009 |
20090166770 | METHOD OF FABRICATING GATE ELECTRODE FOR GATE OF MOSFET AND STRUCTURE THEREOF - A method of fabricating a gate electrode for a gate of a metal oxide semiconductor field effect transistor (MOSFET), where the transistor has a structure incorporating a gate disposed on a substrate. The substrate comprises a source-drain region. The gate includes a gate electrode disposed on a gate dielectric and surrounded by a spacer. The gate electrode includes a capping layer of polysilicon (poly-Si) and a thin polycrystalline intermixed silicon-germanium (SiGe) layer superposed on the gate dielectric. The thin polycrystalline intermixed silicon-germanium (SiGe) layer may be formed by a high-temperature ultrafast melt-crystalization annealing process. The melt-crystallization process of the intermixed silicon-germanium provides an active dopant concentration that reduces the width of a depletion region formed at an interface of the polycrystalline intermixed silicon-germanium (SiGe) layer and the gate dielectric. | 07-02-2009 |
20090189229 | Semiconductor devices and methods of fabricating the same - Provided are semiconductor devices and methods of fabricating the same, and more specifically, semiconductor devices having a W—Ni alloy thin layer that has a low resistance, and methods of fabricating the same. The semiconductor devices include the W—Ni alloy thin layer. The weight of Ni in the W—Ni alloy thin layer may be in a range from approximately 0.01 to approximately 5.0 wt % of the total weight of the W—Ni alloy thin layer. | 07-30-2009 |
20090206421 | ORGANIC LIGHT EMITTING DISPLAY AND MANUFACTURING METHOD THEREOF - Disclosed are an organic light emitting display and a manufacturing method thereof. The organic light emitting display includes an organic light emitting section that generates a light, a first thin film transistor that drives the organic light emitting section and includes a first polysilicon layer and a first gate electrode formed below the first polysilicon layer, and a second thin film transistor connected to the first thin film transistor and includes a second polysilicon layer and a second gate electrode formed above the second polysilicon layer. The first and second polysilicon layers are formed on the same layer. | 08-20-2009 |
20090218640 | Self Aligned Silicided Contacts - Structures and methods of forming self aligned silicided contacts are disclosed. The structure includes a gate electrode disposed over an active area, a liner disposed over the gate electrode and at least a portion of the active area, an insulating layer disposed over the liner. A first contact plug is disposed in the insulating layer and the liner, the first contact plug disposed above and in contact with a portion of the active area, the first contact plug including a first conductive material. A second contact plug is disposed in the insulating layer and the liner, the second contact plug disposed above and in contact with a portion of the gate electrode, the second contact plug includes the first conductive material. A contact material layer is disposed in the active region, the contact material layer disposed under the first contact plug and includes the first conductive material. | 09-03-2009 |
20090250773 | Semiconductor device - A semiconductor device includes a first metal region, a plurality of vias, a plurality of second metal regions, a plurality of openings and a third metal region. The first metal region conducts source/drain current. The second metal regions are electrically connected to the first metal region through the vias for conducting the source/drain current, in which each of the second metal regions is disposed in a distance from the adjacent second metal regions. The third metal region is electrically connected to the second metal regions through the openings, in which the resistance of the third metal region is smaller than the resistances of the first metal region and the second metal regions. | 10-08-2009 |
20090250774 | Gate Structure - A gate structure includes a gate insulation layer pattern, a gate electrode, a first spacer and a protecting layer pattern. The gate insulation layer pattern is on a substrate. The gate electrode is on the gate insulation layer pattern, the gate electrode including a lower portion having a first width, a central portion having a second width smaller than the first width and an upper portion having a third width. The first spacer is on a lower sidewall of the gate electrode. The protecting layer pattern is on a central sidewall of the gate electrode. | 10-08-2009 |
20090321855 | Boundaries with elevated deuterium levels - A device is annealed in a deuterium atmosphere. Deuterium penetrates the device to a boundary, which is passivated by the deuterium. | 12-31-2009 |
20100013029 | Structure and a Method of Manufacture for Low Resistance NiSix - A device and a method for forming a metal silicide is presented. A device, which includes a gate region, a source region, and a drain region, is formed on a substrate. A metal is disposed on the substrate, followed by a first anneal, forming a metal silicide on at least one of the gate region, the source region, and the drain region. The unreacted metal is removed from the substrate. The metal silicide is implanted with atoms. The implant is followed by a super anneal of the substrate. | 01-21-2010 |
20100044806 | INTEGRATED CIRCUIT METAL GATE STRUCTURE AND METHOD OF FABRICATION - A method of forming a gate structure is provided. The method includes providing a metal layer in the gate structure, the metal layer includes an oxygen-gettering composition. The metal layer getters oxygen from the interface layer, which may decrease the thickness of the interface layer. The gettered oxygen converts the metal layer to a metal oxide, which may act as a gate dielectric for the gate structure. A multi-layer metal gate structure is also provided including a oxygen-gettering metal layer, an oxygen-containing metal layer, and a polysilicon interface metal layer overlying a high-k gate dielectric. | 02-25-2010 |
20100052079 | SEMICONDUCTOR DEVICES AND FABRICATION PROCESS THEREOF - A semiconductor device has an insulated gate transistor provided with a semiconductor substrate and a gate electrode arranged on the semiconductor substrate via a gate insulating film. The gate electrode includes an electrically-conductive buffer film for preventing any damage, which would occur if a main gate electrode portion were formed directly over the gate insulating film, and the main gate electrode portion formed over the buffer film. A fabrication process for the semiconductor device is also disclosed. | 03-04-2010 |
20100065928 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - In one aspect of the present invention, a semiconductor device may include a first semiconductor layer of a first conductivity type and having a main surface that has a first plane orientation, a second semiconductor layer of the first conductivity type and having a main surface that has a second plane orientation different from the first plane orientation, the second semiconductor layer being directly provided on the first semiconductor layer, a third semiconductor layer having a main surface that has the first plane orientation, and being formed on the first semiconductor layer and on a side face of the second semiconductor layer, a gate electrode formed on the second semiconductor layer via a gate insulating film, first impurity diffusion regions of a second conductivity type, and being formed in the second semiconductor layer so that the gate electrode is located on a region sandwiched in a gate length direction between the first impurity diffusion regions, the first impurity diffusion regions extending to an interface between the first and second semiconductor layers, and second impurity diffusion regions of a second conductivity type, and being formed so as to extend from the third semiconductor layers to the first semiconductor layer, respectively, so that both the first impurity diffusion regions is sandwiched in the gate length direction between the second impurity diffusion regions. | 03-18-2010 |
20100084720 | Gate in semiconductor device and method of fabricating the same - A gate of a semiconductor device includes a substrate, and a polysilicon layer over the substrate, wherein the polysilicon layer is doped with first conductive type impurities having a concentration that decreases when receding from the substrate and counter-doped with second conductive type impurities having a concentration that increases when receding from the substrate. | 04-08-2010 |
20100102402 | METHOD OF FABRICATING A TRANSISTOR WITH SEMICONDUCTOR GATE COMBINED LOCALLY WITH A METAL - A method of forming a field effect transistor comprising a gate formed on an insulating layer, the gate having, in a zone in contact with the insulating layer, a semiconducting central zone and lateral zones in the length of the gate, the method comprising forming a gate comprising a portion of insulating layer, a portion of semiconducting layer formed over the insulating layer, and a portion of mask layer formed over the semiconducting layer; performing an etching of the portion of the mask layer such that only a portion in the centre of the gate remains; and reacting the semiconducting gate with a metal deposited over the gate. | 04-29-2010 |
20100109099 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device including a semiconductor substrate, an interface layer formed on the semiconductor substrate including at least 1×10 | 05-06-2010 |
20100117164 | SEMICONDUCTOR DEVICE WITH A LOW JFET REGION RESISTANCE - A high-voltage MOS transistor device includes a substrate, a semiconductor layer formed on the substrate, a gate structure having an opening, formed on the semiconductor layer, a first source/drain region of a first conductivity type formed in the semiconductor layer at one side of the gate structure, a second source/drain region of the first conductivity type formed in the semiconductor layer at the other side of the gate structure, a channel region disposed by a dopant of the first conductivity type between the first source/drain region and the second source/drain region, and a doping region of the first conductivity type formed in the channel region and under the opening of the gate structure, wherein a doping concentration of the doping region is higher than a doping concentration of the channel region. | 05-13-2010 |
20100123206 | METHODS OF FABRICATING FIELD EFFECT TRANSISTORS INCLUDING TITANIUM NITRIDE GATES OVER PARTIALLY NITRIDED OXIDE AND DEVICES SO FABRICATED - A gate of an integrated circuit field effect transistor is fabricated by fabricating a gate insulating layer on an integrated circuit substrate, fabricating a metal nitride layer on the gate insulating layer, annealing the metal nitride layer in a nitridizing ambient and fabricating a cap on the metal nitride layer that has been annealed. Thereafter, the cap on the metal nitride layer may be etched to expose sidewalls thereof and another anneal in a nitridizing ambient may take place. Related integrated circuit field effect transistors are also described. | 05-20-2010 |
20100140722 | Strained Semiconductor Device and Method of Making Same - To form a semiconductor device, an electrode layer is formed over a semiconductor body. The electrode layer includes an amorphous portion. A liner, e.g., a stress-inducing liner, is deposited over the electrode layer. The electrode layer is annealed to recrystallize the amorphous portion of the electrode layer. The liner can then be removed and an electronic component (e.g., a transistor) that includes a feature (e.g., a gate) formed from the electrode layer can be formed. | 06-10-2010 |
20100148281 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A semiconductor device has a gate insulating film formed on a semiconductor substrate, a second gate electrode portion of a gate electrode including a TiN film and a polysilicon film that are successively formed on the gate insulating film, and an interlayer insulating film formed on the semiconductor substrate so as to cover the gate electrode. A contact formed to extend through the interlayer insulating film and the polysilicon film is directly connected to the TiN film. | 06-17-2010 |
20100155859 | SELECTIVE SILICIDE PROCESS - A method of self-aligned silicidation on structures having high aspect ratios involves depositing a metal oxide film using atomic layer deposition (ALD) and converting the metal oxide film to metal film in order to obtain uniform step coverage. The substrate is then annealed such that the metal in regions directly overlying the patterned and exposed silicon reacts with the silicon to form uniform metal silicide at the desired locations. | 06-24-2010 |
20100155860 | TWO STEP METHOD TO CREATE A GATE ELECTRODE USING A PHYSICAL VAPOR DEPOSITED LAYER AND A CHEMICAL VAPOR DEPOSITED LAYER - One embodiment of the present invention relates a semiconductor device formed by utilizing a two step deposition method for forming a gate electrode without causing damages to an underlying gate dielectric material. In one embodiment, a first layer of gate electrode material (first gate electrode layer) is formed onto the surface of a gate dielectric material using a deposition that does not damage the gate dielectric material (e.g., physical vapor deposition) thereby resulting in a damage free interface between the gate dielectric material and the gate electrode material. A second layer of gate electrode material (second gate electrode layer) is then formed onto the first layer of gate electrode material using a chemical deposition method that provides increased deposition control (e.g., good layer uniformity, impurity control, etc.). The first and second gate electrode layers are then selectively patterned to cumulatively form a semiconductor device's gate electrode. | 06-24-2010 |
20100176461 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A method for easily manufacturing a semiconductor device in which variation in thickness or disconnection of a source electrode or a drain electrode is prevented is proposed. A semiconductor device includes a semiconductor layer formed over an insulating substrate; a first insulating layer formed over the semiconductor layer; a gate electrode formed over the first insulating layer; a second insulating layer formed over the gate electrode; an opening which reaches the semiconductor layer and is formed at least in the first insulating layer and the second insulating layer; and a step portion formed at a side surface of the second insulating layer in the opening. | 07-15-2010 |
20100176462 | METHOD OF SIMULTANEOUSLY SILICIDING A POLYSILICON GATE AND SOURCE/DRAIN OF A SEMICONDUCTOR DEVICE, AND RELATED DEVICE - A method of simultaneously siliciding a polysilicon gate and source/drain of a semiconductor device, and related device. At least some of the illustrative embodiments are methods comprising forming a gate stack over a semiconductor substrate (the gate stack comprising a first polysilicon layer, a first nitride layer, and a second polysilicon layer), forming a second nitride layer over an active region in the semiconductor substrate adjacent to the gate stack, performing a chemical mechanical polishing that stops on the first nitride layer and on the second nitride layer, removing the first nitride layer and the second nitride layer, and performing a simultaneous silicidation of the first polysilicon layer and the active region. | 07-15-2010 |
20100237445 | MISFET, SEMICONDUCTOR DEVICE HAVING THE MISFET AND METHOD FOR MANUFACTURING THE SAME - To solve the problem, a MISFET covered with an insulating film which generates stress is provided. The MISFET including a gate insulating film; a gate electrode disposed on the gate insulating film, the gate electrode including a polysilicon portion and a silicide portion; and a source/drain disposed adjacent to the gate electrode, in which the ratio between the polysilicon portion and the silicide portion is determined depending on a strain for enhancing the driving capability of the MISFET, the strain being generated on the basis of the stress through the gate electrode in a channel region of the MISFET. | 09-23-2010 |
20100244158 | SEMICONDUCTOR STRUCTURES RESULTING FROM SELECTIVE OXIDATION - Methods for selectively oxidizing a semiconductor structure include generating a gas cluster ion beam comprising an oxidizing source gas, directing the gas cluster ion beam to a region of a substrate adjacent a conductive line and exposing the region to the gas cluster ion beam including an oxidizing matter. Utilizing the gas cluster ion beam enables selective oxidation of a targeted region at temperatures substantially lower than those of typical oxidation processes thus, reducing or eliminating oxidation of the conductive line. Semiconductor devices including transistors formed using such methods are also disclosed. | 09-30-2010 |
20100276764 | SEMICONDUCTOR STRUCTURE WITH SELECTIVELY DEPOSITED TUNGSTEN FILM AND METHOD FOR MAKING THE SAME - A semiconductor structure is provided. The semiconductor structure includes a substrate; a dielectric layer overlying the substrate; a conductor pattern on a main surface of the dielectric layer, the conductor pattern having a top surface and sidewalls; and a conformal metal layer selectively deposited on the top surface and sidewalls, but without deposited on the main surface of the dielectric layer substantially. | 11-04-2010 |
20100314698 | METHODS OF MANUFACTURING METAL-SILICIDE FEATURES - A method of manufacturing a microelectronic device including forming a dielectric layer surrounding a dummy feature located over a substrate, removing the dummy feature to form an opening in the dielectric layer, and forming a metal-silicide layer conforming to the opening. The metal-silicide layer may then be annealed. | 12-16-2010 |
20110031563 | Method for Manufacturing a Semiconductor Device Having Doped and Undoped Polysilicon Layers - Various illustrative embodiments of methods for manufacturing a semiconductor device are described. These methods may include, for example, forming a first polysilicon layer above a substrate, wherein the first polysilicon layer comprises a doped portion, and forming a second polysilicon layer over a surface of the first polysilicon layer. Also, various illustrative embodiments of semiconductor devices are described that may be manufactured such as by the various methods described herein. | 02-10-2011 |
20110042760 | SEMICONDUCTOR DEVICE WITH GATE STRUCTURE - A gate structure of a semiconductor device includes an intermediate structure, wherein the intermediate structure includes a titanium layer and a tungsten silicide layer. A method for forming a gate structure of a semiconductor device includes forming a polysilicon-based electrode. An intermediate structure, which includes a titanium layer and a tungsten silicide layer, is formed over the polysilicon-based electrode. A metal electrode is formed over the intermediate structure. | 02-24-2011 |
20110062530 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device includes: a semiconductor substrate; an interface layer formed on the semiconductor substrate; a high-k gate dielectric film formed on the interface layer; and a gate electrode formed on the high-k gate dielectric film. The high-k gate dielectric film contains La. The high-k gate dielectric film has the higher La concentration in an interface with the gate electrode than in an interface with the interface layer. | 03-17-2011 |
20110073965 | GATE PATTERN OF SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A method for fabricating a semiconductor device includes forming a recess pattern by selectively etching a substrate; forming a gate dielectric layer filling the recess pattern on the substrate; forming a groove by selectively etching the gate dielectric layer; forming a polysilicon electrode filling the groove; forming an electrode metal layer on the polysilicon electrode and the gate dielectric layer; and forming a gate pattern by etching the electrode metal layer and the gate dielectric layer. The recess pattern is formed along an edge portion of the gate pattern as a quadrilateral periphery. | 03-31-2011 |
20110095380 | SEMICONDUCTOR DEVICE - A semiconductor device includes a silicon substrate, and a NiSi layer provided on the silicon substrate aiming to suppress oxidation of the surface of a NiSi layer and the resistivity increase. The NiSi layer includes a bottom NiSi region and a top NiSi region. The bottom NiSi region provided in contact with silicon surface, and containing substantially no nitrogen. The top NiSi region is a nitrided NiSi region provided in contact with the bottom NiSi region, and containing nitrogen. The NiSi layer has a total thickness of 50 nm or below. | 04-28-2011 |
20110101472 | STRUCTURE AND METHOD TO FORM A THERMALLY STABLE SILICIDE IN NARROW DIMENSION GATE STACKS - An integrated circuit is provided including a narrow gate stack having a width less than or equal to 65 nm, including a silicide region comprising Pt segregated in a region of the silicide away from the top surface of the silicide and towards an lower portion defined by a pulldown height of spacers on the sidewalls of the gate conductor. In a preferred embodiment, the spacers are pulled down prior to formation of the silicide. The silicide is first formed by a formation anneal, at a temperature in the range 250° C. to 450° C. Subsequently, a segregation anneal at a temperature in the range 450° C. to 550° C. The distribution of the Pt along the vertical length of the silicide layer has a peak Pt concentration within the segregated region, and the segregated Pt region has a width at half the peak Pt concentration that is less than 50% of the distance between the top surface of the silicide layer and the pulldown spacer height. | 05-05-2011 |
20110108930 | Borderless Contacts For Semiconductor Devices - In one exemplary embodiment of the invention, a method (e.g., to fabricate a semiconductor device having a borderless contact) including: forming a first gate structure on a substrate; depositing an interlevel dielectric over the first gate structure; planarizing the interlevel dielectric to expose a top surface of the first gate structure; removing at least a portion of the first gate structure; forming a second gate structure in place of the first gate structure; forming a contact area for the borderless contact by removing a portion of the interlevel dielectric; and forming the borderless contact by filling the contact area with a metal-containing material. | 05-12-2011 |
20110121410 | Semiconductor Contact Barrier - System and method for reducing contact resistance and improving barrier properties is provided. An embodiment comprises a dielectric layer and contacts extending through the dielectric layer to connect to conductive regions. A contact barrier layer is formed between the conductive regions and the contacts by electroless plating the conductive regions after openings have been formed through the dielectric layer for the contact. The contact barrier layer is then treated to fill the grain boundary of the contact barrier layer, thereby improving the contact resistance. In another embodiment, the contact barrier layer is formed on the conductive regions by electroless plating prior to the formation of the dielectric layer. | 05-26-2011 |
20110140207 | METAL GATE STRUCTURE AND METHOD OF FORMING THE SAME - The metal gate structure of the present invention can include a TiN complex, and the N/Ti proportion of the TiN complex is decreased from bottom to top. In one embodiment, the TiN complex can include a single TiN layer, which has an N/Ti proportion gradually decreasing from bottom to top. In another embodiment, the TiN complex can include a plurality of TiN layers stacking together. In such a case, the lowest TiN layer has a higher N/Ti proportion than the adjusted TiN layer. | 06-16-2011 |
20110147858 | METAL GATE STRUCTURE OF A FIELD EFFECT TRANSISTOR - The invention relates to integrated circuit fabrication, and more particularly to a Field Effect Transistor with a low resistance metal gate electrode. An exemplary structure for a gate electrode for a Field Effect Transistor comprises a lower portion formed of a first metal material having a recess and a first resistance; and an upper portion formed of a second metal material having a protrusion and a second resistance, wherein the protrusion extends into the recess, wherein the second resistance is lower than the first resistance. | 06-23-2011 |
20110193182 | FIELD EFFECT TRANSISTOR AND SEMICONDUCTOR DEVICE - An object is to provide a field effect transistor (FET) having a conductor-semiconductor junction, which has excellent characteristics, which can be manufactured through an easy process, or which enables high integration. Owing to the junction between a semiconductor layer and a conductor having a work function lower than the electron affinity of the semiconductor layer, a region into which carriers are injected from the conductor is formed in the semiconductor layer. Such a region is used as an offset region of the FET or a resistor of a semiconductor circuit such as an inverter. Further, in the case of setting up such an offset region and a resistor in one semiconductor layer, an integrated semiconductor device can be manufactured. | 08-11-2011 |
20110198710 | DIELECTRIC LAYER FOR SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device comprises a silicate interface layer and a high-k dielectric layer overlying the silicate interface layer. The high-k dielectric layer comprises metal alloy oxides. | 08-18-2011 |
20110210406 | STRUCTURES OF AND METHODS OF FABRICATING SPLIT GATE MIS DEVICES - A split gate field effect transistor device. The device includes a split gate structure having a trench, a gate electrode and a source electrode. A first poly layer is disposed within the trench and is connected to the gate electrode. A second poly layer connected to the source electrode, wherein the first poly layer and the second poly layer are independent. | 09-01-2011 |
20110215426 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - According to one embodiments, an impurity that is introduced into a gate electrode and includes phosphorus or arsenic, a carbon that is introduced into the gate electrode, and an impurity diffusion layer that is formed in a semiconductor substrate to be arranged on both sides of the gate electrode are included, in which a coverage of an active region in which the gate electrode and the impurity diffusion layer are formed is 50% or more and an area thereof is 0.02 mm | 09-08-2011 |
20110227172 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - In order that a top surface of a gate electrode does not have sharp portions, ends of the top surface of the gate electrode are rounded before refractory metal is deposited for silicidation. This reduces intensive application of film stresses which are generated in heat treatment, enabling formation of a silicide layer with a uniform, sufficient thickness. | 09-22-2011 |
20110241132 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - The semiconductor device includes a thin film transistor; a first interlayer insulating film over the thin film transistor; a first electrode electrically connected to one of a source region and a drain region, over the first interlayer insulating film; a second electrode electrically connected to the other of the source region and the drain region; a second interlayer insulating film formed over the first interlayer insulating film, the first electrode, and the second electrode; a first wiring electrically connected to one of the first electrode and the second electrode, on the second interlayer insulating film; and a second wiring not electrically connected to the other of the first electrode and the second electrode, on the second interlayer insulating film; in which the second wiring is not electrically connected to the other of the first electrode and the second electrode by a separation region formed in the second interlayer insulating film. | 10-06-2011 |
20110248362 | SELF-ALIGNED CONTACTS - A method of forming a gate structure with a self-aligned contact is provided and includes sequentially depositing a sacrificial layer and a secondary layer onto poly-Si disposed at a location of the gate structure, encapsulating the sacrificial layer, the secondary layer and the poly-Si, removing the sacrificial layer through openings formed in the secondary layer and forming silicide within at least the space formally occupied by the sacrificial layer. | 10-13-2011 |
20110260264 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - There is provided a semiconductor device and a method of fabricating the same. The method of fabricating a semiconductor device according to the present invention comprises: forming a transistor structure including a gate, and source and drain regions on a semiconductor substrate; carrying out a first silicidation to form a first metal silicide layer on the source and drain regions; depositing a first dielectric layer on the substrate, the top of the first dielectric layer being flush with the top of the gate region; forming contact holes at the portions corresponding to the source and drain regions in the first dielectric layer; and carrying out a second silicidation to form a second metal silicide at the gate region and in the contact holes, wherein the first metal silicide layer is formed to prevent silicidation from occurring at the source and drain regions during the second silicidation. According to the present invention, it is possible not only to reduce the gate resistance, but also to eliminate difficulties in forming contact holes by RIE at the gate and source/drain regions. | 10-27-2011 |
20110266638 | Semiconductor Device Comprising Contact Elements and Metal Silicide Regions Formed in a Common Process Sequence - A metal silicide in sophisticated semiconductor devices may be provided in a late manufacturing stage on the basis of contact openings, wherein the deposition of the contact material, such as tungsten, may be efficiently combined with the silicidation process. In this case, the thermally activated deposition process may initiate the formation of a metal silicide in highly doped semiconductor regions. | 11-03-2011 |
20110272767 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - There is provided a semiconductor device and a method of fabricating the same. The method comprises: providing a semiconductor substrate; forming a transistor structure on the semiconductor substrate, wherein the transistor structure comprises a gate region and a source/drain region, and the gate region comprises a gate dielectric layer provided on the semiconductor substrate and a sacrificial gate formed on the gate dielectric layer; depositing a first interlayer dielectric layer, and planarizing the first interlayer dielectric layer to expose the sacrificial gate; removing the sacrificial gate to form a replacement gate hole; forming first contact holes at positions corresponding to the source/drain region in the first interlayer dielectric layer; and filling a first conductive material in the first contact holes and the replacement gate hole respectively to form first contacts and a replacement gate, wherein the first contacts come into contact with the source/drain region. Thereby, the replacement gate and the first contacts can be made in one same step of depositing the same material, and thus the process flows are simplified. | 11-10-2011 |
20110291206 | Semiconductor Device and Method of Manufacturing a Semiconductor Device - A semiconductor device and a method of manufacturing a gate stack for such a semiconductor device. The device includes a gate stack that has a gate insulation layer provided over a channel region of the device, and a metal layer that is insulated from the channel region by the gate insulation layer. The metal layer contains work function modulating impurities which have a concentration profile that varies along a length of the metal layer from the source region to the drain region. The gate stack has a first effective work function in the vicinity of a source region and/or the drain region of the device and a second, different effective work function toward a centre of the channel region. | 12-01-2011 |
20110303991 | TRANSISTOR PERFORMANCE IMPROVING METHOD WITH METAL GATE - The present disclosure provides a method for making a semiconductor device having metal gate stacks. The method includes forming a high k dielectric material layer on a semiconductor substrate; forming a first metal layer on the high k dielectric material layer; forming a silicon layer on the first metal layer; patterning the silicon layer, the first metal layer and the high k dielectric material layer to form a gate stack; and performing a silicidation process to fully change the silicon layer into a silicide electrode. | 12-15-2011 |
20110309457 | Method for Forming a Notched Gate Insulator for Advanced MIS Semiconductor Devices and Devices Thus Obtained - Methods of providing a semiconductor device with a control electrode structure having a controlled overlap between control electrode and first and second main electrode extensions without many spacers are disclosed. A preferred method provides a step of etching back an insulating layer performed after amorphizing and implanting the main electrode extensions. Preferably, the step that amorphizes the extensions also partly amorphizes the insulating layer. Because etch rates of amorphous insulator and crystalline insulator differ, the amorphized portion of the insulating layer may serve as a natural etch stop to enable even better fine-tuning of the overlap. Corresponding semiconductor devices are also provided. | 12-22-2011 |
20120012947 | SEMICONDUCTOR DEVICE - A semiconductor device includes a gate pad, a gate wiring conductor connected to the gate pad, and a gate electrode formed under the gate pad and the gate wiring conductor. Portions of the gate electrode closer to the gate pad have a higher resistance per unit area than portions of the gate electrode farther away from the gate pad. | 01-19-2012 |
20120012948 | METAL GATE SEMICONDUCTOR DEVICE - A semiconductor device includes a semiconductor substrate, a source and a drain region formed on the semiconductor substrate, and a gate structure disposed on the substrate between the source and drain regions. The gate structure includes an interfacial layer formed over the substrate, a high-k dielectric formed over the interfacial layer, and a metal gate formed over the high-k dielectric that includes a first metal layer and a second metal layer, where the first metal layer is formed on a portion of the sidewalls of the gate structure and where the second metal layer is formed on another portion of the sidewalls of the gate structure. | 01-19-2012 |
20120056278 | Method for Manufacturing Contacts for a Semiconductor Device, and Semiconductor Device Having Such Contacts - A manufacturing method for contacts for a semiconductor device and a semiconductor device having said contacts, said method forms contact structures whose lower part consists of a plurality of contact holes and whose upper part consists of a trench contact, said contact holes having relatively smaller diameters, and the trench contacts having relatively larger contact areas. Thus contact holes with smaller diameters and trench contacts having larger contact areas can be easily connected to the metal layer above them, thereby improving the electrical conductivity of the contacts and improving the overall performances of the device. | 03-08-2012 |
20120126343 | Self Aligned Silicided Contacts - Structures and methods of forming self aligned silicided contacts are disclosed. The structure includes a gate electrode disposed over an active area, a liner disposed over the gate electrode and at least a portion of the active area, an insulating layer disposed over the liner. A first contact plug is disposed in the insulating layer and the liner, the first contact plug disposed above and in contact with a portion of the active area, the first contact plug including a first conductive material. A second contact plug is disposed in the insulating layer and the liner, the second contact plug disposed above and in contact with a portion of the gate electrode, the second contact plug includes the first conductive material. A contact material layer is disposed in the active region, the contact material layer disposed under the first contact plug and includes the first conductive material. | 05-24-2012 |
20120146160 | HIGH-K METAL GATE DEVICE - A method of forming a semiconductor device is presented. The method includes providing a substrate. The method further includes forming a gate stack having a gate electrode on the substrate, which includes forming a metal gate electrode layer. A buffer gate electrode layer is formed on top of the metal gate electrode layer and a top gate electrode layer having a poly-silicon alloy is formed over the metal gate electrode layer. | 06-14-2012 |
20120146161 | NANOWIRE FABRICATION METHOD AND SEMICONDUCTOR ELEMENT USING NANOWIRE FABRICATED THEREBY - The present invention discloses a nanowire fabrication method and a semiconductor element using a nanowire fabricated thereby. The method of the present invention comprises steps: providing a substrate; sequentially depositing a silicon dioxide layer and a silicon nitride layer on the substrate; forming a patterned photoresist layer on the silicon nitride layer; using the patterned photoresist layer as a mask to etch the silicon nitride layer and the silicon dioxide layer with the substrate partly etched away to form a protrusion; removing the patterned photoresist layer to form an isolation layer; removing the silicon nitride and the silicon dioxide layer, sequentially depositing a dielectric layer and a polysilicon layer; and anisotropically etching the polysilicon layer to form nanowires on a region of the dielectric layer, which is around sidewalls of the protrusion. | 06-14-2012 |
20120161252 | FORMING CONFORMAL METALLIC PLATINUM ZINC FILMS FOR SEMICONDUCTOR DEVICES - Forming conformal platinum-zinc films for semiconductor devices is described. In one example, a conformal film is formed by heating a substrate in a reaction chamber, exposing a desired region of the substrate to a precursor that contains platinum, purging excess precursor from the chamber, exposing the desired region of the substrate to a co-reactant containing zinc to cause a reaction between the precursor and the co-reactant to form a platinum zinc film on the desired region, and purging the chamber of excess reaction by-products. | 06-28-2012 |
20120181634 | Method of Introducing Strain Into Channel and Device Manufactured by Using the Method - The present invention relates to a method of introducing strain into a channel and a device manufactured by using the method, the method comprising: providing a semiconductor substrate; forming a channel in the semiconductor substrate; forming a first gate dielectric layer on the channel; forming a polysilicon gate layer on the first gate dielectric layer; doping or implanting a first element into the polysilicon gate layer; removing a part of the first gate dielectric layer and polysilicon gate layer to thereby form a first gate structure; forming a source/drain extension region in the channel; forming spacers on both sides of the first gate structure; forming a source/drain in the channel; and performing annealing such that lattice change occurs in the polysilicon that is doped or implanted with the first element in the high-temperature crystallization process, thereby producing a first strain in the polysilicon gate layer, and introducing the first strain through the gate dielectric layer to the channel. This method has greater process flexibility and simple process complexity with no additional process cost. | 07-19-2012 |
20120181635 | Semiconductor device - In a method of the present invention during a salicide process, before a second thermal process, a dopant is implanted at a place located in a region ranging from a Ni | 07-19-2012 |
20120181636 | Printing of Contact Metal and Interconnect Metal Via Seed Printing and Plating - Methods of forming contacts (and optionally, local interconnects) using an ink comprising a silicide-forming metal, electrical devices such as diodes and/or transistors including such contacts and (optional) local interconnects, and methods for forming such devices are disclosed. Electrical devices, such as diodes and transistors may be made using such printed contact and/or local interconnects. A metal ink may be printed for contacts as well as for local interconnects at the same time, or in the alternative, the printed metal can act as a seed for electroless deposition of other metals if different metals are desired for the contact and the interconnect lines. This approach advantageously reduces the number of processing steps and does not necessarily require any etching. | 07-19-2012 |
20120193729 | DEVICES AND METHODS TO OPTIMIZE MATERIALS AND PROPERTIES FOR REPLACEMENT METAL GATE STRUCTURES - Devices and methods for device fabrication include forming a gate structure with a sacrificial material. Silicided regions are formed on source/drain regions adjacent to the gate structure or formed at the bottom of trench contacts within source/drain areas. The source/drain regions or the silicided regions are processed to build resistance to subsequent thermal processing and adjust Schottky barrier height and thus reduce contact resistance. Metal contacts are formed in contact with the silicided regions. The sacrificial material is removed and replaced with a replacement conductor. | 08-02-2012 |
20120217592 | SEMICONDUCTOR DEVICE AND METHOD FOR FORMING THE SAME - It is provided a method for forming a semiconductor device, the semiconductor device comprising a PMOS device, wherein forming the PMOS device comprises: removing the sidewall spacer so as to form a void; and filling the void with an assistant layer, the assistant layer having a first compressive stress. Alternatively, a gate is formed in the PMOS device, the gate having a second compressive stress; the sidewall spacer is removed, so as to form a void; and the void is filled with an assistant layer. A semiconductor device comprising a PMOS device, the PMOS device comprising: an assistant layer, the assistant layer being formed on a semiconductor substrate, the assistant layer surrounding both a gate and a gate dielectric layer, or surrounding the gate and positioned on the gate dielectric layer, wherein the assistant layer has a first compressive stress, or the assistant layer has a first compressive stress and the gate has a second compressive stress, so as to produce a compressive stress in the channel region of the PMOS device. This helps to improve the device performance | 08-30-2012 |
20120223399 | SEMICONDUCTOR DEVICE WITH ISOLATION TRENCH LINER - A semiconductor device includes a layer of semiconductor material having an active transistor region defined therein, an isolation trench formed in the semiconductor material adjacent the active transistor region, and a trench liner lining the isolation trench, wherein the trench liner is formed from a material that substantially inhibits formation of high-k material thereon, and wherein the isolation trench and the trench liner together form a lined trench. The device has an insulating material in the lined trench, and high-k gate material overlying at least a portion of the insulating material and overlying at least a portion of the active transistor region, such that the trench liner divides and separates the high-k gate material overlying the at least a portion of the insulating material from the high-k gate material overlying the at least a portion of the active transistor region. | 09-06-2012 |
20120248551 | MOL INSITU PT REWORK SEQUENCE - The amount of Pt residues remaining after forming Pt-containing NiSi is reduced by performing an O | 10-04-2012 |
20120256279 | METHOD OF GATE WORK FUNCTION ADJUSTMENT AND METAL GATE TRANSISTOR - A method of gate work function adjustment includes the steps as follow. First, a substrate is provided, wherein a metal gate is disposed on the substrate, a source doping region and a drain doping region are disposed in the substrate at opposite sites of the metal gate, wherein the metal gate is divided into a source side adjacent to the source doping region, and a drain side adjacent to the drain doping region. Later, a mask layer is formed to cover the source doping region and the drain doping region. After that, an implantation process is performed to implant nitrogen into the metal gate so as to make a first nitrogen concentration of the source side higher than a second nitrogen concentration of the drain side. Finally, the mask layer is removed. | 10-11-2012 |
20120261773 | SEMICONDUCTOR DEVICE, METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE AND SYSTEM OF PROCESSING SUBSTRATE - Disclosed is a semiconductor device that comprises a gate insulating film formed on a semiconductor substrate; a first conductive metal-containing film formed on the gate insulating film; a second conductive metal-containing film, formed on the first metal-containing film, to which aluminum is added; and a silicon film formed on the second metal-containing film. | 10-18-2012 |
20120267728 | Dummy Structures and Methods - A semiconductor device and a method of making a semiconductor device are disclosed. The method of manufacturing a semiconductor device comprises forming a material layer on a substrate, patterning a first semi-global region with a first main pattern and patterning a second semi-global region with a second main pattern, wherein the first main pattern is different than the second main pattern. The method further comprises introducing a first dummy pattern in the first semi-global region so that a first sidewall area surface density of the first main pattern and the first dummy pattern in the first semi-global region and a second sidewall area surface density of the second main pattern in the second semi-global region are substantially a same density. | 10-25-2012 |
20120286375 | PRESERVING STRESS BENEFITS OF UV CURING IN REPLACEMENT GATE TRANSISTOR FABRICATION - A method of forming a semiconductor structure includes forming a stress inducing layer over one or more partially completed field effect transistor (FET) devices disposed over a substrate, the one or more partially completed FET devices including sacrificial dummy gate structures; planarizing the stress inducing layer and removing the sacrificial dummy gate structures; and following the planarizing the stress inducing layer and removing the sacrificial dummy gate structures, performing an ultraviolet (UV) cure of the stress inducing layer so as to enhance a value of an initial applied stress by the stress inducing layer on channel regions of the one or more partially completed FET devices. | 11-15-2012 |
20120286376 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A semiconductor device is disclosed. The semiconductor device includes: a substrate having a region; a gate structure disposed on the region of the substrate; a raised epitaxial layer disposed in the substrate adjacent to two sides of the gate structure, wherein the surface of the raised epitaxial layer is even with the surface of the gate structure. | 11-15-2012 |
20120292721 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - A method of fabricating a semiconductor device includes following steps. A substrate is provided, wherein a first dielectric layer having a trench therein is formed on the substrate, a source/drain region is formed in the substrate at two sides of the trench, and a second dielectric layer is formed on the substrate in the trench. A first physical vapor deposition process is performed to form a Ti-containing metal layer in the trench. A second physical vapor deposition process is performed to form an Al layer on the Ti-containing metal layer in the trench. A thermal process is performed to anneal the Ti-containing metal layer and the Al layer so as to form a work function metal layer. A metal layer is formed to fill the trench. | 11-22-2012 |
20120306029 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - To provide a semiconductor device with a TFT, capable of reducing the electric resistance of a power supply wiring without increasing the off-current. The semiconductor device includes an insulating film with a surface; a semiconductor layer which is formed over the surface of the insulating film and which includes a channel region and a pair of source/drain regions and sandwiching the channel region; and a power supply wiring for supplying power to the source region. A concave portion is formed in the surface of the insulating film. The power supply wiring includes a layer formed from the same layer as the semiconductor layer, and has a first portion formed over the surface of the insulating film and a second portion formed in the concave portion. The bottom of the second portion is covered with an insulator. | 12-06-2012 |
20120313187 | Method of Removing Gate Cap Materials While Protecting Active Area - Disclosed herein is a method of forming a semiconductor device. In one example, the method includes forming a gate electrode structure above a semiconducting substrate, wherein the gate electrode structure includes a gate insulation layer, a gate electrode, a first sidewall spacer positioned proximate the gate electrode, and a gate cap layer, and forming an etch stop layer above the gate cap layer and above the substrate proximate the gate electrode structure. The method further includes forming a layer of spacer material above the etch stop layer, and performing at least one first planarization process to remove the portion of said layer of spacer material positioned above the gate electrode, the portion of the etch stop layer positioned above the gate electrode and the gate cap layer. | 12-13-2012 |
20120313188 | SEMICONDUCTOR DEVICE - A semiconductor device includes, on a semiconductor substrate, a gate insulating film, a pMIS metal material or an nMIS metal material, a gate electrode material, and a gate sidewall metal layer. | 12-13-2012 |
20130020658 | REPLACEMENT GATE ELECTRODE WITH PLANAR WORK FUNCTION MATERIAL LAYERS - In a replacement gate scheme, a continuous material layer is deposited on a bottom surface and a sidewall surface in a gate cavity. A vertical portion of the continuous material layer is removed to form a gate component of which a vertical portion does not extend to a top of the gate cavity. The gate component can be employed as a gate dielectric or a work function material portion to form a gate structure that enhances performance of a replacement gate field effect transistor. | 01-24-2013 |
20130032901 | FULL SILICIDATION PREVENTION VIA DUAL NICKEL DEPOSITION APPROACH - Semiconductor devices are formed without full silicidation of the gates and with independent adjustment of silicides in the gates and source/drain regions. Embodiments include forming a gate on a substrate, forming a nitride cap on the gate, forming a source/drain region on each side of the gate, forming a first silicide in each source/drain region, removing the nitride cap subsequent to the formation of the first silicide, and forming a second silicide in the source/drain regions and in the gate, subsequent to removing the nitride cap. Embodiments include forming the first silicide by forming a first metal layer on the source/drain regions and performing a first RTA, and forming the second silicide by forming a second metal layer on the source/drain regions and on the gate and performing a second RTA. | 02-07-2013 |
20130043546 | Semiconductor Contact Barrier - System and method for reducing contact resistance and improving barrier properties is provided. An embodiment comprises a dielectric layer and contacts extending through the dielectric layer to connect to conductive regions. A contact barrier layer is formed between the conductive regions and the contacts by electroless plating the conductive regions after openings have been formed through the dielectric layer for the contact. The contact barrier layer is then treated to fill the grain boundary of the contact barrier layer, thereby improving the contact resistance. In another embodiment, the contact barrier layer is formed on the conductive regions by electroless plating prior to the formation of the dielectric layer. | 02-21-2013 |
20130049141 | METAL GATE STRUCTURE AND FABRICATION METHOD THEREOF - A metal gate structure located on a substrate includes a gate dielectric layer, a metal layer and a titanium aluminum nitride metal layer. The gate dielectric layer is located on the substrate. The metal layer is located on the gate dielectric layer. The titanium aluminum nitride metal layer is located on the metal layer. | 02-28-2013 |
20130049142 | TRANSISTOR WITH REDUCED PARASITIC CAPACITANCE - Scaled transistors with reduced parasitic capacitance are formed by replacing a high-k dielectric sidewall spacer with a SiO | 02-28-2013 |
20130099330 | Controllable Undercut Etching of Tin Metal Gate Using DSP+ - A wet process utilizing a dilute acid oxidant solution, for example, a dilute sulfuric acid with hydrogen peroxide is used in the fabrication of a metal gate electrode of a semiconductor device, offering high etch selectivity and high controllability to achieve a desired profile for the metal gate electrode. In some embodiments, the dilute acid oxidant solution is a dilute sulfuric peroxide solution, comprising at least 50% or 80% by weight of water, less than 30% or 15% by weight of sulfuric acid, and less than 20% or 20% of hydrogen peroxide with optionally less than 100 ppm or 30 ppm ozone. In some embodiments, the dilute sulfuric peroxide solution further comprises less than 100 ppm of hydrofluoric acid. The dilute acid oxidant solution can be used effectively to clean the metal gate electrode or to form an undercut on a metal gate layer of the metal gate electrode. | 04-25-2013 |
20130119487 | Structure and Method for MOSFETS with High-K and Metal Gate Structure - The present disclosure provides a semiconductor structure. The semiconductor structure includes a semiconductor substrate; and a gate stack disposed on the semiconductor substrate. The gate stack includes a high k dielectric material layer, a capping layer disposed on the high k dielectric material layer, and a metal layer disposed on the capping layer. The capping layer and the high k dielectric material layer have a footing structure. | 05-16-2013 |
20130146993 | SEMICONDUCTOR STRUCTURE HAVING A POLYSILICON STRUCTURE AND METHOD OF FORMING SAME - The present application discloses a method of forming a semiconductor structure. In at least one embodiment, the method includes forming a polysilicon layer over a substrate. A mask layer is formed over the polysilicon layer. The mask layer is patterned to form a patterned mask layer. A polysilicon structure is formed by etching the polysilicon layer using the patterned mask layer as a mask. The polysilicon structure has an upper surface and a lower surface, and the etching of the polysilicon layer is arranged to cause a width of the upper surface of the polysilicon structure greater than that of the lower surface of the polysilicon structure. | 06-13-2013 |
20130161767 | SEMICONDUCTOR DEVICES HAVING POLYSILICON GATE PATTERNS AND METHODS OF FABRICATING THE SAME - A semiconductor device including a gate insulation pattern on a substrate, and a semiconductor gate pattern including an amorphous silicon pattern and a polycrystalline silicon pattern stacked on a side of the gate insulation pattern opposite to the substrate. The amorphous silicon pattern includes anti-diffusion impurities that suppress diffusion of impurity ions in the semiconductor gate pattern. | 06-27-2013 |
20130241011 | SEMICONDUCTOR DEVICE WITH GATE STACK STRUCTURE - A semiconductor device includes a first conductive layer, a first intermediate structure over the first conductive layer, a second intermediate structure over the first intermediate structure, and a second conductive layer over the second intermediate structure. The first intermediate structure includes a metal silicide layer and a nitrogen containing metal layer. The second intermediate structure includes at least a nitrogen containing metal silicide layer. | 09-19-2013 |
20130277768 | Semiconductor Structure And Method For Manufacturing The Same - The present invention provides a semiconductor structure and a method for manufacturing the same. The method comprises the following steps: providing a substrate and forming a sacrificial gate, sidewall spacers and source/drain regions located on both sides of the sacrificial gate; forming an interlayer dielectric layer that covers the device; removing the sacrificial gate to form a cavity within the sidewall spacers; forming first oxygen absorbing layers in the cavity; forming a second oxygen absorbing layer in the remaining of the space of the cavity; and performing an annealing step to make the surface of the substrate form an interfacial layer. The present invention further provides a semiconductor structure. By forming a symmetrical interfacial layer in a channel region, the present invention has reduced processing difficulty while effectively mitigating short-channel effects and preserving carrier mobility. | 10-24-2013 |
20130277769 | Non-Planar Transistors and Methods of Fabrication Thereof - Non-planar transistors and methods of fabrication thereof are described. In an embodiment, a method of forming a non-planar transistor includes forming a channel region on a first portion of a semiconductor fin, the semiconductor fin having a top surface and sidewalls. A gate electrode is formed over the channel region of the semiconductor fin, and an in-situ doped semiconductor layer is grown on the top surface and the sidewalls of the semiconductor fin on opposing sides of the gate electrode using a selective epitaxial growth process. At least a part of the doped semiconductor layer is converted to form a dopant rich region. | 10-24-2013 |
20130299922 | INTEGRATED CIRCUIT AND METHOD FOR FABRICATING THE SAME HAVING A REPLACEMENT GATE STRUCTURE - Integrated circuits and methods of fabricating integrated circuits are provided herein. In an embodiment, a method of fabricating an integrated circuit includes depositing a layer of a high-k dielectric material; depositing a layer of a work function shifter material over a portion of the high-k dielectric material to form an overlapping region; heat treating the layer of the high-k dielectric material and the layer of the work function shifter material to as to form a transformed dielectric material via thermal diffusion that is a combination of the high-k dielectric and work function shifter materials in the overlapping region; and depositing a layer of a first replacement gate fill material to obtain multiple threshold voltages. | 11-14-2013 |
20140001575 | SEMICONDUCTOR DEVICES HAVING DIFFERENT GATE OXIDE THICKNESSES | 01-02-2014 |
20140001576 | LOWERING TUNGSTEN RESISTIVITY BY REPLACING TITANIUM NITRIDE WITH TITANIUM SILICON NITRIDE | 01-02-2014 |
20140015068 | Gate Structure, Semiconductor Device and Methods for Forming the Same - The disclosure relates to a gate structure, a semiconductor device and methods for forming the same. An embodiment of the disclosure provides a method for forming a gate structure, including: providing a substrate; forming an interface layer on the substrate; forming a gate dielectric layer on the interface layer; forming a gate dielectric capping layer on the gate dielectric layer; forming an etching stop layer on the gate dielectric capping layer; forming an oxygen scavenging element layer on the etching stop layer; forming an oxygen scavenging element capping layer on the oxygen scavenging element layer; performing Post-Metallization Annealing; performing etching until the etching stop layer is exposed; forming a work function adjustment layer on the etching stop layer; and forming a gate layer on the work function adjustment layer. | 01-16-2014 |
20140054727 | METHOD OF SELECTIVELY DEGLAZING P205 - A method of forming a transistor is disclosed, in which gate-to-substrate leakage is addressed by forming and maintaining a conformal oxide layer overlying the transistor gate. Using the method disclosed for an n-type device, the conformal oxide layer can be formed as part of the source-drain doping process. Subsequent removal of residual phosphorous dopants from the surface of the oxide layer is accomplished without significant erosion of the oxide layer. The removal step uses a selective deglazing process that employs a hydrolytic reaction, and an acid-base neutralization reaction that includes an ammonium hydroxide component. | 02-27-2014 |
20140070334 | SEMICONDUCTOR DEVICE INCLUDING GRADED GATE STACK, RELATED METHOD AND DESIGN STRUCTURE - A semiconductor device is disclosed. The semiconductor device includes a substrate; and a gate structure disposed directly on the substrate, the gate structure including: a graded region with a varied material concentration profile; and a metal layer disposed on the graded region. | 03-13-2014 |
20140091402 | INTEGRATED CIRCUIT METAL GATE STRUCTURE - A semiconductor device includes a gate dielectric layer and a gate electrode formed on the gate dielectric layer. The gate electrode includes a first metal layer, a second metal layer, and a third metal layer. The first metal layer includes an oxygen-gettering composition. The second metal layer includes oxygen. The third metal layer includes an interface with a polysilicon layer. | 04-03-2014 |
20140097507 | Semiconductor Device Having a Metal Gate and Fabricating Method Thereof - The present invention provides a method of forming a semiconductor device having a metal gate. A substrate is provided and a gate dielectric and a work function metal layer are formed thereon, wherein the work function metal layer is on the gate dielectric layer. Then, a top barrier layer is formed on the work function metal layer. The step of forming the top barrier layer includes increasing a concentration of a boundary protection material in the top barrier layer. Lastly, a metal layer is formed on the top barrier layer. The present invention further provides a semiconductor device having a metal gate. | 04-10-2014 |
20140103459 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A semiconductor device includes: a channel layer made of GaN; a barrier layer formed on the channel layer, the bather layer being made of AlGaN and having a larger band gap than the channel layer; a p-type GaN layer selectively formed on the barrier layer; a gate electrode made of ITO on the p-type GaN layer; and a source electrode and a drain electrode on regions of the barrier layer laterally outward of the gate electrode. The width of the gate electrode in the gate length direction is smaller than or equal to the width of the p-type GaN layer in the gate length direction, and the difference between the width of the gate electrode in the gate length direction and the width of the p-type GaN layer in the gate length direction is less than or equal to 0.2 μm. | 04-17-2014 |
20140117467 | Metal-Oxide-Semiconductor Field-Effect Transistor with Spacer over Gate - A metal-oxide-semiconductor field-effect transistor (MOSFET) includes a substrate, a source and a drain in the substrate, a gate electrode disposed over the substrate between the source and drain. An inner spacer is disposed at least partially over the gate electrode. An outer spacer is disposed adjacent to a sidewall of the gate electrode. | 05-01-2014 |
20140159171 | METHODS OF FORMING BULK FINFET SEMICONDUCTOR DEVICES BY PERFORMING A LINER RECESSING PROCESS TO DEFINE FIN HEIGHTS AND FINFET DEVICES WITH SUCH A RECESSED LINER - One method disclosed herein includes forming a conformal liner layer in a plurality of trenches that define a fin, forming a layer of insulating material above the liner layer, exposing portions of the liner layer, removing portions of the liner layer so as to result in a generally U-shaped liner positioned at a bottom of each of the trenches, performing at least one third etching process on the layer of insulating material, wherein at least a portion of the layer of insulating material is positioned within a cavity of the U-shaped liner layer, and forming a gate structure around the fin. A FinFET device disclosed herein includes a plurality of trenches that define a fin, a local isolation that includes a generally U-shaped liner that defines, in part, a cavity and a layer of insulating material positioned within the cavity, and a gate structure positioned around the fin. | 06-12-2014 |
20140183665 | SEMICONDUCTOR STRUCTURE AND METHOD OF FABRICATING MOS DEVICE - Provided is a semiconductor structure including a gate structure, a first spacer, and a second spacer. The gate structure is formed on a substrate and includes a gate material layer, a first hard mask layer disposed on the gate material layer, and a second hard mask layer disposed on the first hard mask layer. The first spacer is disposed on sidewalls of the gate structure. The second spacer is disposed adjacent to the first spacer. The etch rate of the first hard mask layer, the etch rate of the first spacer, and the etch rate of the second spacer are substantially the same and significantly smaller than the etch rate of the second hard mask layer in a rinsing solution. | 07-03-2014 |
20140183666 | Flourine-Stabilized Interface - Methods for forming an electronic device having a fluorine-stabilized semiconductor substrate surface are disclosed. In an exemplary embodiment, a layer of a high-κ dielectric material is formed together with a layer containing fluorine on a semiconductor substrate. Subsequent annealing causes the fluorine to migrate to the surface of the semiconductor (for example, silicon, germanium, or silicon-germanium). A thin interlayer of a semiconductor oxide may also be present at the semiconductor surface. The fluorine-containing layer can comprise F-containing WSi | 07-03-2014 |
20140191340 | Transistors, Semiconductor Constructions, and Methods of Forming Semiconductor Constructions - Some embodiments include a transistor having a first electrically conductive gate portion along a first segment of a channel region and a second electrically conductive gate portion along a second segment of the channel region. The second electrically conductive gate portion is a different composition than the first electrically conductive gate portion. Some embodiments include a method of forming a semiconductor construction. First semiconductor material and metal-containing material are formed over a NAND string. An opening is formed through the metal-containing material and the first semiconductor material, and is lined with gate dielectric. Second semiconductor material is provided within the opening to form a channel region of a transistor. The transistor is a select device electrically coupled to the NAND string. | 07-10-2014 |
20140210017 | SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME - A semiconductor device and a method of forming the semiconductor device includes: forming gate electrodes on a semiconductor substrate and forming spacers on both side surfaces of the gate electrodes; forming capping patterns on the gate electrodes; and forming a metal contact between the gate electrodes. Each of the capping patterns is formed to have a width greater than a width of each of the gate electrodes. | 07-31-2014 |
20140217520 | AIR-SPACER MOS TRANSISTOR - A MOS transistor including, above a gate insulator, a conductive gate stack having a height, a length, and a width, this stack having a lower portion close to the gate insulator and an upper portion, wherein the stack has a first length in its lower portion, and a second length shorter than the first length in its upper portion. | 08-07-2014 |
20140239420 | SILICON NITRIDE GATE ENCAPSULATION BY IMPLANTATION - A method of forming a FinFET structure which includes forming fins on a semiconductor substrate; forming a gate wrapping around at least one of the fins, the gate having a first surface and an opposing second surface facing the fins; depositing a hard mask on a top of the gate; angle implanting nitrogen into the first and second surfaces of the gate so as to form a nitrogen-containing layer in the gate that is below and in direct contact with the hard mask on top of the gate; forming spacers on the gate and in contact with the nitrogen-containing layer; and epitaxially depositing silicon on the at least one fin so as to form a raised source/drain. Also disclosed is a FinFET structure. | 08-28-2014 |
20140252504 | Method for Fabricating a Semiconductor Device - A method for fabricating a semiconductor device includes receiving a silicon substrate having an isolation feature disposed on the substrate and a well adjacent the isolation feature, wherein the well includes a first dopant. The method also includes etching a recess to remove a portion of the well and epitaxially growing a silicon layer (EPI layer) in the recess to form a channel, wherein the channel includes a second dopant. The method also includes forming a barrier layer between the well and the EPI layer, the barrier layer including at least one of either silicon carbon or silicon oxide. The barrier layer can be formed either before or after the channel. The method further includes forming a gate electrode disposed over the channel and forming a source and drain in the well. | 09-11-2014 |
20140264640 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - The invention provides a semiconductor device, including: a substrate; a U-shaped gate dielectric layer formed on the substrate; and a dual work function metal gate layer on the inner surface of U-shaped gate dielectric layer, wherein the dual work function metal gate layer includes a first conductive type metal layer and a second conductive type metal layer. | 09-18-2014 |
20140264641 | SEMICONDUCTOR DEVICE COMPRISING CONTACT STRUCTURES WITH PROTECTION LAYERS FORMED ON SIDEWALLS OF CONTACT ETCH STOP LAYERS - When forming semiconductor devices with contact plugs comprising protection layers formed on sidewalls of etch stop layers to reduce the risk of shorts, the protection layers may be formed by performing a sputter process to remove material from a contact region and redeposit the removed material on the sidewalls of the etch stop layers. | 09-18-2014 |
20140284728 | Metal Silicide Thin Film, Ultra-Shallow Junctions, Semiconductor Device and Method of Making - A metal silicide thin film and ultra-shallow junctions and methods of making are disclosed. In the present disclosure, by using a metal and semiconductor dopant mixture as a target, a mixture film is formed on a semiconductor substrate using a physical vapor deposition (PVD) process. The mixture film is removed afterwards by wet etching, which is followed by annealing to form metal silicide thin film and ultra-shallow junctions. Because the metal and semiconductor dopant mixture is used as a target to deposit the mixture film, and the mixture film is removed by wet etching before annealing, self-limiting, ultra-thin, and uniform metal silicide film and ultra-shallow junctions are formed concurrently in semiconductor field-effect transistor fabrication processes, which are suitable for field-effect transistors at the 14 nm, 11 nm, or even further technology node. | 09-25-2014 |
20140346617 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A semiconductor device includes an interlayer insulating film on a substrate, the interlayer insulating film including first and second trenches, a gate insulating film in the first and second trenches, a first conductivity type work function control film on the gate insulating film in the first trench, a second conductivity type work function control film on the gate insulating film in the second trench, a first gate metal on the first conductivity type work function control film, the first gate metal filling the first trench, a second gate metal on the gate insulating film in the second trench, and a carrier mobility improving film on the second conductivity type work function control film, the carrier mobility improving film filling the second trench. | 11-27-2014 |
20140361385 | METHOD OF FORMING A SEMICONDUCTOR DEVICE STRUCTURE EMPLOYING FLUORINE DOPING AND ACCORDING SEMICONDUCTOR DEVICE STRUCTURE - Methods of forming a semiconductor device structure at advanced technology nodes and respective semiconductor device structures are provided at advanced technology nodes, i.e., smaller than 100 nm. In some illustrative embodiments, a fluorine implantation process for implanting fluorine at least into a polysilicon layer formed over a dielectric layer structure is performed prior to patterning the gate dielectric layer structure and the polysilicon layer for forming a gate structure and implanting source and drain regions at opposing sides of the gate structure. | 12-11-2014 |
20140361386 | SEMICONDUCTOR DEVICE - Provided is a semiconductor device including a substrate, a gate structure, a second dielectric layer and a source/drain region. A first dielectric layer is disposed on the substrate, and the first dielectric layer has a trench therein. The gate structure is disposed on the substrate in the trench and includes a work function metal layer and a metal layer. The work function metal layer is disposed in the trench, and includes a TiAl | 12-11-2014 |
20140367803 | FINFET GATE WITH INSULATED VIAS AND METHOD OF MAKING SAME - An intermediate semiconductor structure of a FinFET device in fabrication includes a substrate, a plurality of fin structures coupled to the substrate and a dummy gate disposed perpendicularly over the fin structures. A portion of the dummy gate is removed between the fin structures to create one or more vias and the one or more vias are filled with a dielectric. The dummy gate is then replaced with a metal gate formed around the dielectric-filled vias. | 12-18-2014 |
20140367804 | TRANSISTOR GATE AND PROCESS FOR MAKING TRANSISTOR GATE - A transistor gate is formed of a stack of layers including a polysilicon layer and a tungsten layer separated by a barrier layer. A titanium layer reduces interface resistance. A tungsten liner reduces sheet resistance. The tungsten liner, a tungsten nitride barrier layer, and the tungsten layer may be formed sequentially in the same chamber. | 12-18-2014 |
20140374844 | METHOD FOR FORMING METAL SEMICONDUCTOR ALLOYS IN CONTACT HOLES AND TRENCHES - A semiconductor device is provided that includes a gate structure on a channel region of a substrate. A source region and a drain region are present on opposing sides of the channel region. A first metal semiconductor alloy is present on an upper surface of at least one of the source and drain regions. The first metal semiconductor alloy extends to a sidewall of the gate structure. A dielectric layer is present over the gate structure and the first metal semiconductor alloy. An opening is present through the dielectric layer to a portion of the first metal semiconductor alloy that is separated from the gate structure. A second metal semiconductor alloy is present in the opening, is in direct contact with the first metal semiconductor alloy, and has an upper surface that is vertically offset and is located above the upper surface of the first metal semiconductor alloy. | 12-25-2014 |
20150021715 | Low Temperature Salicide for Replacement Gate Nanowires - Techniques for integrating low temperature salicide formation in a replacement gate device process flow are provided. In one aspect, a method of fabricating a FET device is provided that includes the following steps. A dummy gate(s) is formed over an active area of a wafer. A gap filler material is deposited around the dummy gate. The dummy gate is removed selective to the gap filler material, forming a trench in the gap filler material. A replacement gate is formed in the trench in the gap filler material. The replacement gate is recessed below a surface of the gap filler material. A gate cap is formed in the recess above the replacement gate. The gap filler material is etched back to expose at least a portion of the source and drain regions of the device. A salicide is formed on source and drain regions of the device. | 01-22-2015 |
20150028430 | Semiconductor Devices and Methods of Manufacturing the Same - Semiconductor devices and methods of manufacturing the same are disclosed. The semiconductor device a gate dielectric pattern on a substrate and a gate electrode on the gate dielectric pattern opposite the substrate. The gate electrode includes a first conductive pattern disposed on the gate dielectric pattern and including aluminum, and a second conductive pattern disposed between the first conductive pattern and the gate dielectric pattern. The second conductive pattern has an aluminum concentration that is higher than an aluminum concentration of the first conductive pattern. The second conductive pattern may be thicker than the first conductive pattern. | 01-29-2015 |
20150028431 | MOL INSITU PT REWORK SEQUENCE - The amount of Pt residues remaining after forming Pt-containing NiSi is reduced by performing an O | 01-29-2015 |
20150041926 | TUNGSTEN GATES FOR NON-PLANAR TRANSISTORS - The present description relates to the field of fabricating microelectronic devices having non-planar transistors. Embodiments of the present description relate to the formation of gates within non-planar NMOS transistors, wherein an NMOS work-function material, such as a composition of aluminum, titanium, and carbon, may be used in conjunction with a titanium-containing gate fill barrier to facilitate the use of a tungsten-containing conductive material in the formation of a gate electrode of the non-planar NMOS transistor gate. | 02-12-2015 |
20150061042 | METAL GATE STRUCTURE AND METHOD OF FABRICATING THE SAME - A metal gate structure is provided. The metal gate structure includes a semiconductor substrate, a gate dielectric layer, a multi-layered P-type work function layer and a conductive metal layer. The gate dielectric layer is disposed on the semiconductor substrate. The multi-layered P-type work function layer is disposed on the gate dielectric layer, and the multi-layered P-type work function layer includes at least a crystalline P-type work function layer and at least an amorphous P-type work function layer. Furthermore, the conductive metal layer is disposed on the multi-layered P-type work function layer. | 03-05-2015 |
20150069536 | SEMICONDUCTOR ELEMENT AND METHOD FOR PRODUCING THE SAME - A semiconductor element and a method for producing the same are provided. A semiconductor element includes an active region comprising trenches, a termination region outside the active region, a transient region disposed between the active region and the termination region, the transient region including an inside trench, in which a center poly electrode is disposed inside at least one of the trenches of the active region, at least two gate poly electrodes are disposed adjacent to an upper portion of the center poly electrode, a p-body region is disposed between upper portions of the trenches, and a source region is disposed at a side of the gate poly electrodes. | 03-12-2015 |
20150076624 | INTEGRATED CIRCUITS HAVING SMOOTH METAL GATES AND METHODS FOR FABRICATING SAME - Integrated circuits with smooth metal gates and methods for fabricating integrated circuits with smooth metal gates are provided. In an embodiment, a method for fabricating an integrated circuit includes providing a partially fabricated integrated circuit including a dielectric layer formed with a trench bound by a trench surface. The method deposits metal in the trench and forms an overburden portion of metal overlying the dielectric layer. The method includes selectively etching the metal with a chemical etchant and removing the overburden portion of metal. | 03-19-2015 |
20150076625 | SEMICONDUCTOR DEVICE - A semiconductor device according to an embodiment includes a gate wire including a laminated film in which a polysilicon film, a barrier conductive film, and a metal film are laminated in this order; a first contact plug/upper layer wire arranged above the source or the drain; a second upper layer wire arranged above an element isolation region; a second contact plug arranged apart from the second upper layer wire and connecting the metal film and the polysilicon film above a channel region; and a third contact plug formed apart from the polysilicon film in the element isolation region and connecting the second upper layer wire and the metal film. The second contact plug includes a barrier metal in contact with the polysilicon film and the barrier conductive film is made of WN, TaN, or Ta and the barrier metal is made of Ti or TiN. | 03-19-2015 |
20150091106 | METHOD FOR MAKING AN INTEGRATED CIRCUIT - A method includes making a gate stack on the surface of an active zone, including depositing a first dielectric layer; depositing a gate conductive layer; depositing a first metal layer; depositing a second metal layer; depositing a second dielectric layer; partially etching the gate stack for the formation of a gate zone on the active zone; making insulating spacers on either side of the gate zone on the active zone; making source and drain electrodes zones; making silicidation zones on the surface of the source and drain zones; etching, in the gate zone on the active zone, the second dielectric layer and the second metal layer with stopping on the first metal layer, so as to form a cavity between the insulating spacers; making a protective plug at the surface of the first metal layer of the gate zone on the active zone, where the protective plug fills the cavity. | 04-02-2015 |
20150123216 | COMMON FILL OF GATE AND SOURCE AND DRAIN CONTACTS - A semiconductor structure includes a source region, a drain region, a channel region and a gate region over a bulk silicon substrate. The gate region further includes a dielectric layer and one or more work function layers disposed over the dielectric layer. A first filler material, such as a flowable oxide is provided over the source region and the drain region. A second filler material, such as an organic material, is provided within the gate region. The first filler material and the second filler material are selectively removed to create, source, drain and gate openings. The gate, source and drain openings are filled simultaneously with a metal, such as tungsten, to create a metal gate structure, source contact and drain contact. | 05-07-2015 |
20150129990 | SEMICONDUCTOR DEVICE HAVING ELEVATED STRUCTURE - A semiconductor device includes a gate stack overlying a substrate. The semiconductor device further includes a spacer on sidewalls of the gate stack, where a top surface of the spacer is above a top surface of the gate stack. Additionally, the semiconductor device includes a protection layer overlying the gate stack and filling at least a portion of a space surrounded by the spacer above the top surface of the gate stack. Furthermore, the semiconductor device includes a contact hole over the spacer, where the contact hole extends over the gate stack, and where a sidewall of the contact hole has a step-wise shape. | 05-14-2015 |
20150137273 | METHOD AND DEVICE FOR SELF-ALIGNED CONTACT ON A NON-RECESSED METAL GATE - A methodology for forming a self-aligned contact (SAC) that exhibits reduced likelihood of a contact-to-gate short circuit failure and the resulting device are disclosed. Embodiments may include forming a replacement metal gate, with spacers at opposite sides thereof, on a substrate, forming a recess in an upper surface of the spacers along outer edges of the replacement metal gate, and forming an aluminum nitride (AlN) cap over the metal gate and in the recess. | 05-21-2015 |
20150340461 | METAL GATE STRUCTURE AND METHOD OF FORMATION - Embodiments of the present invention provide a metal gate structure and method of formation. In the replacement metal gate (RMG) process flow, the gate cut process is performed after the metal gate is formed. This allows for a reduced margin between the end of the gate and an adjacent fin. It enables a thinner sacrificial layer on top of the dummy gate, since the gate cut step is deferred. The thinner sacrificial layer improves device quality by reducing the adverse effect of shadowing during implantation. Furthermore, in this process flow, the work function metal layer is terminated along the semiconductor substrate by a capping layer, which reduces undesirable shifts in threshold voltage that occurred in prior methods and structures. | 11-26-2015 |
20150364543 | SILICON NANOWIRE FORMATION IN REPLACEMENT METAL GATE PROCESS - Techniques for a semiconductor device are provided. Techniques are directed to forming a semiconductor device by: forming a fin structure in a substrate, forming a protective layer over an upper portion of the fin structure, the protective layer having an etch selectivity with respect to a material of the fin structure, and performing an undercut etch so as to remove a lower portion of the fin structure below the protective layer, thereby defining a nanowire structure from the fin structure | 12-17-2015 |
20160005867 | SILICIDE PROTECTION DURING CONTACT METALLIZATION AND RESULTING SEMICONDUCTOR STRUCTURES - A semiconductor transistor has a structure including a semiconductor substrate, a source region, a drain region and a channel region in between the source region and the drain region. A metal gate, having a top conductive portion of tungsten is provided above the channel region. A first silicon nitride protective layer over the source region and the drain region and a second silicon nitride protective layer over the gate region are provided. The first silicon nitride protective layer and the second silicon nitride protective layer are configured to allow punch-through of the first silicon nitride protective layer while preventing etching through the second silicon nitride protective layer. Source and drain silicide is protected by avoiding fully etching a gate opening unless either the etching used would not harm the silicide, or the silicide and source and drain contacts are created prior to fully etching an opening to the gate for a gate contact. | 01-07-2016 |
20160020104 | SEMICONDUCTOR STRUCTURE INCLUDING SILICON AND OXYGEN-CONTAINING METAL LAYER AND PROCESS THEREOF - A metal gate process for polishing and oxidizing includes the following steps. A first dielectric layer having a trench is formed on a substrate. A barrier layer and a metal layer are formed sequentially to cover the trench and the first dielectric layer. A first chemical mechanical polishing process including a slurry of H | 01-21-2016 |
20160087075 | TRANSISTOR DEVICE AND FABRICATION METHOD - The present disclosure provides a transistor device and fabrication method thereof. A dummy gate is formed on a substrate. An interlayer dielectric layer is formed on the substrate and sidewall surfaces of the dummy gate. The interlayer dielectric layer has a top surface coplanar with a top surface of the dummy gate. A mask layer is formed on the top surface of the interlayer dielectric layer. The mask layer is used as an etch mask to remove the dummy gate to form a trench in the interlayer dielectric layer to provide a trench footing on sidewall surfaces of the trench and near a trench bottom. The trench footing is then removed by applying a dry etching process. A gate electrode is then formed in the trench to form a transistor with improved electrical performance. | 03-24-2016 |
20160093497 | SALICIDE FORMATION USING A CAP LAYER - A method of forming a semiconductor device includes forming a gate stack over a first portion of a source and a first portion of a drain. The method includes depositing a first cap layer comprising silicon over a second portion of the source and depositing a second cap layer comprising silicon over a second portion of the drain. The method includes depositing a metal layer over the gate stack, the first cap layer and the second cap layer. The method includes annealing the semiconductor device until all of the silicon in the first and second cap layers reacts with metal from the metal layer, wherein the annealing causes metal from the metal layer to react with silicon in the first cap layer, the second cap layer, the source, and the drain. Annealing the semiconductor device includes forming a salicide layer having a germanium concentration less than 3% by weight. | 03-31-2016 |
20160099332 | PARTIAL SACRIFICIAL DUMMY GATE WITH CMOS DEVICE WITH HIGH-K METAL GATE - A gate structure in a semiconductor device includes: a gate stack formed on a substrate with three sections, a bottom portion, a top portion, and a sacrificial cap layer over the top portion; gate spacers, source and drain regions, a nitride encapsulation over top and sidewalls of the gate stack after removal of the sacrificial cap layer, an organic planarizing layer over the nitride encapsulation, planarizing the encapsulation, and silicidation performed over the source and drain regions and the bottom portion after removal of the nitride encapsulation, the organic planarizing layer, and the top portion of the gate stack. | 04-07-2016 |
20160111514 | ULTRA-LOW RESISTANCE GATE STRUCTURE FOR NON-PLANAR DEVICE VIA MINIMIZED WORK FUNCTION MATERIAL - A non-planar semiconductor structure includes an ultra-low resistance gate structure. The non-planar structure includes a semiconductor substrate and raised semiconductor structures coupled to the substrate, a lower portion of the raised structures surrounded by a layer of isolation material. The structure further includes gate structures surrounding an upper portion of the raised structures, the gate structures including a conductive material and a layer of work function material present only in a limited area surrounding each raised structure. The limited area of work function material is achieved in fabrication by including dummy gate structures covering a layer of selectively removable material above the raised structures and a layer of hard mask material above the selectively removable layer, removing the selectively removable layer with the dummy gate structures, filling the resulting gate openings with work function material and then removing most of it, using the layer of hard mask material to delimit the limited area of work function material. | 04-21-2016 |
20160118469 | INTEGRATED CIRCUIT DEVICES WITH COUNTER-DOPED CONDUCTIVE GATES - Integrated circuit devices with counter-doped conductive gates. The devices have a semiconductor substrate that has a substrate surface. The devices also have a first well of a first conductivity type, a source of a second conductivity type, and a drain of the second conductivity type. A channel extends between the source and the drain. A conductive gate extends across the channel. The conductive gate includes a first gate region and a second gate region of the second conductivity type and a third gate region of the first conductivity type. The third gate region extends between the first and second gate regions. The devices further include a gate dielectric that extends between the conductive gate and the substrate and also include a silicide region in electrical communication with the first, second, and third gate regions. The methods include methods of manufacturing the devices. | 04-28-2016 |
20160163603 | PFET GATE STACK MATERIALS HAVING IMPROVED THRESHOLD VOLTAGE, MOBILITY AND NBTI PERFORMANCE - A method of forming a transistor device includes forming an interfacial layer and a dielectric layer over a substrate; and forming a p-type field effect transistor (PFET) workfunction metal layer over the dielectric layer, the workfunction metal layer comprising a lower titanium nitride (TiN) first layer and a second layer including one of titanium-aluminum-carbide (TiAlC) and tantalum-aluminum-carbide (TaAlC) formed on the lower TiN first layer. | 06-09-2016 |
20160190275 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - It is made possible to provide a method for manufacturing a semiconductor device that has a high-quality insulating film in which defects are not easily formed, and experiences less leakage current. A method for manufacturing a semiconductor device, includes: forming an amorphous silicon layer on an insulating layer; introducing oxygen into the amorphous silicon layer; and forming a silicon oxynitride layer by nitriding the amorphous silicon layer having oxygen introduced thereinto. | 06-30-2016 |
20160196976 | Method for tuning the effective work function of a metal | 07-07-2016 |