Entries |
Document | Title | Date |
20080197425 | Semiconductor device - A semiconductor device has a trench isolation structure and a high voltage circuit section including at least one well region, a MOS transistor, and an interconnect for electrically connecting elements. An electrode for preventing inversion layer formation is formed in a region above the trench isolation region provided near an end portion of the well region and below the interconnect for preventing parasitic formation of an inversion layer on a surface of the semiconductor substrate due to the potential of the interconnect, and fixed at the same potential as that of the semiconductor substrate therebelow. Further, a guard ring region formed of a heavily doped impurity region of the same conductivity type as the semiconductor substrate is provided below the electrode for preventing inversion layer formation and is fixed at the same potential as that of the semiconductor substrate to capture carriers to prevent latch-up. | 08-21-2008 |
20080203496 | SEMICONDUCTOR DEVICE - A gate electrode | 08-28-2008 |
20080203497 | Semiconductor Devices Including Assymetric Source and Drain Regions Having a Same Width and Related Methods - A semiconductor device may include an active region of a semiconductor substrate and first and second impurity regions in the active region. The active region may have a first conductivity type, the first and second impurity regions may have a second conductivity type opposite the first conductivity type, and the first and second impurity regions are spaced apart to define a channel region therebetween. A first source/drain region may be provided in the first impurity region, a second source/drain region may be provide in the second impurity region, the first and second source/drain regions may have the second conductivity type, and impurity concentrations of the first and second source/drain regions may be greater than impurity concentrations of the first and second impurity regions. Moreover, the first and second source/drain regions may have a same width in a direction perpendicular with respect to a direction between the first and second source/drain regions, and a distance between the first source/drain region and the channel region may be less than a distance between the second source/drain region and the channel region. In addition, a control gate may be provided on the channel region. Related methods are also discussed. | 08-28-2008 |
20080237746 | Gated diode with non-planar source region - A gated-diode semiconductor device or similar component and a method of fabricating the device. The device features a gate structure disposed on a substrate over a channel and adjacent a source and a drain. The top of the source or drain region, or both, are formed so as to be at a higher elevation, in whole or in part, than the bottom of the gate structure. This configuration may be achieved by overlaying the gate structure and substrate with a profile layer that guides a subsequent etch process to create a sloped profile. The source and drain, if both are present, may be symmetrical or asymmetrical. This configuration significantly reduces dopant encroachment and, as a consequence, reduces junction leakage. | 10-02-2008 |
20080237747 | SEMICONDUCTOR DEVICE - A semiconductor device including: a semiconductor layer; a gate insulating layer; a gate electrode; a channel region; a source region and a drain region; a guard ring region; an offset insulating layer; a first interlayer dielectric; a first shield layer formed above the first interlayer dielectric and the guard ring region and electrically connected to the guard ring region; a second interlayer dielectric; and a second shield layer formed above the second interlayer dielectric, wherein the first shield layer is provided outside of both ends of the gate electrode in a channel width direction when viewed from the top side; and wherein the second shield layer is provided in at least part of a first region and/or at least part of a second region, the first region being a region between one edge of the gate electrode and an edge of the first shield layer opposite to the edge of the gate electrode in the channel width direction when viewed from the top side, and the second region being a region between the other edge of the gate electrode and an edge of the first shield layer opposite to the other edge of the gate electrode in the channel width direction when viewed from the top side. | 10-02-2008 |
20080251863 | HIGH-VOLTAGE RADIO-FREQUENCY POWER DEVICE - A high-voltage RF power device includes a plurality of serially connected transistors. Each transistor includes a gate finger disposed on a substrate, a gate dielectric layer, a drain structure disposed on one side of the gate finger, and an N+ source region on the other side of the gate finger. The drain structure includes an N+ doping region encompassed by a shallow trench isolation (STI) structure, and an N well directly underneath the STI structure and the N+ doping region. | 10-16-2008 |
20080272443 | Field effect transistor having field plate electrodes - A field effect transistor includes an active layer formed on a semiconductor substrate, source and drain electrodes formed apart from each other on the active layer, a gate electrode formed between the source and drain electrodes, a first interlayer film formed on the active layer, a first field plate (FP) electrode connected to the gate electrode and provided on the first interlayer film between the gate and drain electrodes, a second interlayer film formed on the first interlayer film, and a second FP electrode connected to the source electrode and provided on the second interlayer film between the first FP and drain electrodes. The field effect transistor is provided which exhibits a comparatively high gain factor at high frequencies. | 11-06-2008 |
20080277744 | HIGH VOLTAGE DEVICE - The invention is directed to a method for manufacturing a high voltage device. The method includes steps of providing a substrate and then forming a first doped region having a first conductive type in the substrate. At least two second doped regions having a second conductive type are formed in the substrate. The second doped regions are located adjacent to both sides of the first doped region respectively, and the first doped region is separated from the second doped regions with an isolation region. A gate structure is formed on the substrate between the second doped regions and a source/drain region having the second doped region is formed in the substrate adjacent to both sides of the gate structure. | 11-13-2008 |
20080315329 | INTEGRATED CIRCUIT WITH A SUBSURFACE DIODE - An integrated circuit includes a first and second diode connected in parallel. The first diode has a first breakdown voltage and has first P type region and first N type region adjacent to each other at the surface of the substrate of a substrate to form a lateral diode. The second diode has a second breakdown voltage less than the first breakdown voltage and has a second P type region and second N type region lateral adjacent to each other in the substrate to form a lateral diode below the surface The first and second N type regions overlap and the first and second P type region being electrically connected whereby the first and second diodes are in parallel. | 12-25-2008 |
20090008723 | SEMICONDUCTOR COMPONENT INCLUDING AN EDGE TERMINATION HAVING A TRENCH AND METHOD FOR PRODUCING - A semiconductor component includes a semiconductor body having a first side, a second side, an edge delimiting the semiconductor body in a lateral direction, an inner region and an edge region. A first semiconductor zone of a first conduction type is arranged in the inner region and in the edge region. A second semiconductor zone of a second conduction type is arranged in the inner region and adjacent to the first semiconductor zone. A trench is arranged in the edge region and has first and second sidewalls and a bottom, and extends into the semiconductor body. A doped first sidewall zone of the second conduction type is adjacent to the first sidewall of the trench. A doped second sidewall zone of the second conduction type is adjacent to the second sidewall of the trench. A doped bottom zone of the second conduction type is adjacent to the bottom of the trench. Doping concentrations of the sidewall zones are lower than a doping concentration of the bottom zone. | 01-08-2009 |
20090014815 | High voltage device and method for fabricating the same - A high voltage device includes drift regions formed in a substrate, an isolation layer formed in the substrate to isolate neighboring drift regions, wherein the isolation layer has a depth greater than that of the drift region, a gate electrode formed over the substrate, and source and drain regions formed in the drift regions on both sides of the gate electrode. | 01-15-2009 |
20090014816 | High voltage operating field effect transistor, and bias circuit therefor and high voltage circuit thereof - A high voltage operating field effect transistor has a substrate and a semiconductor channel formation region disposed in a surface of the substrate. A source region and a drain region are spaced apart from each other with the semiconductor channel formation region disposed between the source region and the drain region. A gate insulating film region is disposed on the semiconductor channel formation region. A resistive gate region is disposed on the gate insulating film region. A source side electrode is disposed on a source region side of the resistive gate region and is operative to receive a signal electric potential. A drain side electrode is disposed on a drain region side of the resistive gate region and is operative to receive a bias electric potential an absolute value of which is equal to or larger than that of a specified electric potential and which changes according to an increase or decrease in a drain electric potential. | 01-15-2009 |
20090020834 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - In a MOSFET using SiC a p-type channel is formed by epitaxial growth, so that the depletion layer produced in the p-type region right under the channel is reduced, even when the device is formed in a self-aligned manner. Thus, a high breakdown voltage is obtained. Also, since the device is formed in a self-aligned manner, the device size can be reduced so that an increased number of devices can be fabricated in a certain area and the on-state resistance can be reduced. | 01-22-2009 |
20090072326 | ULTRA HIGH VOLTAGE MOS TRANSISTOR DEVICE - An ultra high voltage MOS transistor device includes a substrate; a source region formed in the substrate; a first doping region formed in the substrate and bordering upon the source region; a first ion well encompassing the source region and the first doping region; a gate oxide layer formed on the source region and on the first ion well; a field oxide layer connected with the gate oxide layer and formed on a semiconductor region; a dielectric layer stacked on the field oxide layer; a drain region formed at one side of the field oxide layer and being spaced apart from the source region; a second ion well encompassing the drain region; and a gate disposed on the gate oxide layer and laterally extending to the field oxide layer and onto the dielectric layer. | 03-19-2009 |
20090090983 | DUAL WORK FUNCTION HIGH VOLTAGE DEVICES - A transistor has a substrate having a channel region and source and drain regions within the substrate on opposite sides of the channel region. The structure includes a gate oxide above the channel region of the substrate and a gate conductor above the gate oxide. The polysilicon gate conductor comprises a source side positioned toward the source and a drain side positioned toward the drain. The source side comprises a first concentration of conductive doping and the drain side comprises a second concentration of the conductive doping that is less than the first concentration. | 04-09-2009 |
20090090984 | Novel Method to Increase Breakdown Voltage of Semiconductor Devices - Methods of achieving high breakdown voltages in semiconductor devices by suppressing the surface flashover using high dielectric strength insulating encapsulation material are generally described. In one embodiment of the present invention, surface flashover in AlGaN/GaN heterostructure field-effect transistors (HFETs) is suppressed by using high dielectric strength insulating encapsulation material. Surface flashover in as-fabricated III-Nitride based HFETs limits the operating voltages at levels well below the breakdown voltages of GaN. | 04-09-2009 |
20090090985 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A semiconductor device includes a substrate having an active region and an isolation region, a gate pattern crossing both the active region and the isolation region of the substrate, and a protrusion having a surface higher than that of the substrate over at least an edge of the active region contacting a portion of the isolation region under the gate pattern. | 04-09-2009 |
20090096039 | HIGH-VOLTAGE DEVICE AND MANUFACTURING METHOD OF TOP LAYER IN HIGH-VOLTAGE DEVICE - A high-voltage device including a first conductive type substrate, a gate, a second conductive type well, a second conductive type source region, a second conductive type drain region, conductive layers, and a first conductive type top layer. The gate is disposed on the substrate, and the well is disposed in the substrate at one side of the gate. The source region is disposed in the substrate at the other side of the gate. The drain region is disposed in the well of the substrate. The conductive layers are disposed on the substrate between the gate and the drain region. The top layer is disposed in the well of the substrate, and the well is below the conductive layers. One portion of the top layer near the gate has a thickness greater than that of the other portion of the top layer away from the gate. | 04-16-2009 |
20090127637 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - The HVIC includes a dielectric layer and an SOI active layer stacked on a silicon substrate, a transistor formed in the surface of the SOI active layer, and a trench isolation region formed around the transistor. The dielectric layer includes a first buried oxide film formed in the surface of the silicon substrate, a shield layer formed below the first buried oxide film opposite the element area, a second buried oxide film formed around the shield layer, and a third buried oxide film formed below the shield layer and the second buried oxide film. Therefore, the potential distribution curves PC within the dielectric layer are low in density and a high withstand voltage is achieved. | 05-21-2009 |
20090134478 | SEMICONDUCTOR STRUCTURE - A semiconductor structure including a substrate, a first well, a second well, a third well, a first doped region, and a second doped region. The substrate includes a first conductive type. The first well includes a second conductive type and is formed in the substrate. The second well includes the second conductive type and is formed in the first well. The third well includes the first conductive type, is formed in the substrate, and neighbors the first well. The first doped region includes the first conductive type and is formed in the first well. The second doped region includes the first conductive type and is formed in the first well. The first well surrounds all surfaces of the first and the second doped regions. | 05-28-2009 |
20090152649 | Semiconductor Device of Multi-Finger Type - Provided is a semiconductor device of a multi-finger type. The semiconductor device comprises an active region, a guard ring, a source electrode, at least one gate electrode, and at least one drain electrode. The active region includes a source region, a drain region, and a channel region. The guard ring surrounds the active region. The source electrode is connected to the guard ring and a bulk region. The source electrode includes electrode bodies disposed on a first side of the active region and a second side of the active region opposite the first side, and fingers connecting the two electrode bodies to branch through the source region. The gate electrode can be provided in plurality as fingers on the channel region. One or more gate electrode fingers can be connected to each other through a set of vias. The drain electrode can be provided in plurality as fingers branching on the drain region. | 06-18-2009 |
20090166765 | MOS TRANSISTOR AND METHOD FOR MANUFACTURING THE TRANSISTOR - A MOS transistor and a method for manufacturing the transistor that may include forming a gate pattern on and/or over an active area of a semiconductor substrate defined as the active area and a field area, and silicide blocking films at each side of the gate pattern and partially over the uppermost surface of the gate pattern the silicide blocking films including first and second silicide blocking film portions formed spaced apart and extending in parallel to each other, and third and fourth silicide blocking film portions connected to the first and second silicide blocking film portions and formed spaced apart and extending in parallel to each other and perpendicular to the first and second silicide blocking film portions. With such a structural design, a high voltage transistor and middle voltage transistor having a reduced pitch size may be formed, thereby reducing the overall chip size. | 07-02-2009 |
20090174011 | Semiconductor device having guard ring - A semiconductor device includes an internal circuit region on a semiconductor substrate, at least one guard ring on the semiconductor substrate, the guard ring surrounding the internal circuit region, and at least one current blocking unit on the semiconductor substrate, the current blocking unit being configured to block an electric current flowing from the guard ring to the semiconductor substrate. | 07-09-2009 |
20090218638 | NAND FLASH PERIPHERAL CIRCUITRY FIELD PLATE - A high voltage device for use in periphery circuitry of a NAND flash memory device comprising a field plate. | 09-03-2009 |
20090242998 | PENETRATING IMPLANT FOR FORMING A SEMICONDUCTOR DEVICE - A semiconductor device and method to form a semiconductor device is described. The semiconductor includes a gate stack disposed on a substrate. Tip regions are disposed in the substrate on either side of the gate stack. Halo regions are disposed in the substrate adjacent the tip regions. A threshold voltage implant region is disposed in the substrate directly below the gate stack. The concentration of dopant impurity atoms of a particular conductivity type is approximately the same in both the threshold voltage implant region as in the halo regions. The method includes a dopant impurity implant technique having sufficient strength to penetrate a gate stack. | 10-01-2009 |
20090261427 | MOS P-N JUNCTION DIODE DEVICE AND METHOD FOR MANUFACTURING THE SAME - A MOS P-N junction diode device includes a substrate having a first conductivity type, a field oxide structure defining a trench structure, a gate structure formed in the trench structure and a doped region having a second conductivity type adjacent to the gate structure in the substrate. The method for manufacturing such diode device includes several ion-implanting steps. After the gate structure is formed by isotropic etching using a patterned photo-resist layer as a mask, an ion-implanting step is performed using the patterned photo-resist layer as a mask to form a deeper doped sub-region. Then, another ion-implanting step is performed using the gate structure as a mask to form a shallower doped sub-region between the gate structure and the deeper doped sub-region. The formed MOS P-N junction diode device has low forward voltage drop, low reverse leakage current, fast reverse recovery time and high reverse voltage tolerance. | 10-22-2009 |
20090261428 | MOS P-N JUNCTION SCHOTTKY DIODE DEVICE AND METHOD FOR MANUFACTURING THE SAME - A MOS P-N junction Schottky diode device includes a substrate having a first conductivity type, a field oxide structure defining a trench structure, a gate structure formed in the trench structure and a doped region having a second conductivity type adjacent to the gate structure in the substrate. An ohmic contact and a Schottky contact are formed at different sides of the gate structure. The method for manufacturing such diode device includes several ion-implanting steps to form several doped sub-regions with different implantation depths to constitute the doped regions. The formed MOS P-N junction Schottky diode device has low forward voltage drop, low reverse leakage current, fast reverse recovery time and high reverse voltage tolerance. | 10-22-2009 |
20090289312 | Semiconductor device and method of manufacturing the same - Provided is a semiconductor device including a first region, a source region, a second region, a drain region, a gate insulating layer, a field insulating layer and a gate electrode. The first region is formed in a surface area of a semiconductor substrate. The source region is formed in a surface area of the first region. The second region is formed in a surface area of the semiconductor substrate. The drain region is formed in a surface region of the second region. The gate insulating layer is formed on a front surface of the semiconductor substrate between the source region and the second region. The field insulating layer is formed in a surface area of the semiconductor substrate between the drain region and the gate insulating layer. The gate electrode covers part of the gate insulating layer and part of the field insulating layer. The field insulating layer has, in its portion overlapping the gate electrode, such a step that a portion of the field insulating layer between the step and the gate insulating layer is thinner than the rest of the field insulating layer. | 11-26-2009 |
20090321852 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A P type drift layer is formed in an N type epitaxial layer from under a drain layer to under an N type body layer under a source layer through under an element isolation insulation film. This P type drift layer is shallower immediately under the drain layer than under the element isolation insulation film, and gradually shallows from under the element isolation insulation film to the N type body layer to be in contact with the bottom of the N type body layer. Since the P type drift layer is thus diffused in a wide region, a wide current path is formed from the N type body layer to the drain layer, and the current drive ability is enhanced and the drain breakdown voltage is also increased. | 12-31-2009 |
20100078737 | High-voltage metal oxide semiconductor device and fabrication method thereof - A high-voltage metal oxide semiconductor device comprising a main body of a first conductivity type, a conductive structure, a first well of a second conductivity type, a source region of the first conductivity type, and a second well of the second conductivity type is provided. The conductive structure has a first portion and a second portion. The first portion is extended from an upper surface of the main body into the main body. The second portion is extended along the upper surface of the main body. The first well is located in the main body and below the second portion. The first well is kept away from the first portion with a predetermined distance. The source region is located in the first well. The second well is located in the main body and extends from a bottom of the first portion to a place close to a drain region. | 04-01-2010 |
20100090291 | TRANSISTOR STRUCTURE HAVING REDUCED INPUT CAPACITANCE - A semiconductor device having reduced input capacitance is disclosed. The semiconductor device includes a pedestal region having a gate overlying a sidewall of the pedestal region and gate interconnect overlying a major surface of the pedestal region. The pedestal region includes a conductive shield layer ( | 04-15-2010 |
20100187642 | SEMICONDUCTOR COMPONENT AND METHOD OF MANUFACTURE - A semiconductor component that includes a field plate and a semiconductor device and a method of manufacturing the semiconductor component. A body region is formed in a semiconductor material that has a major surface. A gate trench is formed in the epitaxial layer and a gate structure is formed on the gate trench. A source region is formed adjacent the gate trench and extends from the major surface into the body region and a field plate trench is formed that extends from the major surface of the epitaxial layer through the source and through the body region. A field plate is formed in the field plate trench, wherein the field plate is electrically isolated from the sidewalls of the field plate trench. A source-field plate-body contact is made to the source region, the field plate and the body region. A gate contact is made to the gate region. | 07-29-2010 |
20100200936 | SEMICONDUCTOR DEVICE - A semiconductor device includes: a semiconductor layer of a first conductivity type; a first semiconductor pillar region of the first conductivity type provided on a major surface of the semiconductor layer; a second semiconductor pillar region of a second conductivity type provided adjacent to the first semiconductor pillar region on the major surface of the semiconductor layer, the second semiconductor pillar region forming a periodic arrangement structure substantially parallel to the major surface of the semiconductor layer together with the first semiconductor pillar region; a first main electrode; a first semiconductor region of the second conductivity type; a second semiconductor region of the first conductivity type; a second main electrode; a control electrode; and a high-resistance semiconductor layer provided on the semiconductor layer in an edge termination section surrounding the first semiconductor pillar region and the second semiconductor pillar region. The high-resistance semiconductor layer has a lower dopant concentration than the first semiconductor pillar region. A boundary region is provided between a device central region and the edge termination section. The first semiconductor pillar region and the second semiconductor pillar region adjacent to the high-resistance semiconductor layer in the boundary region have a depth decreasing stepwise toward the edge termination section. | 08-12-2010 |
20100237441 | Gated Diode with Non-Planar Source Region - A gated-diode semiconductor device or similar component and a method of fabricating the device. The device features a gate structure disposed on a substrate over a channel and adjacent a source and a drain. The top of the source or drain region, or both, are formed so as to be at a higher elevation, in whole or in part, than the bottom of the gate structure. This configuration may be achieved by overlaying the gate structure and substrate with a profile layer that guides a subsequent etch process to create a sloped profile. The source and drain, if both are present, may be symmetrical or asymmetrical. This configuration significantly reduces dopant encroachment and, as a consequence, reduces junction leakage. | 09-23-2010 |
20100276762 | SEMICONDUCTOR DEVICE - A semiconductor device including: a semiconductor layer; a gate insulating layer; a gate electrode; a channel region; a source region and a drain region; a guard ring region; an offset insulating layer; a first interlayer dielectric; a first shield layer formed above the first interlayer dielectric and the guard ring region and electrically connected to the guard ring region; a second interlayer dielectric; and a second shield layer formed above the second interlayer dielectric, wherein the first shield layer is provided outside of both ends of the gate electrode in a channel width direction when viewed from the top side; and wherein the second shield layer is provided in at least part of a first region and/or at least part of a second region, the first region being a region between one edge of the gate electrode and an edge of the first shield layer opposite to the edge of the gate electrode in the channel width direction when viewed from the top side, and the second region being a region between the other edge of the gate electrode and an edge of the first shield layer opposite to the other edge of the gate electrode in the channel width direction when viewed from the top side. | 11-04-2010 |
20100289094 | ENHANCING DEPOSITION UNIFORMITY OF A CHANNEL SEMICONDUCTOR ALLOY BY AN IN SITU ETCH PROCESS - When forming sophisticated gate electrode structures requiring a threshold adjusting semiconductor alloy for one type of transistor, a recess is formed in the corresponding active region, thereby providing superior process uniformity during the deposition of the semiconductor material. Due to the recess, any exposed sidewall surface areas of the active region may be avoided during the selective epitaxial growth process, thereby significantly contributing to enhanced threshold stability of the resulting transistor including the high-k metal gate stack. | 11-18-2010 |
20100314695 | Self-aligned vertical group III-V transistor and method for fabricated same - In one embodiment a self-aligned vertical group III-V transistor comprises a group III-V layer having a first conductivity type formed over a group III-V drift body having a second conductivity type opposite the first conductivity type, a pinch-off region formed by dopant implantation of the group III-V layer. The pinch-off region is doped so as to have the second conductivity type, and extends through the group III-V layer to the group III-V drift body. The self-aligned vertical group III-V transistor also comprises a pinch-off insulation body formed over the pinch-off region, the pinch-off region and the pinch-off insulation body being self-aligned. In one embodiment, the present invention may take the form of a self-aligned vertical N-channel field-effect transistor (FET) in gallium nitride GaN. | 12-16-2010 |
20110018071 | HIGH-VOLTAGE METAL OXIDE SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF - A high-voltage metal oxide semiconductor device comprising a main body of a first conductivity type, a conductive structure, a first well of a second conductivity type, a source region of the first conductivity type, and a second well of the second conductivity type is provided. The conductive structure has a first portion and a second portion. The first portion is extended from an upper surface of the main body into the main body. The second portion is extended along the upper surface of the main body. The first well is located in the main body and below the second portion. The first well is kept away from the first portion with a predetermined distance. The source region is located in the first well. The second well is located in the main body and extends from a bottom of the first portion to a place close to a drain region. | 01-27-2011 |
20110115033 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device which solves the following problem of a super junction structure: due to a relatively high concentration in the body cell region (active region), in peripheral areas (peripheral regions or junction end regions), it is difficult to achieve a breakdown voltage equivalent to or higher than in the cell region through a conventional junction edge terminal structure or resurf structure. The semiconductor device includes a power MOSFET having a super junction structure formed in the cell region by a trench fill technique. Also, super junction structures having orientations parallel to the sides of the cell region are provided in a drift region around the cell region. | 05-19-2011 |
20110169103 | DEVICES, COMPONENTS AND METHODS COMBINING TRENCH FIELD PLATES WITH IMMOBILE ELECTROSTATIC CHARGE - N-channel power semiconductor devices in which an insulated field plate is coupled to the drift region, and immobile electrostatic charge is also present at the interface between the drift region and the insulation around the field plate. The electrostatic charge permits OFF-state voltage drop to occur near the source region, in addition to the voltage drop which occurs near the drain region (due to the presence of the field plate). | 07-14-2011 |
20110215424 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device includes a semiconductor operating layer that is made of group-III nitride-based compound semiconductor and a first electrode and a second electrode formed on the semiconductor operating layer. Sheet carrier density of the semiconductor operating layer is no less than 1×10 | 09-08-2011 |
20110221011 | SEMICONDUCTOR COMPONENT AND METHOD FOR PRODUCING THE SAME - The invention relates to a transistor, in which the electric field is reduced in critical areas using field plates, thus permitting the electric field to be more uniformly distributed along the component. The aim of the invention is to provide a transistor and a production method therefor, wherein the electric field in the active region is smoothed (and field peaks are reduced), thus allowing the component to be made more simply and cost-effectively. The semiconductor component according to the invention has a substrate ( | 09-15-2011 |
20110291203 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device according to an embodiment of the present invention includes a active region, a drain electrode, a source electrode, a gate electrode, a passivation layer, a source field plate, and a electrical connection. The active region is formed on a semiconductor substrate. The drain electrode, the source electrode, and the gate electrode are formed on a surface of the active region to be separated from each other. The passivation layer is formed on a surface of the active region between the drain electrode and the source electrode to cover the gate electrode. The source field plate is formed at least at a position including an upper portion of the drain-side end portion of the gate electrode on a surface of the passivation layer. The electrical connection is formed on the passivation layer to connect the source field plate and the source electrode. The electrical connection has a width of the electrical connection smaller than electrode widths of the source field plate and the source electrode. | 12-01-2011 |
20120139060 | SEMICONDUCTOR DEVICE HAVING GUARD RING - A semiconductor device includes an internal circuit region on a semiconductor substrate, at least one guard ring on the semiconductor substrate, the guard ring surrounding the internal circuit region, and at least one current blocking unit on the semiconductor substrate, the current blocking unit being configured to block an electric current flowing from the guard ring to the semiconductor substrate. | 06-07-2012 |
20120181629 | HV Interconnection Solution Using Floating Conductors - A device includes a first and a second heavily doped region in a semiconductor substrate. An insulation region has at least a portion in the semiconductor substrate, wherein the insulation region is adjacent to the first and the second heavily doped regions. A gate dielectric is formed over the semiconductor substrate and having a portion over a portion of the insulation region. A gate is formed over the gate dielectric. A floating conductor is over and vertically overlapping the insulation region. A metal line includes a portion over and vertically overlapping the floating conductor, wherein the metal line is coupled to, and carries a voltage of, the second heavily doped region. | 07-19-2012 |
20120235250 | SEMICONDUCTOR DEVICE AND A METHOD OF MANUFACTURING THE SAME - In a high frequency amplifying MOSFET having a drain offset region, the size is reduced and the on-resistance is decreased by providing conductor plugs | 09-20-2012 |
20120248549 | Method for Increasing Reverse Breakdown Voltage Between P-Well and N-Well and related Semiconductor Silicon Devices - A method for improving the reverse breakdown voltage between P-well and N-well and related semiconductor silicon devices are described herein. In one aspect, a semiconductor silicon device comprises a substrate; a P-well in said substrate; an N-well in said substrate; wherein said N-well and said P-well are separated by said substrate. In another aspect, a method for increasing the reverse breakdown voltage from P-well to N-well comprises: providing a substrate; forming an N-well and a P-well in said substrate and separating said N-well and said P-well by said substrate. | 10-04-2012 |
20130032895 | HIGH-VOLTAGE TRANSISTOR DEVICE AND ASSOCIATED METHOD FOR MANUFACTURING - A high-voltage transistor device comprises a spiral resistive field plate over a first well region between a drain region and a source region of the high-voltage transistor device, wherein the spiral resistive field plate is separated from the first well region by a first isolation layer, and is coupled between the drain region and the source region. The high-voltage transistor device further comprises a plurality of first field plates over the spiral resistive field plate with each first field plate covering one or more segments of the spiral resistive field plate, wherein the plurality of first field plates are isolated from the spiral resistive field plate by a first dielectric layer, and wherein the plurality of first field plates are isolated from each other, and a starting first field plate is connected to the source region. | 02-07-2013 |
20130032896 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device includes a p-type semiconductor layer, n-type column regions formed of columnar thermal donors exhibiting an n-type property, a p-type column region interposed between the n-type column regions, the n-type column regions configured to form a super-junction structure in cooperation with the p-type column region, a channel region formed in the semiconductor layer, a source region formed in the channel region, a gate insulator film formed on the semiconductor layer, and a gate electrode formed on the gate insulator film and opposite to the channel region across the gate insulator film. | 02-07-2013 |
20130069173 | POWER SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF - Disclosed are a power semiconductor device and a method of fabricating the same which can increase a breakdown voltage of the device through a field plate formed between a gate electrode and a drain electrode and achieve an easier manufacturing process at the same time. The power semiconductor device according to an exemplary embodiment of the present disclosure includes a source electrode and a drain electrode formed on a substrate; a dielectric layer formed between the source electrode and the drain electrode to have a lower height than heights of the two electrodes and including an etched part exposing the substrate; a gate electrode formed on the etched part; a field plate formed on the dielectric layer between the gate electrode and the drain electrode; | 03-21-2013 |
20130082336 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - An AlGaN/GaN HEMT includes a compound semiconductor multilayer structure, an insertion metal layer in contact with a surface of the compound semiconductor multilayer structure, a gate insulating film formed on the insertion metal layer, and a gate electrode formed above the insertion metal layer with the gate insulating film between the gate electrode and the insertion metal layer. | 04-04-2013 |
20130134526 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - A semiconductor device and a method of fabricating the semiconductor device is provided. In the method, a semiconductor substrate defining a device region and an outer region at a periphery of the device region is provided, an align trench is formed in the outer region, a dummy trench is formed in the device region, an epi layer is formed over a top surface of the semiconductor substrate and within the dummy trench, a current path changing part is formed over the epi layer, and a gate electrode is formed over the current path changing part. When the epi layer is formed, a current path changing trench corresponding to the dummy trench is formed over the epi layer, and the current path changing part is formed within the current path changing trench. | 05-30-2013 |
20130154030 | Semiconductor Device with Self-Charging Field Electrodes and Compensation Regions - A semiconductor device includes a drift region of a first doping type, a junction between the drift region and a device region, a compensation region of a second doping type, and at least one field electrode structure arranged between the drift region and the compensation region. The at least one field electrode includes a field electrode and a field electrode dielectric adjoining the field electrode. The field electrode dielectric is arranged between the field electrode and the drift region and between the field electrode and the compensation. The field electrode dielectric includes a first opening through which the field electrode is coupled to drift region and a second opening through which the field electrode is coupled to the compensation region. | 06-20-2013 |
20130187240 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device including a semiconductor layer of a first conductivity type in a cell region, a first base layer of a second conductivity type on the semiconductor layer in the cell region; a second base layer of the second conductivity type on the semiconductor layer in an intermediate region; a conductive region of a first conductivity type in the first base layer; a gate electrode on a channel region placed between the conductive region and the semiconductor layer; a first electrode connected to the first and second base layers; a second electrode connected to the semiconductor layer; and a gate pad on the semiconductor layer via an insulating film in a pad region and connected to the gate electrode, an impurity concentration gradation in the gate pad side of the second base layer has a gentler VLD structure than an impurity concentration gradation in the first base layer. | 07-25-2013 |
20130200471 | ALIGNMENT TOLERANT SEMICONDUCTOR CONTACT AND METHOD - An alignment tolerant electrical contact is formed by providing a substrate on which is a first electrically conductive region (e.g., a MOSFET gate) having an upper surface, the first electrically conductive region being laterally bounded by a first dielectric region, applying a mask having an opening extending partly over a contact region (e.g., for the MOSFET source or drain) on the substrate and over a part of the upper surface, forming a passage through the first dielectric region extending to the contact region and the part of the upper surface, thereby exposing the contact region and the part of the upper surface, converting the part of the upper surface to a second dielectric region and filling the opening with a conductor making electrical contact with the contact region but electrically insulated from the electrically conductive region by the second dielectric region. | 08-08-2013 |
20130277763 | POWER SEMICONDUCTOR DEVICE - In general, according to one embodiment, a power semiconductor device includes a first pillar region, a second pillar region, and an epitaxial layer of a first conductivity type on a first semiconductor layer. The first pillar region is composed of a plurality of first pillar layers of a second conductivity type and a plurality of second pillar layers of the first conductivity type alternately arranged along a first direction. The second pillar region is adjacent to the first pillar region along the first direction and includes a third pillar layer of the second conductivity type, a fourth pillar layer of the first conductivity type, and a fifth pillar layer of the second conductivity type in this order along the first direction. A plurality of second base layers of the second conductivity type electrically connected, respectively, onto the third pillar layer and the fifth pillar layer and spaced from each other. | 10-24-2013 |
20130320462 | ADAPTIVE CHARGE BALANCED EDGE TERMINATION - In one embodiment, a semiconductor device can include a substrate including a first type dopant. The semiconductor device can also include an epitaxial layer located above the substrate and including a lower concentration of the first type dopant than the substrate. In addition, the semiconductor device can include a junction extension region located within the epitaxial layer and including a second type dopant. Furthermore, the semiconductor device can include a set of field rings in physical contact with the junction extension region and including a higher concentration of the second type dopant than the junction extension region. Moreover, the semiconductor device can include an edge termination structure in physical contact with the set of field rings. | 12-05-2013 |
20140110797 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A MOS semiconductor device has a MOS structure, including a p | 04-24-2014 |
20140231928 | Super Junction Semiconductor Device with an Edge Area Having a Reverse Blocking Capability - A semiconductor device includes a semiconductor layer with a super junction structure including first columns of a first conductivity type and second columns of a second conductivity type opposite the first conductivity type. The super junction structure is formed in a cell area and in an inner portion of an edge area surrounding the cell area. In the inner portion of the edge area a reverse blocking capability is locally reduced by a local modification of the semiconductor layer. The local modification allows an electric field to extend in case an avalanche breakdown occurs. The reverse blocking capability is locally reduced in the edge area, wherein once an avalanche breakdown has been triggered the semiconductor device accommodates a higher reverse voltage. Avalanche ruggedness is improved. | 08-21-2014 |
20140231929 | TRANSISTORS WITH ISOLATION REGIONS - A transistor device is described that includes a source, a gate, a drain, a semiconductor material which includes a gate region between the source and the drain, a plurality of channel access regions in the semiconductor material on either side of the gate, a channel in the semiconductor material having an effective width in the gate region and in the channel access regions, and an isolation region in the gate region. The isolation region serves to reduce the effective width of the channel in the gate region without substantially reducing the effective width of the channel in the access regions. Alternatively, the isolation region can be configured to collect holes that are generated in the transistor device. The isolation region may simultaneously achieve both of these functions. | 08-21-2014 |
20140264637 | STRIP-GROUND FIELD PLATE - Among other things, one or more semiconductor devices and techniques for forming such semiconductor devices are provided. The semiconductor device comprises a strip-ground field plate. The strip-ground field plate is connected to a source region of the semiconductor device and/or a ground plane. The strip-ground field plate provides a release path for a gate edge electric field. The release path directs an electrical field away from a gate region of the semiconductor device. In this way, breakdown voltage and gate charge are improved. | 09-18-2014 |
20140291773 | POWER SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF - A power semiconductor device includes a cell region on a semiconductor substrate, at least a transistor device in the cell region, a peripheral termination region encompassing the cell region, a plurality of epitaxial islands arranged around the cell region, and a grid type epitaxial layer in the peripheral termination region. The grid type epitaxial layer separates the plurality of epitaxial islands from one another. | 10-02-2014 |
20140299946 | SEMICONDUCTOR DEVICE - A semiconductor device concerning an embodiment is provided with a semiconductor layer, an impurity-doped layer selectively formed on the semiconductor layer, and a drain electrode formed on the impurity-doped layer. The semiconductor device is further provided with a source electrode which is formed and isolated from the drain electrode, and a gate electrode which is formed between the source electrode and the drain electrode. The semiconductor device is provided with an insulating film which is formed between the gate electrode and the drain electrode, and a shielding plate which is formed on the insulating film and is electrically connected to the source electrode. At least a part of the shielding plate is formed above an extending portion of the impurity-doped layer which extends in the direction to the gate electrode from the drain electrode. | 10-09-2014 |
20140306298 | Semiconductor Device with Compensation Regions - A semiconductor device includes a semiconductor body including an inner region, and an edge region, a first doped device region of a first doping type in the inner region and the edge region and coupled to a first terminal, and at least one second doped device region of a second doping type complementary to the first doping type in the inner region and coupled to a second terminal. Further, the semiconductor device includes a minority carrier converter structure in the edge region. The minority carrier converter structure includes a first trap region of the second doping type adjoining the first doped device region, and a conductor electrically coupling the first trap region to the first doped device region. | 10-16-2014 |
20140332906 | HIGH-VOLTAGE TRANSISTOR DEVICE AND PRODUCTION METHOD - A body region ( | 11-13-2014 |
20140339649 | FINFET TYPE DEVICE USING LDMOS - The present invention is a finFET type semiconductor device using LDMOS features. The device includes a first portion of a substrate doped with a second doping type and has a first trench, second trench, and first fin. The second portion of the substrate with a first doping type includes a third trench and second fin. The second fin between the second and third trench covers a part the first portion and a part of the second portion of the substrate. A first segment of the second fin is between the second segment and second trench. A second segment covers a part of the second portion of the substrate and is between the first segment and third trench. A gate covering at least a part of the first segment and a part of the first portion and a part of the second portion of the substrate. | 11-20-2014 |
20140339650 | TRANSISTORS HAVING FEATURES WHICH PRECLUDE STRAIGHT-LINE LATERAL CONDUCTIVE PATHS FROM A CHANNEL REQION TO A SOURCE/DRAIN REQION - Some embodiments include transistors having a channel region under a gate, having a source/drain region laterally spaced from the channel region by an active region, and having one or more dielectric features extending through the active region in a configuration which precludes any straight-line lateral conductive path from the channel region to the source/drain region. The dielectric features may be spaced-apart islands in some configurations. The dielectric features may be multi-branched interlocking structures in some configurations. | 11-20-2014 |
20140339651 | Semiconductor Device with a Field Plate Double Trench Having a Thick Bottom Dielectric - Disclosed is a power device, such as power MOSFET, and method for fabricating same. The device includes an upper trench situated over a lower trench, where the upper trench is wider than the lower trench. The device further includes a trench dielectric inside the lower trench and on sidewalls of the upper trench. The device also includes an electrode situated within the trench dielectric. The trench dielectric of the device has a bottom thickness that is greater than a sidewall thickness. | 11-20-2014 |
20140346614 | SEMICONDUCTOR DEVICE - A semiconductor device includes a gate structure over a substrate, a source region in the substrate, where the source region is adjacent to the gate structure. Additionally, the semiconductor device includes a drain region in the substrate, where the drain region is adjacent to the gate structure. Moreover, the semiconductor device includes a first dislocation in the substrate between the source region and the drain region. Furthermore, the semiconductor device includes a second dislocation in the substrate between the source region and the drain region, where the second dislocation is substantially parallel to the first dislocation. | 11-27-2014 |
20140374842 | Semiconductor Device with Self-Charging Field Electrodes - A semiconductor device includes a drift region of a first doping type, a junction between the drift region and a device region, and a field electrode structure in the drift region. The field electrode structure includes a field electrode, a field electrode dielectric adjoining the field electrode, arranged between the field electrode and the drift region, and having an opening, and at least one of a field stop region and a generation region. The semiconductor device further includes a coupling region of a second doping type complementary to the first doping type. The coupling region is electrically coupled to the device region and coupled to the field electrode. | 12-25-2014 |
20150008539 | SEMICONDUCTOR DEVICE - A field plate electrode is repetitively disposed in a folded manner or a spiral shape in a direction along an edge of a first circuit region. A coupling transistor couples a first circuit to a second circuit lower in supply voltage than the first circuit. A second conductivity type region is disposed around the coupling transistor. A part of the field plate electrode partially overlaps with the second conductivity type region. The field plate electrode is electrically coupled to a drain electrode of the coupling transistor at a portion located on the first circuit region side from a center thereof in a width direction of the separation region. A ground potential or a power potential of the second circuit is applied to the field plate electrode at a portion located on the second conductivity type region side from the center. | 01-08-2015 |
20150014791 | SEMICONDUCTOR DEVICE, AND A METHOD OF IMPROVING BREAKDOWN VOLTAGE OF A SEMICONDUCTOR DEVICE - A semiconductor device having a first layer adjoining a semiconductor layer, and further comprising at least one field modification structure positioned such that, in use, a potential at the field modification structure causes an E-field vector at a region of an interface between the semiconductor and the first layer to be modified. | 01-15-2015 |
20150021713 | GUARD RING STRUCTURE OF SEMICONDUCTOR ARRANGEMENT - Among other things, one or more semiconductor arrangements and techniques for forming such semiconductor arrangements are provided. A semiconductor arrangement comprises a first guard ring surrounding at least a portion of a device, and a first poly layer formed over the first guard ring. | 01-22-2015 |
20150091104 | SEMICONDUCTOR STRUCTURE AND SEMICONDUCTOR DEVICE HAVING THE SAME - The invention provides a semiconductor structure and a semiconductor device having such semiconductor structure. The semiconductor structure includes: a substrate; a first well having a first conductivity type, which is provided on the substrate; a second well having a second conductivity type and contacting the first well at a boundary in between in a lateral direction; and a plurality of mitigation regions having the first conductivity type or the second conductivity type, provided in the first well and being close to the boundary in a lateral direction and penetrating the first well in a vertical direction. | 04-02-2015 |
20150102427 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING - A semiconductor device includes a substrate having an active region, a drain region in the active region, a source region in the active region, a gate structure, and a conductive field plate. The gate structure extends in a first direction over the active region. The gate structure is arranged between the drain region and the source region in a second direction transverse to the first direction. The conductive field plate extends in the second direction over an edge of the active region. | 04-16-2015 |
20150108588 | RADIATION HARDENED MOS DEVICES AND METHODS OF FABRICATION - Radiation hardened NMOS devices suitable for application in NMOS, CMOS, or BiCMOS integrated circuits, and methods for fabricating them. A device includes a p-type silicon substrate, a field oxide surrounding a moat region on the substrate tapering through a Bird's Beak region to a gate oxide within the moat region, a heavily-doped p-type guard region underlying at least a portion of the Bird's Beak region and terminating at the inner edge of the Bird's Beak region, a gate included in the moat region, and n-type source and drain regions spaced by a gap from the inner edge of the Bird's Beak and guard regions. A variation of minor alterations to the conventional moat and n-type source/drain masks. The resulting devices have improved radiation tolerance while having a high breakdown voltage and minimal impact on circuit density. | 04-23-2015 |
20150318345 | SEMICONDUCTOR DEVICE CONFIGURED FOR AVOIDING ELECTRICAL SHORTING - In one aspect a semiconductor device as set forth herein can include a spacer having a first section of a first material and a second section of a second material, the second section disposed above a certain elevation and the first section disposed below the certain elevation. In one aspect a semiconductor device as set forth herein can include a conductive gate structure having a first length at elevations below a certain elevation and a second length at elevations above the certain elevation, the second length being less than the first length. A semiconductor device having one or more of a plural material spacer or a reduced length upper elevation conductive gate structure can feature a reduced likelihood of electrical shorting. | 11-05-2015 |
20150340229 | TRANSISTOR(S) WITH DIFFERENT SOURCE/DRAIN CHANNEL JUNCTION CHARACTERISTICS, AND METHODS OF FABRICATION - Field-effect transistors (FETs) and methods of fabricating field-effect transistors are provided, with one or both of a source cavity or a drain cavity having different channel junction characteristics. The methods include, for instance, recessing a semiconductor material to form a cavity adjacent to a channel region of the transistor, the recessing defining a bottom channel interface surface and a sidewall channel interface surface within the cavity; providing a protective liner over the sidewall channel interface surface, with the bottom channel interface surface being exposed within the cavity; processing the bottom channel interface surface to facilitate forming a first channel junction of the transistor; and removing the protective liner from over the sidewall channel interface surface, and subsequently processing the sidewall channel interface surface to form a second channel junction of the transistor, where the first and second channel junctions have different channel junction characteristics. | 11-26-2015 |
20150372077 | PROCESSES USED IN FABRICATING A METAL-INSULATOR-SEMICONDUCTOR FIELD EFFECT TRANSISTOR - During fabrication, a second oxide layer is disposed over a first region and a second region of a structure. The second region includes a first oxide layer between the second oxide layer and an epitaxial layer. The first region corresponds to an active region of a metal-insulator-semiconductor field effect transistor (MISFET), and a first-type dopant source region, a second-type dopant body region, and a second-type dopant implant region are formed in the first region. The second region corresponds to a termination region of the MISFET. A mask is formed over the second region, and parts of the second oxide layer and the first oxide layer that are exposed through the gaps are removed, thereby exposing the epitaxial layer. Second-type dopant is deposited into the epitaxial layer through the resultant openings in the first and second oxide layers, thereby forming field rings for the MISFET. | 12-24-2015 |
20160013178 | ELECTROSTATIC DISCHARGE PROTECTION DEVICE AND SEMICONDUCTOR DEVICE INCLUDING THE SAME | 01-14-2016 |
20160020323 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - A semiconductor device includes a fin structure, an insulating structure, a protruding structure, an epitaxial structure, and a gate structure. The fin structure and the insulating structure are disposed on the substrate. The protruding structure is in direct contact with the substrate and partially protrudes from the insulating structure, and the protruding structure is the fin structure. The epitaxial structure is disposed on a top surface of the fin structure and completely covers the top surface of the fin structure. In addition, the epitaxial structure has a curved top surface. The gate structure covers the fin structure and the epitaxial structure. | 01-21-2016 |
20160027872 | FIELD EFFECT TRANSISTOR WITH CHANNEL CORE MODIFIED FOR A BACKGATE BIAS AND METHOD OF FABRICATION - A semiconductor device, includes a substrate, a source structure and a drain structure formed on the substrate. At least one interconnect structure interconnects the source structure and the drain structure and serves as a channel therebetween. A gate structure is formed over the at least one interconnect structure to provide a control of a conductivity of carriers in the channel. Each of the interconnect structures include a center core serving as a backbias electrode for the channel. | 01-28-2016 |
20160064495 | SEMICONDUCTOR DEVICES WITH INTEGRATED HOLE COLLECTORS - Transistor devices which include semiconductor layers with integrated hole collector regions are described. The hole collector regions are configured to collect holes generated in the transistor device during operation and transport them away from the active regions of the device. The hole collector regions can be electrically connected or coupled to the source, the drain, or a field plate of the device. The hole collector regions can be doped, for example p-type or nominally p-type, and can be capable of conducting holes but not electrons. | 03-03-2016 |
20160064559 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor substrate has a main surface with an n type offset region having a trench portion formed of a plurality of trenches extending in a direction from an n | 03-03-2016 |
20160071938 | Semiconductor Device with Breakdown Preventing Layer - A semiconductor device with a breakdown preventing layer is provided. The breakdown preventing layer can be located in a high-voltage surface region of the device. The breakdown preventing layer can include an insulating film with conducting elements embedded therein. The conducting elements can be arranged along a lateral length of the insulating film. The conducting elements can be configured to split a high electric field spike otherwise present in the high-voltage surface region during operation of the device into multiple much smaller spikes. | 03-10-2016 |
20160079066 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device includes a semiconductor region, a first electrode provided on the semiconductor region, a second electrode provided on the semiconductor region adjacent to and spaced from a side of the first electrode, and containing an identical material as the material of the first electrode, a third electrode provided on the semiconductor region in a location between the first electrode and the second electrode, a first insulating film provided between the semiconductor region and the third electrode, and a fourth electrode connected to the third electrode containing the same material as the material of the first electrode and the second electrode. | 03-17-2016 |
20160079373 | SEMICONDUCTOR DEVICE - A semiconductor device includes a compound semiconductor layer, an insulating element, and a conductive element. The conductive element includes a plurality of conductive regions which are spaced from the compound semiconductor layer in a first direction. The insulating element is provided between the compound semiconductor layer and the conductive element. A length of each of the plurality of conductive regions in a second direction which intersects the first direction becomes longer the farther the individual one of the plurality of conductive regions is spaced from the compound semiconductor layer. | 03-17-2016 |
20160111502 | SEMICONDUCTOR DEVICE WITH IMPROVED FIELD PLATE - A transistor device includes a semiconductor body, a spacer layer, and a field plate. The spacer layer is over at least a portion of a surface of the semiconductor body. The field plate is over at least a portion of the spacer layer, and includes a semiconductor layer between a first refractory metal interposer layer and a second refractory metal interposer layer. By including the semiconductor layer between the first refractory metal interposer layer and the second refractory metal interposer layer, the electromigration of metals in the field plate is significantly reduced. Since electromigration of metals in the field plate is a common cause of transistor device failures, reducing the electromigration of metals in the field plate improves the reliability and lifetime of the transistor device. | 04-21-2016 |
20160126334 | SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF - The present invention provides a semiconductor structure, including a substrate, having a fin structure disposed thereon, a gate structure, crossing over parts of the fin structure. The top surface of the fin structure which is covered by the gate structure is defined as a first top surface, and the top surface of the fin structure which is not covered by the gate structure is defined as a second top surface. The first top surface is higher than the second top surface, and a spacer covers the sidewalls of the gate structure. The spacer includes an inner spacer and an outer spacer, and the outer pacer further contacts the second top surface of the fin structure directly. | 05-05-2016 |
20160380047 | SEMICONDUCTOR DEVICE - A semiconductor device includes a first electrode, a first semiconductor layer of a first conductivity type located on the first electrode, a second semiconductor layer of a second conductivity type located on the first semiconductor layer, a third semiconductor layer of the first conductivity type located on a portion of the second semiconductor layer, a second electrode located in the first semiconductor layer, the second semiconductor layer and the third semiconductor layer, the second electrode extending along and around an outer edge of the first semiconductor layer, and spaced from the second semiconductor layer by an insulating film, a wiring located on the third semiconductor layer and connected to the second electrode, and a third electrode connected to the second semiconductor layer and the third semiconductor layer. | 12-29-2016 |
20160380062 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device comprises: a substrate; a semiconductor layer formed on the substrate; a source electrode, a drain electrode and a gate electrode between the source electrode and the drain electrode formed on the semiconductor layer; and a source field plate formed on the semiconductor layer. The source field plate sequentially comprises: a start portion electrically connected to the source electrode; a first intermediate portion spaced apart from the semiconductor layer with air therebetween; a second intermediate portion disposed between the gate electrode and the drain electrode in a horizontal direction, without air between the second intermediate portion and the semiconductor layer; and an end portion spaced apart from the semiconductor layer with air therebetween. | 12-29-2016 |