Class / Patent application number | Description | Number of patent applications / Date published |
257309000 | With increased effective electrode surface area (e.g., tortuous path, corrugated, or textured electrodes) | 11 |
20080277710 | SEMICONDUCTOR DEVICES AND METHODS OF FORMING THE SAME - Provided are semiconductor devices and methods of forming the same. In the semiconductor devices and methods of forming the same, different insulating patterns are disposed around a cell gate pattern and a peripheral gate pattern to impose different heat budgets around the cell gate pattern and the peripheral gate pattern. For this purpose, a semiconductor substrate having a cell array region and a peripheral circuit region is prepared. First and second cell gate patterns are disposed in the cell array region. A peripheral gate pattern is disposed in the peripheral circuit region to be adjacent to the second cell gate pattern. Buried insulating patterns are disposed around the first and second cell gate patterns. Planarization insulating patterns are disposed around the peripheral gate pattern. | 11-13-2008 |
20090096003 | SEMICONDUCTOR CELL STRUCTURE INCLUDING BURIED CAPACITOR AND METHOD FOR FABRICATION THEREOF - A semiconductor structure and a method for fabricating the semiconductor structure include at least one field effect transistor, and also a capacitor, located over a substrate. In particular, the capacitor is located interposed between the field effect transistor and the substrate. The field effect transistor may include a planar field effect transistor as well as a fin-FET. The capacitor may be connected with a conductor plug layer to a source/drain region of the field effect transistor to form a dynamic random access memory cell structure. | 04-16-2009 |
20090108319 | DRAM STACK CAPACITOR AND FABRICATION METHOD THEREOF - A DRAM stack capacitor and a fabrication method thereof has a first capacitor electrode formed of a conductive carbon layer overlying a semiconductor substrate, a capacitor dielectric layer and a second capacitor electrode. The first capacitor electrode is of crown shape geometry and possesses an inner surface and an outer surface. The DRAM stack capacitor features the outer surface of the first capacitor electrode as an uneven surface. | 04-30-2009 |
20100052029 | TRANSISTOR STRUCTURE AND DYNAMIC RANDOM ACCESS MEMORY STRUCTURE INCLUDING THE SAME - A dynamic random access memory structure is disclosed, in which, the active area is a donut-type pillar at which a novel vertical transistor is disposed and has a gate filled in the central cavity of the pillar and upper and lower sources/drains located in the upper and the lower portions of the pillar respectively. A buried bit line is formed in the substrate beneath the transistor. A word line is horizontally disposed above the gate. A capacitor is disposed above the word line as well as the gate and electrically connected to the upper source/drain through a node contact. The node contact has a reverse-trench shape with the top surface electrically connected to the capacitor and with the bottom of the sidewalls electrically connected to the upper source/drain. The word line passes through the space confined by the reverse-trench shape. | 03-04-2010 |
20130187212 | HYBRID ELECTRICAL CONTACTS - Devices having hybrid-vertical contacts. In certain embodiments, a substrate includes a lower patterned layer that has a target conductor. A hybrid-vertical contact may be disposed directly on the target conductor. The hybrid vertical contact may include a lower-vertical contact directly on the target conductor and an upper-vertical contact directly on the lower-vertical contact. The upper-vertical contact may have an upper width that is greater than a lower width of the lower-vertical contact. | 07-25-2013 |
20150060973 | ARRAY SUBSTRATE AND LIQUID CRYSTAL DISPLAY DEVICE USING SAME - An array substrate for a liquid crystal display device includes a first storage capacitor and a second storage capacitor for increased capacitance. The first storage capacitor is formed by a first common electrode and a pixel electrode. The second storage capacitor is formed by a second common electrode and the pixel electrode. | 03-05-2015 |
20150333117 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - One semiconductor device includes lower electrodes arranged in rows along first and second directions parallel to the surface of a semiconductor substrate and extending in a third direction perpendicular to the surface of the substrate, a first support film arranged on the upper end of the lower electrodes and having first openings, a second support film arranged in the middle of the lower electrodes in the third direction, and having second openings aligned in a plane in the same pattern as the first openings, a capacitance insulating film covering the surface of the lower electrodes, and upper electrodes covering the surface of the capacitance insulating film. A portion of each of eight lower electrodes contained in two lower electrode unit groups adjacent in the first direction are collectively positioned inside of the first and second openings. A lower electrode unit group is four lower electrodes adjacent in the second direction. | 11-19-2015 |
20160035818 | FORMING A VERTICAL CAPACITOR AND RESULTING DEVICE - Methods for forming a vertical capacitance structure and the resulting devices are disclosed. Embodiments may include forming fins on a substrate; conformally forming a first metal layer over the fins; conformally forming an insulation layer over the first metal layer; and forming a second metal layer over the insulation layer. | 02-04-2016 |
20160071850 | Semiconductor Integrated Circuit Device and Method for Producing the Same - A capacitive element has improved electrical properties. The capacitive element is configured in a DRAM cell and has a lower electrode, a capacitive insulator film formed over the lower electrode, and an upper electrode formed over the capacitive insulator film. The upper electrode has a structure in which from the capacitive insulator film side of this electrode, a first upper electrode, a second upper electrode and a third upper electrode are stacked in turn. The third upper electrode is a tungsten film that may contain an impurity. Between the first and third upper electrodes, the second upper electrode is interposed which is a barrier film for preventing the possible impurity in the third upper electrode from diffusing into the capacitive insulator film. | 03-10-2016 |
20160197138 | HIGH VOLTAGE METAL-OXIDE-METAL (HV-MOM) DEVICE, HV-MOM LAYOUT AND METHOD OF MAKING THE HV-MOM DEVICE | 07-07-2016 |
20160379970 | DECOUPLING CAPACITOR CELL, CELL-BASED IC, AND PORTABLE DEVICE - A decoupling capacitor cell includes: a first decoupling capacitor formed by only a pMOS transistor; and a second decoupling capacitor formed by two metal layers. The decoupling capacitor cell is arranged in an unused region not occupied by basic cells in a cell-based IC and is connected to a power wiring and a ground wiring. | 12-29-2016 |