Class / Patent application number | Description | Number of patent applications / Date published |
257142000 | Having impurity doping for gain reduction | 8 |
20100038675 | POWER SEMICONDUCTOR DEVICES AND METHODS FOR MANUFACTURING THE SAME - A power semiconductor device that realizes high-speed turnoff and soft switching at the same time has an n-type main semiconductor layer that includes lightly doped n-type semiconductor layers and extremely lightly doped n-type semiconductor layers arranged alternately and repeatedly between a p-type channel layer and an n | 02-18-2010 |
20100244093 | SEMICONDUCTOR MODULE - A controlled-punch-through semiconductor device with a four-layer structure is disclosed which includes layers of different conductivity types, a collector on a collector side, and an emitter on an emitter side which lies opposite the collector side. The semiconductor device can be produced by a method performed in the following order: producing layers on the emitter side of wafer of a first conductivity type; thinning the wafer on a second side; applying particles of the first conductivity type to the wafer on the collector side for forming a first buffer layer having a first peak doping concentration in a first depth, which is higher than doping of the wafer; applying particles of a second conductivity type to the wafer on the second side for forming a collector layer on the collector side; and forming a collector metallization on the second side. At any stage particles of the first conductivity type can be applied to the wafer on the second side for forming a second buffer layer with a second peak doping concentration lower than the first peak doping concentration of the first buffer layer, but higher than the doping of the wafer. A third buffer layer can be arranged between the first depth and the second depth with a doping concentration which is lower than the second peak doping concentration of the second buffer layer. Thermal treatment can be used for forming the first buffer layer, the second buffer layer and/or the collector layer. | 09-30-2010 |
20110079819 | IGBT WITH FAST REVERSE RECOVERY TIME RECTIFIER AND MANUFACTURING METHOD THEREOF - An IGBT with a fast reverse recovery time rectifier includes an N-type drift epitaxial layer, a gate, a gate insulating layer, a P-type doped base region, an N-type doped source region, a P-type doped contact region, and a P-type lightly doped region. The P-type doped base region is disposed in the N-type drift epitaxial layer, and the P-type doped contact region is disposed in the N-type drift epitaxial layer. The P-type lightly doped region is disposed between the P-type contact doped region and the N-type drift epitaxial layer, and is in contact with the N-type drift epitaxial layer. | 04-07-2011 |
20120286326 | POWER SEMICONDUCTOR DEVICES AND METHODS FOR MANUFACTURING THE SAME - A power semiconductor device that realizes high-speed turnoff and soft switching at the same time has an n-type main semiconductor layer that includes lightly doped n-type semiconductor layers and extremely lightly doped n-type semiconductor layers arranged alternately and repeatedly between a p-type channel layer and an n | 11-15-2012 |
20130256747 | POWER SEMICONDUCTOR FIELD EFFECT TRANSISTOR STRUCTURE WITH CHARGE TRAPPING MATERIAL IN THE GATE DIELECTRIC - The subject disclosure presents power semiconductor devices, and methods for manufacture thereof, with improved ruggedness and. In an aspect, the power semiconductor devices are power field effect transistors (FETs) having enhanced suppression of the activation of the parasitic bipolar junction transistor (BJT) and a normal threshold value. The devices comprise a doped source ( | 10-03-2013 |
20140015007 | Semiconductor Device with Charge Carrier Lifetime Reduction Means - A semiconductor device includes a cell region having at least one device cell, wherein the at least one device cell includes a first device region of a first conductivity type. The semiconductor device further includes a drift region of a second conductivity type adjoining the first device region of the at least one device cell, a doped region of the first conductivity type adjoining the drift region, and charge carrier lifetime reduction means configured to reduce a charge carrier lifetime in the doped region of the first conductivity type. | 01-16-2014 |
20150091055 | SEMICONDUCTOR DEVICE - A semiconductor device includes a first region of a first conductivity type, a collector electrode electrically connected to a first side of the first region, first and second gate electrodes and first and second conductor electrodes, each of the gate and conductor electrodes extending into the first region from a second side thereof that is opposite to the first side, an emitter electrode electrically connected to the conductor electrodes, and a second region of the first conductivity type, that is adjacent to the gate electrodes, electrically connected to the emitter electrode, and spaced from the first and second conductor electrodes. | 04-02-2015 |
20150129930 | INSULATING GATE-TYPE BIPOLAR TRANSISTOR - An object of the present invention is to provide a trench gate type IGBT achieving both retention of withstand voltage and lowering of ON-state voltage and to provide a method for manufacturing the trench gate type IGBT. The IGBT according to the present invention is an SJ-RC-IGBT which includes a drift layer having super junction structure, and includes an IGBT area and an FWD area on the rear surface. In the IGBT according to the present invention, a first drift layer has an impurity concentration of 1×10 | 05-14-2015 |