Entries |
Document | Title | Date |
20080224124 | Transistor on the basis of new quantum interference effect - A quantum interference transistor comprising a thin metal film having a protrusion and a thin insulating layer between the metal film and protrusion. A potential barrier is formed in the region beneath the protrusion as a result of quantum interference caused by the geometry of the film and protrusion. A voltage applied between the electrically isolated protrusion (“island”) and the thin film leads to a change in the electron wave function of the island which in turn leads to a change in the Fermi level of the metal film in the entire region beneath the protrusion. Consequently, a potential barrier may or may not exist depending on the applied voltage, thus providing the present invention with the transistor-like property of switching between open and closed states. | 09-18-2008 |
20080237579 | QUANTUM COMPUTING DEVICE AND METHOD INCLUDING QUBIT ARRAYS OF ENTANGLED STATES USING NEGATIVE REFRACTIVE INDEX LENSES - A quantum computing device and method employs qubit arrays of entangled states using negative refractive index lenses. A qubit includes a pair of neutral atoms separated by or disposed on opposite sides of a negative refractive index lens. The neutral atoms and negative refractive index lens are selectively energized and/or activated to cause entanglement of states of the atoms. The quantum computing device enjoys a novel architecture that is workable and scalable in terms of size and wavelength. | 10-02-2008 |
20080251782 | RANDOM NUMBER GENERATING DEVICE - The objective is to provide a random number generating device having a smaller circuit size and a smaller value of output bias. The random number generating device includes a pair of first and second current paths arranged in parallel with each other, and a pair of first and second fine particles, which can mutually exchange charges, and are located in the vicinity of the first and second current paths. | 10-16-2008 |
20080251783 | RANDOM NUMBER GENERATING DEVICE - The objective is to provide a random number generating device having a smaller circuit size and a smaller value of output bias. The random number generating device includes a pair of first and second current paths arranged in parallel with each other, and a pair of first and second fine particles, which can mutually exchange charges, and are located in the vicinity of the first and second current paths. | 10-16-2008 |
20080265243 | Magnetic floating gate flash memory structures - Methods of forming ferromagnetic floating gate structures are described. The methods include atomic layer deposition of multiple precursor films, followed by alloying the metals in the precursor films, to form a ferromagnetic floating gate. Devices that include ferromagnetic floating gates formed with these methods are also described. | 10-30-2008 |
20080315184 | Switching Element - A switching element comprising: an insulative substrate; a first electrode and a second electrode provided on one surface of the insulative substrate; and an interelectrode gap which is provided between the first electrode and the second electrode, and which has a gap on the order of nanometers in which switching phenomenon of resistance occurs by applying predetermined voltage between the first electrode and the second electrode, wherein the one surface of the insulative substrate contains nitrogen. | 12-25-2008 |
20090159872 | Reducing Ambipolar Conduction in Carbon Nanotube Transistors - Ambipolar conduction can be reduced in carbon nanotube transistors by forming a gate electrode of a metal. Metal sidewall spacers having different workfunctions than the gate electrode may be formed to bracket the metal gate electrode. | 06-25-2009 |
20090212279 | Nanostructure-Based Electronic Device - The nanostructure-based electronic device comprises a solid support, an organic template layer, a nanostructure and electrodes. The organic template layer is on the surface of the solid support, and has a surface comprising a pair of spaced, electrically-charged regions arranged in tandem in an electrically-neutral background. The nanostructure is elongate, is electrically-conducting, and extends between the charged regions. The electrodes are located the surface of the template layer and are at least co-extensive with the charged regions. | 08-27-2009 |
20090315020 | Diodes, and Methods of Forming Diodes - Some embodiments include methods of forming diodes in which a first electrode is formed to have a pedestal extending upwardly from a base. At least one layer is deposited along an undulating topography that extends across the pedestal and base, and a second electrode is formed over the least one layer. The first electrode, at least one layer, and second electrode together form a structure that conducts current between the first and second electrodes when voltage of one polarity is applied to the structure, and that inhibits current flow between the first and second electrodes when voltage having a polarity opposite to said one polarity is applied to the structure. Some embodiments include diodes having a first electrode that contains two or more projections extending upwardly from a base, having at least one layer over the first electrode, and having a second electrode over the at least one layer. | 12-24-2009 |
20100072461 | THERMO-ELECTRIC SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A thermo-electric semiconductor device is provided. The thermo-electric semiconductor device includes: a first electrode layer; a spacer layer formed on the first electrode layer and having a plurality of pillars with a uniform height, the plurality of pillars thermally grown and protruded on a surface of the spacer layer; and a second electrode layer formed over the spacer layer in such a manner as to contact tops of the protruded pillars. | 03-25-2010 |
20100123122 | SELECT DEVICES INCLUDING AN OPEN VOLUME, MEMORY DEVICES AND SYSTEMS INCLUDING SAME, AND METHODS FOR FORMING SAME - Select devices including an open volume that functions as a high bandgap material having a low dielectric constant are disclosed. The open volume may provide a more nonlinear, asymmetric I-V curve and enhanced rectifying behavior in the select devices. The select device may comprise, for example, a metal-insulator-insulator-metal (MIIM) device. Various methods may be used to form select devices and memory systems including such select devices. Memory devices and electronic systems include such select devices. | 05-20-2010 |
20100237325 | Highly resolved, low noise, room-temperature coulomb-staircase and blockade up to 2.2V in isolated 50 micron long one dimensional necklace of 10 NM AU particles - Coulomb blockade in metal nanoparticles isolated by a tunneling barrier is considered to be a potential solution to low power, robust, high-speed electronic switching device operating at single-electron transport. However, the switching voltage equal to the threshold voltage to overcome coulomb blockade for these devices is typically in the 10 mV range and/or operating at currents well below 1 nA, which inhibits their application as a practical device. Theoretically, a one dimensional nanoparticle necklace is predicted to be an ideal structure to achieve higher switching voltages. The present invention provides a single-electron device composed of a necklace of about 5000 nanoparticles. The linear necklace is self-assembled by interfacial phenomena along a triple-phase line of fiber, a substrate and electrolyte containing nanoparticles. The I-V measurements on the system show both coulomb blockade and staircase, with high currents and high threshold voltage of 1-3 V. The present invention also provides methods for constructing such a device. | 09-23-2010 |
20110068325 | Diodes, and Methods of Forming Diodes - Some embodiments include methods of forming diodes in which a first electrode is formed to have a pedestal extending upwardly from a base. At least one layer is deposited along an undulating topography that extends across the pedestal and base, and a second electrode is formed over the least one layer. The first electrode, at least one layer, and second electrode together form a structure that conducts current between the first and second electrodes when voltage of one polarity is applied to the structure, and that inhibits current flow between the first and second electrodes when voltage having a polarity opposite to said one polarity is applied to the structure. Some embodiments include diodes having a first electrode that contains two or more projections extending upwardly from a base, having at least one layer over the first electrode, and having a second electrode over the at least one layer. | 03-24-2011 |
20110068326 | SCHOTTKY BARRIER TUNNEL TRANSISTOR AND METHOD FOR FABRICATING THE SAME - A Schottky barrier tunnel transistor includes a gate electrode, and source and drain regions. The gate electrode is formed over a channel region of a substrate to form a Schottky junction with the substrate. The source and drain regions are formed in the substrate exposed on both sides of the gate electrode. | 03-24-2011 |
20110198570 | SELF ASSEMBLED NANO DOTS (SAND) AND NON-SELF ASSEMBLED NANO-DOTS (NSAND) DEVICE STRUCTURES AND FABRICATION METHODS THEREOF TO CREATE SPACERS FOR ENERGY TRANSFER - A structure and method for transferring electronic charge or heat or light between substrates. The structure includes first and second substrates separated from one another and a plurality of localized spacers connecting the first and second substrates together. At least one of the localized spacers having a lateral dimension less than 350 nm. A sub-micron separation distance between the first and second substrates is configured to provide carrier tunneling or to provide heat transfer or light transfer between the first and second substrates. The method provides charge carriers or heat or light to a first substrate. The first substrate is separated from a second substrate by at least one localized spacer having a lateral dimension less than 350 nm and tunnels the charge carriers or couples the heat or couples light from the first substrate to the second substrate across a sub-micron gap between the first and second substrates formed by the at least one localized spacer. | 08-18-2011 |
20110220876 | SEMICONDUCTOR MEMORY DEVICE - According to an embodiment, a semiconductor memory device capable of stably operating even when an element is shrunk is provided. The semiconductor memory device of the embodiment includes: first and second diodes serially connected between power sources of two different potentials, formed by nanowires, and exhibiting negative differential resistances; and a select transistor connected between the first diode and the second diode. The nanowires are preferably silicon nanowires. The thickness of the silicon nanowires is preferably 8 nm or less. | 09-15-2011 |
20120112167 | NANOSCALE ELECTRONIC DEVICE - One example of the present invention is a nanoscale electronic device comprising a first conductive electrode, a second conductive electrode, and an anisotropic dielectric material layered between the first and second electrodes having a permittivity in a direction approximately that of the shortest distance between the first and second electrodes less than the permittivity in other directions within the anisotropic dielectric material. Additional examples of the present invention include integrated circuits that contain multiple nanoscale electronic devices that each includes an anisotropic dielectric material layered between first and second electrodes having a permittivity in a direction approximately that of the shortest distance between the first and second electrodes less than the permittivity in other directions within the anisotropic dielectric material. | 05-10-2012 |
20130056708 | UNIT PIXEL OF IMAGE SENSOR AND PHOTO DETECTOR THEREOF - A unit pixel of an image sensor and a photo detector are disclosed. The photo detector of the present invention configured to absorb light can include: a light-absorbing part configured to absorb light by being formed in a floated structure; an oxide film being in contact with one surface of the light-absorbing part; a source being in contact with one side of the other surface of the oxide film and separated from the light-absorbing part with the oxide film therebetween; a drain facing the source so as to be in contact with the other side of the other surface of the oxide film and separated from the light-absorbing part with the oxide film therebetween; and a channel interposed between the source and the drain and configured to form flow of an electric current between the source and the drain. | 03-07-2013 |
20130056709 | UNIT PIXEL OF IMAGE SENSOR AND PHOTO DETECTOR THEREOF - A unit pixel of an image sensor and a photo detector are disclosed. The photo detector can include: a substrate in which a V-shaped groove having a predetermined angle is formed; a light-absorbing part formed in a floated structure above the V-shaped groove and to which light is incident; an oxide film formed between the light-absorbing part and the V-shaped groove and in which tunneling occurs; a source formed adjacent to the oxide film on a slope of one side of the V-shaped groove and separated from the light-absorbing part by the oxide film; a drain formed adjacent to the oxide film on a slope of the other side of the V-shaped groove and separated from the light-absorbing part by the oxide film; and a channel interposed between the source and the drain along the V-shaped groove to form flow of an electric current between the source and the drain. | 03-07-2013 |
20130270523 | Free Layer with High Thermal Stability for Magnetic Device Applications by Insertion of a Boron Dusting Layer - A boron or boron containing dusting layer such as CoB or FeB is formed along one or both of top and bottom surfaces of a free layer at interfaces with a tunnel barrier layer and capping layer to improve thermal stability while maintaining other magnetic properties of a MTJ stack. Each dusting layer has a thickness from 0.2 to 20 Angstroms and may be used as deposited, or at temperatures up to 400° C. or higher, or following a subsequent anneal at 400° C. or higher. The free layer may be a single layer of CoFe, Co, CoFeB or CoFeNiB, or may include a non-magnetic insertion layer. The resulting MTJ is suitable for STT-MRAM memory elements or spintronic devices. Perpendicular magnetic anisotropy is maintained in the free layer at temperatures up to 400° C. or higher. Ku enhancement is achieved and the retention time of a memory cell for STT-MRAM designs is increased. | 10-17-2013 |
20140054551 | GATE TUNABLE TUNNEL DIODE - A gate tunable diode is provided. The gate tunable diode includes a gate dielectric formed on a gate electrode and a graphene electrode formed on the gate dielectric. Also, the gate tunable diode includes a tunnel dielectric formed on the graphene electrode and a tunnel electrode formed on the tunnel dielectric. | 02-27-2014 |
20150144887 | MANUFACTURABLE SUB-3 NANOMETER PALLADIUM GAP DEVICES FOR FIXED ELECTRODE TUNNELING RECOGNITION - A technique is provided for manufacturing a nanogap in a nanodevice. An oxide is disposed on a wafer. A nanowire is disposed on the oxide. A helium ion beam is applied to cut the nanowire into a first nanowire part and a second nanowire part which forms the nanogap in the nanodevice. Applying the helium ion beam to cut the nanogap forms a signature of nanowire material in proximity to at least one opening of the nano gap. | 05-28-2015 |
20150144888 | MANUFACTURABLE SUB-3 NANOMETER PALLADIUM GAP DEVICES FOR FIXED ELECTRODE TUNNELING RECOGNITION - A technique is provided for manufacturing a nanogap in a nanodevice. An oxide is disposed on a wafer. A nanowire is disposed on the oxide. A helium ion beam is applied to cut the nanowire into a first nanowire part and a second nanowire part which forms the nanogap in the nanodevice. Applying the helium ion beam to cut the nanogap forms a signature of nanowire material in proximity to at least one opening of the nanogap. | 05-28-2015 |