Class / Patent application number | Description | Number of patent applications / Date published |
257022000 | With specified semiconductor materials | 40 |
20090256136 | MICRORESONATOR SYSTEMS AND METHODS OF FABRICATING THE SAME - Various embodiments of the present invention are related to microresonator systems that can be used as a laser, a modulator, and a photodetector and to methods for fabricating the microresonator systems. In one embodiment, a microdisk comprises: a top layer; a bottom layer; an intermediate layer having at least one quantum well, the intermediate layer sandwiched between the top layer and the bottom layer; a peripheral annular region including at least a portion of the top, intermediate, and bottom layers; and a current isolation region configured to occupy at least a portion of a central region of the microdisk including at least a portion of the top, intermediate, and bottom layers and having relatively lower index of refraction than the peripheral annular region. | 10-15-2009 |
20090289244 | SEMICONDUCTOR HETEROSTRUCTURE NANOWIRE DEVICES - Nanowire devices comprising core-shell or segmented nanowires are provided. In these nanowire devices, strain can be used as a tool to form metallic portions in nanowires made from compound semiconductor materials, and/or to create nanowires in which embedded quantum dots experience negative hydrostatic pressure or high positive hydrostatic pressure, whereby a phase transitions may occur, and/or to create exciton crystals. | 11-26-2009 |
20100117061 | NITRIDE SEMICONDUCTOR DEVICE - There is provided a nitride semiconductor device. A nitride semiconductor device according to an aspect of the invention may include: an n-type nitride semiconductor layer; a p-type nitride semiconductor layer; an active layer provided between the n-type and p-type nitride semiconductor layers and having quantum well layers and quantum barrier layers alternately stacked on each other; and an electron blocking layer provided between the active layer and the p-type nitride semiconductor layer, and having a plurality of first nitride layers formed of a material having a higher band gap energy than the quantum barrier layers and a plurality of second nitride layers formed of a material having a lower band gap energy than the first nitride layers, the first and second nitride layers alternately stacked on each other to form a stacked structure, wherein the plurality of first nitride layers have energy levels bent at predetermined inclinations, and with greater proximity to the p-type nitride semiconductor layer, the first nitride layers have a smaller inclination of the energy level. | 05-13-2010 |
20110001127 | SEMICONDUCTOR MATERIAL, METHOD OF MAKING THE SAME, AND SEMICONDUCTOR DEVICE - A semiconductor material is provided comprising: a composition graded layer, formed on a Si substrate or an interlayer formed thereon, comprising a composition of Al | 01-06-2011 |
20110101307 | SUBSTRATE FOR SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - Provided are a semiconductor substrate including an uneven structure disposed on a surface of a substrate, a buffer layer disposed on the uneven structure, the buffer layer having an acicular structure, a compound semiconductor layer disposed on the buffer layer to planarize the uneven structure, and a plurality of voids defined between the substrate and the compound semiconductor layer, and a method for manufacturing the same. Thus, since the acicular structure disposed on the uneven structure of the substrate forms the voids on an interface between the substrate and the single crystal GaN layer to relax a stress due to a lattice mismatch and intercept propagation of a breakdown potential, a warpage characteristic of the grown single crystal GaN layer may be reduced, as well as, crystallinity may be improved. | 05-05-2011 |
20110220874 | Inorganic Bulk Multijunction Materials and Processes for Preparing the Same - A nanostructured composite material comprising semiconductor nanocrystals in a crystalline semiconductor matrix. Suitable nanocrystals include silicon, germanium, and silicon-germanium alloys, and lead salts such as PbS, PbSe, and PbTe. Suitable crystalline semiconductor matrix materials include Si and silicon-germanium alloys. A process for making the nanostructured composite materials. Devices comprising nanostructured composite materials. | 09-15-2011 |
20110266522 | Semiconductor device - A semiconductor device may reduce a dislocation density and tensile stress by forming a plurality of interlayers between neighboring clad layers. The semiconductor device may include a plurality of clad layers on a substrate and a plurality of interlayers between neighboring clad layers. | 11-03-2011 |
20110272672 | Long Wavelength Infrared Superlattice - An embodiment of the present invention improves the fabrication and operational characteristics of a type-II superlattice material. Layers of indium arsenide and gallium antimonide comprise the bulk of the superlattice structure. One or more layers of indium antimonide are added to unit cells of the superlattice to provide a further degree of freedom in the design for adjusting the effective bandgap energy of the superlattice. One or more layers of gallium arsenide are added to unit cells of the superlattice to counterbalance the crystal lattice strain forces introduced by the aforementioned indium antimonide layers. | 11-10-2011 |
20120001153 | PULSED GROWTH OF CATALYST-FREE GROWTH OF GaN NANOWIRES AND APPLICATION IN GROUP III NITRIDE SEMICONDUCTOR BULK MATERIAL - Exemplary embodiments provide semiconductor devices including high-quality (i.e., defect free) group III-N nanowires and uniform group III-N nanowire arrays as well as their scalable processes for manufacturing, where the position, orientation, cross-sectional features, length and the crystallinity of each nanowire can be precisely controlled. A pulsed growth mode can be used to fabricate the disclosed group III-N nanowires and/or nanowire arrays providing a uniform length of about 10 nm to about 1000 microns with constant cross-sectional features including an exemplary diameter of about 10-1000 nm. In addition, high-quality GaN substrate structures can be formed by coalescing the plurality of GaN nanowires and/or nanowire arrays to facilitate the fabrication of visible LEDs and lasers. Furthermore, core-shell nanowire/MQW active structures can be formed by a core-shell growth on the nonpolar sidewalls of each nanowire. | 01-05-2012 |
20120007050 | METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE HAVING A GROUP-III NITRIDE SUPERLATTICE LAYER ON A SILICON SUBSTRATE - Provided is a semiconductor device containing a silicon single crystal substrate | 01-12-2012 |
20120091435 | EPITAXIAL SUBSTRATE FOR ELECTRONIC DEVICE AND METHOD OF PRODUCING THE SAME - An epitaxial substrate for electronic devices is provided, which can improve vertical breakdown voltage and provides a method of producing the same. | 04-19-2012 |
20120187374 | Semiconductor Device - According to example embodiments, a semiconductor device includes a first layer and second layer. The first layer includes a nitride semiconductor doped with a first type dopant. The second layer is below the first layer and includes a high concentration layer. The high concentration layer includes the nitride semiconductor doped with the first type dopant and has a doping concentration higher than a doping concentration of the first layer. | 07-26-2012 |
20120205625 | (Al, In, Ga, B)N DEVICE STRUCTURES ON A PATTERNED SUBSTRATE - A nitride light emitting diode, on a patterned substrate, comprising a nitride interlayer having at least two periods of alternating layers of In | 08-16-2012 |
20120273759 | EPITAXIAL SUBSTRATE FOR ELECTRONIC DEVICE AND METHOD OF PRODUCING THE SAME - An epitaxial substrate for an electronic device, in which a lateral direction of the substrate is defined as a main current conducting direction and a warp configuration of the epitaxial substrate is adequately controlled, as well as a method of producing the epitaxial substrate. Specifically, the epitaxial substrate for an electron device, including: a Si single crystal substrate; and a Group III nitride laminated body formed by epitaxially growing plural Group III nitride layers on the Si single crystal substrate, wherein a lateral direction of the epitaxial substrate is defined as a main current conducting direction, is characterized in that the Si single crystal substrate is a p-type substrate having a specific resistance value of not larger than 0.01 Ω·cm. | 11-01-2012 |
20130043459 | Long Wavelength Infrared Superlattice - An embodiment of the present invention improves the fabrication and operational characteristics of a type-II superlattice material. Layers of indium arsenide and gallium antimonide comprise the bulk of the superlattice structure. One or more layers of indium antimonide are added to unit cells of the superlattice to provide a further degree of freedom in the design for adjusting the effective bandgap energy of the superlattice. One or more layers of gallium arsenide antimonide are added to unit cells of the superlattice to counterbalance the crystal lattice strain forces introduced by the aforementioned indium antimonide layers. | 02-21-2013 |
20130140525 | GALLIUM NITRIDE GROWTH METHOD ON SILICON SUBSTRATE - A semiconductor structure includes a silicon substrate; more than one bulk layer of group-III/group-V (III-V) compound semiconductor atop the silicon substrate; and each bulk layer of the group III-V compound is separated by an interlayer. | 06-06-2013 |
20130175501 | Pulsed Growth of Catalyst-Free Growth of GaN Nanowires and Application in Group III Nitride Semiconductor Bulk Material - Exemplary embodiments provide semiconductor devices including high-quality (i.e., defect free) group III-N nanowires and uniform group III-N nanowire arrays as well as their scalable processes for manufacturing, where the position, orientation, cross-sectional features, length and the crystallinity of each nanowire can be precisely controlled. A pulsed growth mode can be used to fabricate the disclosed group III-N nanowires and/or nanowire arrays providing a uniform length of about 10 nm to about 1000 microns with constant cross-sectional features including an exemplary diameter of about 10-1000 nm. In addition, high-quality GaN substrate structures can be formed by coalescing the plurality of GaN nanowires and/or nanowire arrays to facilitate the fabrication of visible LEDs and lasers. Furthermore, core-shell nanowire/MQW active structures can be formed by a core-shell growth on the nonpolar sidewalls of each nanowire. | 07-11-2013 |
20140001439 | Graded Aluminum-Gallium-Nitride and Superlattice Buffer Layer for III-V Nitride Layer on Silicon Substrate | 01-02-2014 |
20140042391 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTORING THE SAME - A semiconductor device includes a first coalescent layer, a second coalescent layer, a nitride stacked structure on the second coalescent layer, and a third layer between the first and second coalescent layers. The first coalescent layer includes a plurality of formations that are partially merged, and the third layer is disposed on the formations to allow a first type of stress to be generated in an area which includes the first coalescent layer and a second type of stress to be generated in an area which includes the second coalescent layer. | 02-13-2014 |
20140070167 | Solid State Cloaking for Electrical Charge Carrier Mobility Control - An electrical mobility-controlled material includes a solid state host material having a controllable Fermi energy level and electrical charge carriers with a charge carrier mobility. At least one Fermi level energy at which a peak in charge carrier mobility is to occur is prespecified for the host material. A plurality of particles are distributed in the host material, with at least one particle disposed with an effective mass and a radius that minimize scattering of the electrical charge carriers for the at least one prespecified Fermi level energy of peak charge carrier mobility. The minimized scattering of electrical charge carriers produces the peak charge carrier mobility only at the at least one prespecified Fermi level energy, set by the particle effective mass and radius, the charge carrier mobility being less than the peak charge carrier mobility at Fermi level energies other than the at least one prespecified Fermi level energy. | 03-13-2014 |
20140117311 | SEMICONDUCTOR STRUCTURE HAVING NANOCRYSTALLINE CORE AND NANOCRYSTALLINE SHELL PAIRING WITH COMPOSITIONAL TRANSITION LAYER - Semiconductor structures having a nanocrystalline core and nanocrystalline shell pairing compositional transition layers are described. In an example, a semiconductor structure includes a nanocrystalline core composed of a first semiconductor material. A nanocrystalline shell composed of a second semiconductor material surrounds the nanocrystalline core. A compositional transition layer is disposed between, and in contact with, the nanocrystalline core and nanocrystalline shell and has a composition intermediate to the first and second semiconductor materials. In another example, a semiconductor structure includes a nanocrystalline core composed of a first semiconductor material. A nanocrystalline shell composed of a second semiconductor material surrounds the nanocrystalline core. A nanocrystalline outer shell surrounds the nanocrystalline shell and is composed of a third semiconductor material. A compositional transition layer is disposed between, and in contact with, the nanocrystalline shell and the nanocrystalline outer shell and has a composition intermediate to the second and third semiconductor materials. | 05-01-2014 |
20140131659 | Gallium Nitride Devices With Aluminum Nitride Intermediate Layer - The invention provides semiconductor materials including a gallium nitride material layer formed on a silicon substrate and methods to form the semiconductor materials. The semiconductor materials include a transition layer formed between the silicon substrate and the gallium nitride material layer. The transition layer is compositionally-graded to lower stresses in the gallium nitride material layer which can result from differences in thermal expansion rates between the gallium nitride material and the substrate. The lowering of stresses in the gallium nitride material layer reduces the tendency of cracks to form. Thus, the invention enables the production of semiconductor materials including gallium nitride material layers having few or no cracks. The semiconductor materials may be used in a number of microelectronic and optical applications. | 05-15-2014 |
20140145147 | NITRIDE SEMICONDUCTOR STRUCTURE AND METHOD OF FABRICATING SAME - A nitride semiconductor structure of the present invention is obtained by growing an h- or t-BN thin film ( | 05-29-2014 |
20140183450 | CATALYST FREE SYNTHESIS OF VERTICALLY ALIGNED CNTs ON SiNW ARRAYS - The present invention discloses novel one dimensional, direct nano-heterojunctions of vertically aligned silicon nanowires (SiNW)-carbon nano tube (CNT) arrays with ultra-low turn-on field useful in single electronic devices. The invention further discloses catalyst free chemical vapor deposition (CVD) route for synthesis of one dimensional, direct nano-heterojunctions of vertically aligned SiNW-CNT arrays. | 07-03-2014 |
20140209862 | GROUP III NITRIDE EPITAXIAL SUBSTRATE AND METHOD FOR MANUFACTURING THE SAME - Provided is a Group III nitride epitaxial substrate that can suppress the occurrence of breakage during a device formation process and a method for manufacturing the same. A Group III nitride epitaxial substrate according to the present invention includes a Si substrate, an initial layer in contact with the Si substrate, and a superlattice laminate, formed on the initial layer, including a plurality of sets of laminates, each of the laminates including, in order, a first layer made of AlGaN with an Al composition ratio greater than 0.5 and 1 or less and a second layer made of AlGaN with an Al composition ratio greater than 0 and 0.5 or less. The Al composition ratio of the second layer progressively decreases with distance from the substrate. | 07-31-2014 |
20140306183 | METHOD FOR MANUFACTURING FUNCTIONAL MATERIAL AND ELECTRONIC COMPONENT - A method for manufacturing a functional material including a porous metal complex with nanoparticles included therein, the method including a configuration of adding more than one particle constituent raw material constituting the nanoparticles and a porous metal complex to a solvent, and then synthesizing nanoparticles included in the porous metal complex by heating to a desired temperature. In addition, provided is an electronic component including an electronic component element using a functional material including a porous metal complex with nanoparticles included therein. | 10-16-2014 |
20140332756 | NITRIDE SEMICONDUCTOR LIGHT-EMITTING DEVICE AND METHOD OF MANUFACTURING THE SAME - A nitride semiconductor light-emitting device is formed of an n-type nitride semiconductor layer, a trigger layer, a V-pit expanding layer, a light-emitting layer, and a p-type nitride semiconductor layer provided in this order. The light-emitting layer has a V-pit formed therein. The trigger layer is made of a nitride semiconductor material having a lattice constant different from that of a material that forms an upper surface of the n-type nitride semiconductor layer. The V-pit expanding layer is made of a nitride semiconductor material having a lattice constant substantially identical to that of the material that forms the upper surface of the n-type nitride semiconductor layer, and the V-pit expanding layer has a thickness of 5 nm or more and 5000 nm or less. | 11-13-2014 |
20140353586 | SEMICONDUCTOR ELEMENT AND METHOD FOR PRODUCING THE SAME - A method for producing a semiconductor element includes a step of forming a multiple quantum well in which a GaSb layer and an InAs layer are alternately stacked on a GaSb substrate by MOVPE, wherein, in the step of forming a multiple quantum well, an InSb film is formed on at least one of a lower-surface side and an upper-surface side of the InAs layer so as to be in contact with the InAs layer. | 12-04-2014 |
20140353587 | EPITAXIAL WAFER FOR HETEROJUNCTION TYPE FIELD EFFECT TRANSISTOR - An epitaxial wafer for a heterojunction type FET includes an AlN primary layer, a stepwisely composition-graded buffer layer structure, a superlattice buffer layer structure, a GaN channel layer, and a nitride semiconductor electron supply layer, which are sequentially provided on a Si substrate, the stepwisely composition-graded buffer layer structure including a plurality of AlGaN buffer layers provided on each other such that an Al composition ratio is sequentially reduced, an uppermost layer thereof having a composition of AlxGa1—xN (012-04-2014 | |
20150041762 | Transistor Having Graphene Base - A transistor device having a graphene base for the transport of electrons into a collector is provided. The transistor consists of a heterostructure comprising an electron emitter, an electron collector, and a graphene material base layer consisting of one or more sheets of graphene situated between the emitter and the collector. The transistor also can further include an emitter transition layer at the emitter interface with the base and/or a collector transition layer at the base interface with the collector. The electrons injected into the graphene material base layer can be “hot electrons” having an energy E substantially greater than E | 02-12-2015 |
20150060765 | SEMICONDUCTOR DEVICE - A semiconductor device includes a superlattice buffer layer formed on a substrate. A first semiconductor layer is formed by a nitride semiconductor on the superlattice buffer layer. A second semiconductor layer is formed by a nitride semiconductor on the first semiconductor layer. A gate electrode, a source electrode and a drain electrode are formed on the second semiconductor layer. The superlattice buffer layer is forced by alternately and periodically laminating a first superlattice formation layer, and a second superlattice formation layer. The first super lattice formation layer is formed by Al | 03-05-2015 |
20150115223 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - Disclosed are semiconductor devices and methods of manufacturing the same. The semiconductor device includes: a first conductive type semiconductor layer including a first lower conductive type semiconductor layer and a first upper conductive type semiconductor layer; a V-pit passing through at least one portion of the first upper conductive type semiconductor layer; a second conductive type semiconductor layer placed over the first conductive type semiconductor and filling the V-pit; and an active layer interposed between the first and second conductive type semiconductor layers with the V-pit passing through the active layer. The first upper conductive type semiconductor layer has a higher defect density than the first lower conductive type semiconductor layer and includes a V-pit generation layer comprising a starting point of the V-pit. The semiconductor device includes the V-pits having a large size and a high density to efficiently preventing damage to the semiconductor device due to electrostatic discharge. | 04-30-2015 |
20150357414 | SEMICONDUCTOR DEVICES WITH ENHANCED DETERMINISTIC DOPING AND RELATED METHODS - A method for making a semiconductor device may include forming a plurality of stacked groups of layers on a semiconductor substrate, with each group of layers including a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. The method may further include implanting a dopant in the semiconductor substrate beneath the plurality of stacked groups of layers in at least one localized region, and performing an anneal of the plurality of stacked groups of layers and semiconductor substrate and with the plurality of stacked groups of layers vertically and horizontally constraining the dopant in the at least one localized region. | 12-10-2015 |
20150357419 | P-DOPING OF GROUP-III-NITRIDE BUFFER LAYER STRUCTURE ON A HETEROSUBSTRATE - An epitaxial group-ill-nitride buffer-layer structure is provided on a heterosubstrate, wherein the buffer-layer structure has at least one stress-management layer sequence including an interlayer structure arranged between and adjacent to a first and a second group-ill-nitride layer, wherein the interlayer structure comprises a group-ill-nitride interlayer material having a larger band gap than the materials of the first and second group-ill-nitride layers, and wherein a p-type-dopant-concentration profile drops, starting from at least 1×1018 cm-3, by at least a factor of two in transition from the interlayer structure to the first and second group-ill-nitride layers. | 12-10-2015 |
20150364547 | HIGH-MOBILITY SEMICONDUCTOR HETEROSTRUCTURES - A layer structure and method of fabrication of a semiconductor heterostructure containing a two-dimensional electron gas (2DEG), two-dimensional hole gas (2DHG), or a two-dimensional electron/hole gas (2DEHG). The heterostructure contains a quantum well layer with 2DEG, 2DHG, or 2DEHG embedded between two doped charge reservoir layers and at least two remote charge reservoir layers. Such scheme allows reducing the number of scattering ions in the proximity of the quantum well as well a possibility for a symmetric potential for the electron or hole wavefunction in the quantum well, leading to significant improvement in carrier mobility in a broad range of 2DEG or 2DHG concentration in the quantum well. Embodiments of the invention may be applied to the fabrication of galvano-magnetic sensors, HEMT, pHEMT, and MESFET devices. | 12-17-2015 |
20150372174 | SEMICONDUCTOR DEVICE - An infrared photodiode that is a semiconductor device includes a substrate, a buffer layer formed of GaSb, and an absorption layer including a multiple quantum well structure. The multiple quantum well structure includes a stack of unit structures each including a plurality of component layers. Each unit structure includes a first component layer formed of InAs | 12-24-2015 |
20160049502 | HETEROJUNCTION BIPOLAR TRANSISTOR WITH BLOCKING LAYER STRUCTURE - Provided is a heterojunction bipolar transistor (HBT), including a GaAs substrate; a subcollector layer stacked on the GaAs substrate, wherein a part of or all of the subcollector layer is formed by N-type group III-V semiconductors doped by at least Te and/or Se; a blocking layer structure directly or indirectly stacked on the subcollector layer, and formed by N-type group III-V semiconductors doped by at least group IV elements, a collector layer stacked on the blocking layer structure, and formed by N-type group III-V semiconductors; a base layer stacked on the collector layer, and formed by P-type group III-V semiconductors; an emitter layer stacked on the base layer and formed by N-type group III-V semiconductors; an emitter cap layer stacked on the emitter layer and formed by N-type group III-V semiconductors; and an ohmic contact layer stacked on the emitter cap layer and formed by N-type group III-V semiconductors. | 02-18-2016 |
20160093702 | Ohmic Contact to Semiconductor - An ohmic contact to a semiconductor layer including a heterostructure barrier layer and a metal layer adjacent to the heterostructure barrier layer is provided. The heterostructure barrier layer can form a two dimensional free carrier gas for the contact at a heterointerface of the heterostructure barrier layer and the semiconductor layer. The metal layer is configured to form a contact with the two dimensional free carrier gas. | 03-31-2016 |
20160111273 | SEMICONDUCTOR SUBSTRATE, SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SEMICONDUCTOR DEVICE - A semiconductor substrate having a silicon-based substrate, a buffer layer provided on the silicon-based substrate and made of a nitride semiconductor containing boron, and an operation layer formed on the buffer layer, wherein a concentration of boron in the buffer layer gradually decreasing toward a side of the operation layer from a side of the silicon-based substrate. Thereby, the semiconductor substrate in which the buffer layer contains boron sufficient to obtain a dislocation suppression effect and boron is not diffused to the operation layer is provided. | 04-21-2016 |
20160197146 | SUPERLATTICE MATERIALS AND APPLICATIONS | 07-07-2016 |