Virage Logic Corporation
Virage Logic Corporation Patent applications | ||
Patent application number | Title | Published |
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20110013444 | LOW LEAKAGE ROM ARCHITECURE - A Read only memory (ROM) with minimum leakage includes a ROM array including a first transistor, wherein a drain, a source, a gate, and a bulk of the first transistor is electrically connected to a logic zero in the idle state for ensuring zero junction and sub-threshold leakage current. The drain of the first transistor is electrically connected to a main bit line through a second transistor. The second transistor includes a gate, electrically connected to a first decoding circuit, a drain, electrically connected to the main bit line. A first reference bit line is electrically connected to a drain of a third transistor, wherein gate of the third transistor is electrically connected to a second decoding circuit for generating a stop read signal. A second reference bit line, electrically connected to the first decoding circuit through a first sensing unit for generating a stop pre-charge signal. | 01-20-2011 |
20100050135 | VARIOUS METHODS AND APPARATUSES FOR EFFECTIVE YIELD ENHANCEMENT OF GOOD CHIP DIES HAVING MEMORIES PER WAFER - A method and apparatus are described in which an optimal configuration of memory instances is determined. The optimal configuration of memory instances to be fabricated with built-in repair capacity and memory instances that are non-repairable may provide a maximum number of good chip dies per wafer. An amount of memory instances to be fabricated with built-in repair capacity as well as a remaining amount of memory instances to be fabricated without any built-in repair components in the integrated circuit design is determined relative to achieving the maximum number of good chip dies per wafer for a given defect density and wafer area. The amount of good dies produced per fabricated wafer for a populated amount of memories with built-in repair components is determined to be between an amount established by a minimum limit for the die area up to the amount established by a maximum limit for the die area. | 02-25-2010 |
20090106716 | VARIOUS METHODS AND APPARATUSES FOR MEMORY MODELING USING A STRUCTURAL PRIMITIVE VERIFICATION FOR MEMORY COMPILERS - A structural primitive verification tool for memory compilers is described. A first set of memory structural primitives are supplied by a designer by filling in fields of a presented user interface. The first set of structural primitives describe certain physical layout features of a proposed memory array in an integrated circuit. A first model of a memory instance derived from the first set of memory structural primitives supplied by the designer is compared to a second model of a memory instance derived from a memory layout file from a memory compiler under-test. The first model is verified against the second model to verify to an integrity of the first set of memory structural primitives supplied by the designer compared to the memory layout file derived from a second set of memory structural primitives configuring that memory instance from the memory compiler. | 04-23-2009 |