TAIWAN SEMICONDUTOR MANUFACTURING CO., LTD. Patent applications |
Patent application number | Title | Published |
20150194383 | AIR GAP FORMING TECHNIQUES BASED ON ANODIC ALUMINA FOR INTERCONNECT STRUCTURES - An aluminum (Al) layer is formed over a semiconductor substrate. A selective portion of the Al layer is removed to form openings. The Al layer is anodized to obtain an alumina dielectric layer with a plurality of pores substantially perpendicular to a surface of the semiconductor substrate. The openings are filled with a conductive interconnect material. The pores are widened to form air gaps and a top etch stop layer is formed over the alumina dielectric layer. | 07-09-2015 |
20150143319 | DIFFERENT SCALING RATIO IN FEOL / MOL/ BEOL - The present disclosure relates to a method of generating a scaled integrated chip design by scaling a FEOL and a BEOL of an original IC design at different scaling ratios, and an associated apparatus. In some embodiments, the method is performed by forming an original integrated chip (IC) design that is a graphical representation of an integrated chip. The original IC design has a front-end-of-the-line (FEOL) section, a back-end-of-the-line (BEOL) section, and a middle-of-the-line (MOL) section that is disposed between the FEOL and BEOL sections. A scaled integrated chip design is formed by scaling (i.e., shrinking) the FEOL section and the BEOL section of the original integrated chip design at different scaling ratios, and by scaling different design layers within the MOL section at different scaling ratios to avoid misalignment errors between the FEOL section and the BEOL section. | 05-21-2015 |
20100155849 | TRANSISTORS WITH METAL GATE AND METHODS FOR FORMING THE SAME - A semiconductor device includes at least one first gate dielectric layer over a substrate. A first transition-metal oxycarbide (MC | 06-24-2010 |