SYNOPSYS, INC. Patent applications |
Patent application number | Title | Published |
20160087099 | FINFET WITH HETEROJUNCTION AND IMPROVED CHANNEL CONTROL - Roughly described, a computer program product describes a transistor with a fin, a fin support, a gate, and a gate dielectric. The fin includes a first crystalline semiconductor material which includes a channel region of the transistor between a source region of the first transistor and a drain region of the transistor. The fin is on a fin support. The fin support includes a second crystalline semiconductor material different from the first crystalline semiconductor material. The first crystalline semiconductor material of the fin and the second crystalline semiconductor material of the fin support form a first heterojunction in between. A gate, gate dielectric, and/or isolation dielectric can be positioned to improve control within the channel. | 03-24-2016 |
20160070833 | EXPONENTIALLY FITTED APPROXIMATION FOR ANISOTROPIC SEMICONDUCTOR EQUATIONS - Roughly described, a method for determining characteristics of a body by simulation, useful in analyzing semiconductor devices, includes imposing a Delaunay mesh on a simulated body to be modeled, determining a system of node equations describing generation and flux of a set of at least a first physical quantity at each node in the mesh, and numerically solving the system of node equations to identify the physical quantities in the set at each node in the mesh, where the flux of the first physical quantity in the body, as represented in the node equations, is anisotropic. The method does not impose any limitation on the geometry of the device, on mesh elements, or on the orientation of the anisotropy. | 03-10-2016 |
20160063163 | ARRAYS WITH COMPACT SERIES CONNECTION FOR VERTICAL NANOWIRES REALIZATIONS - An integrated circuit design tool includes a functional cell library. An entry in the cell library comprises a specification of the cell. Entries in the cell library including specifications of particular cells in a computer executable language. At least one entry in the cell library comprising a specification of a cell including a plurality of transistors and an interconnect. At least two transistors in the plurality are in series via at least the interconnect. The transistors and the interconnect can be vertically oriented to support vertical current through a vertical channel relative to the substrate. | 03-03-2016 |
20160063162 | SYSTEM AND METHOD USING PASS/FAIL TEST RESULTS TO PRIORITIZE ELECTRONIC DESIGN VERIFICATION REVIEW - A system and method are provided that use pass/fail test results to prioritize electronic design verification review issues. It may prioritize either generated properties or code coverage items or both. Thus issues, whether generated properties or code coverage items, that have never been violated in any passing or failing test may be given highest priority for review, while those that have been violated in a failing test but are always valid in passing tests may be given lower priority. Still further, where end-users have marked one or more properties or code coverage items as already-reviewed, the method will give these already-reviewed issues the lowest priority. As a result, both properties and code coverage items may be generated together in a progressive manner starting earlier in development and significant duplication of effort is avoided. | 03-03-2016 |
20160043174 | METHODS FOR MANUFACTURING INTEGRATED CIRCUIT DEVICES HAVING FEATURES WITH REDUCED EDGE CURVATURE - A structure, such as an integrated circuit device, is described that includes a line of material with critical dimensions which vary within a distribution substantially less than that of a mask element, such as a patterned resist element, used in etching the line. Techniques are described for processing a line of crystalline phase material which has already been etched using the mask element, in a manner which straightens an etched sidewall surface of the line. The straightened sidewall surface does not carry the sidewall surface variations introduced by photolithographic processes, or other patterning processes, involved in forming the mask element and etching the line. | 02-11-2016 |
20160043083 | FINFET CELL ARCHITECTURE WITH POWER TRACES - A finFET block architecture suitable for use of a standard cell library, is based on an arrangement including a first set of semiconductor fins in a first region of the substrate having a first conductivity type, and a second set of semiconductor fins in a second region of the substrate, the second region having a second conductivity type. A patterned gate conductor layer including gate traces in the first and second regions, arranged over channel regions of the first and second sets of semiconductor fins is used for transistor gates. Patterned conductor layers over the gate conductor layer are arranged in orthogonal layout patterns, and can include a plurality of floating power buses over the fins in the first and second regions. | 02-11-2016 |
20160042115 | PATH-BASED FLOORPLAN ANALYSIS - Systems and techniques for computing a timing effort metric are described. According to one definition, the computed timing effort metric indicates a level of difficulty of fixing a timing violation associated with a timing path between two circuit objects in a circuit design layout. | 02-11-2016 |
20160034624 | OPTIMIZING CONSTRAINT SOLVING BY REWRITING AT LEAST ONE BIT-SLICE CONSTRAINT - Methods and apparatuses are described for assigning random values to a set of random variables so that the assigned random values satisfy a set of constraints. A constraint solver can receive a set of constraints that is expected to cause performance problems when the system assigns random values to the set of random variables in a manner that satisfies the set of constraints. For example, modulo constraints and bit-slice constraints can cause the system to perform excessive backtracking when the system attempts to assign random values to the set of random variables in a manner that satisfies the set of constraints. The system can rewrite the set of constraints to obtain a new set of constraints that is expected to reduce and/or avoid the performance problems. The system can then assign random values to the set of random variables based on the new set of constraints. | 02-04-2016 |
20160034620 | LATCH-UP SUPPRESSION AND SUBSTRATE NOISE COUPLING REDUCTION THROUGH A SUBSTRATE BACK-TIE FOR 3D INTEGRATED CIRCUITS - Roughly described, an integrated circuit device has a conductor extending entirely through the substrate, connected on one end to the substrate topside surface and on the other end to the substrate backside surface. In various embodiments the conductor is insulated from all RDL conductors on the backside of the substrate, and/or is insulated from all conductors and device features on any below-adjacent chip in a 3D integrated circuit structure. Methods of fabrication are also described. | 02-04-2016 |
20150370951 | CELLS HAVING TRANSISTORS AND INTERCONNECTS INCLUDING NANOWIRES OR 2D MATERIAL STRIPS - An integrated circuit design tool includes a cell library. The cell library includes entries for a plurality of cells, entries in the cell library including specifications of particular cells in a computer executable language. At least one entry in the cell library can comprise a specification of physical structures and timing parameters of a plurality of transistors and an interconnect; wherein a transistor in the plurality has a channel comprising one or more nanowires or 2D material strips arranged in parallel, and the interconnect comprises one or more nanowires or 2D material strips arranged in parallel and connected to terminals of more than one of the transistors in the plurality of transistors. An integrated circuit including the plurality of transistors and the interconnect is described. | 12-24-2015 |
20150370950 | ARRAY WITH INTERCELL CONDUCTORS INCLUDING NANOWIRES OR 2D MATERIAL STRIPS - An integrated circuit design tool includes a cell library. The cell library includes entries for a plurality of cells, entries in the cell library including specifications of particular cells in a computer executable language. At least one entry in the cell library can comprise a specification of physical structures and timing parameters of an array of circuit cells, the circuit cells including one or more transistors and a cell interconnect terminal; and a conductor configured to connect interconnect terminals of a plurality of the circuit cells in the array, the conductor comprising one or more nanowires or 2D material strips arranged in parallel. An integrated circuit including the array of circuit cells is described. | 12-24-2015 |
20150370949 | NANOWIRE OR 2D MATERIAL STRIPS INTERCONNECTS IN AN INTEGRATED CIRCUIT CELL - An integrated circuit design tool includes a cell library. The cell library includes entries for a plurality of cells, entries in the cell library including specifications of particular cells in a computer executable language. At least one entry in the cell library can comprise a specification of physical structures and timing parameters of a circuit including a first transistor, a second transistor, and an interconnect connecting a terminal of the first transistor to a terminal of the second transistor, the interconnect comprising one or more nanowires or 2D material strips arranged in parallel. An integrated circuit including the circuit is described. | 12-24-2015 |
20150370948 | MEMORY CELLS HAVING TRANSISTORS WITH DIFFERENT NUMBERS OF NANOWIRES OR 2D MATERIAL STRIPS - An integrated circuit design tool includes a cell library. The cell library includes entries for a plurality of cells, entries in the cell library including specifications of particular cells in a computer executable language. At least one entry in the cell library can comprise a specification of physical structures and timing parameters of a memory cell including a plurality of transistors, at least some of the transistors in the plurality having channels comprising respective sets of one or more nanowires or 2D material strips, and wherein the channel of one of the transistors in the plurality has a different number of nanowires or 2D material strips than a channel of another transistor in the plurality. An integrated circuit including the memory cell is described. | 12-24-2015 |
20150370947 | DESIGN TOOLS FOR INTEGRATED CIRCUIT COMPONENTS INCLUDING NANOWIRES AND 2D MATERIAL STRIPS - An integrated circuit design tool includes a cell library. An entry in the cell library comprises a specification of the cell including a first transistor and a second transistor. The first transistor can include a first set of nanowires or 2D material strips arranged in parallel to form a channel structure, and a gate conductor disposed across the first set of nanowires or 2D material strips. The second transistor can include a second set of nanowires or 2D material strips arranged in parallel to form a channel structure, and a gate conductor disposed across the first set of nanowires or 2D material strips. The number of nanowires or 2D material strips in the first set can be different from the number of nanowires or 2D material strips in the second set, so that the drive power of the individual transistors can be set with finer granularity. | 12-24-2015 |
20150369855 | EVALUATION OF THERMAL INSTABILITY STRESS TESTING - A circuit is powered through a transistor whose thermal instability behavior is to be evaluated in a stress test. The transistor is stressed during a stress phase of the stress test with a sensor circuit powered off and the Vds of the transistor is zero. The sensor circuit is powered on through the transistor during an evaluate phase of the stress test. | 12-24-2015 |
20150339802 | RESOLUTION ENHANCEMENT TECHNIQUES BASED ON HOLOGRAPHIC IMAGING TECHNOLOGY - Systems and techniques for performing resolution enhancement on target patterns based on holographic imaging technique (HIT) are described. During operation, an electronic design automation (EDA) tool can compute an in-line hologram of the target patterns based on parameters associated with a photolithography process that is used in a semiconductor manufacturing process, wherein the semiconductor manufacturing process is to be used for printing the target patterns on a semiconductor wafer. Next, the EDA tool can determine the mask patterns based on the in-line hologram. | 11-26-2015 |
20150324511 | FLOATING METAL FILL CAPACITANCE CALCULATION - A design layout is obtained that includes floating fill shapes and signal shapes. Capacitance of the signal shapes is calculated. A simple model is used to calculate a first subset of fill shapes which contribute capacitance to the signal shapes. A capacitance model selected to meet an acceptable error level using minimum computational requirements is then selected from a set of capacitance models. The selected capacitance model is then used to extract the capacitance contribution from the first subset of fill shapes. A second subset of fill shapes is then created based on the extracted capacitance values, and if the estimated capacitance contribution is significant, the capacitance of the second subset extracted using the selected capacitance model. Additional iterations are performed for additional signal shapes. | 11-12-2015 |
20150318845 | Multi-Bit Standard Cells For Consolidating Transistors With Selective Sourcing - A method for designing a standard cell, e.g. a multi-bit flip-flop, can include identifying a first set of transistors. This first set functions to source power or ground to circuits of the standard cell. A second set of transistors can be determined and correlated. This second set forms at least part of the first set of transistors. Each correlated group in the second set of transistors receives identical signals, e.g. scan enable, reset, and/or set signals, and provides a same sourcing. A third set of transistors can then be created. This third set has fewer transistors than the second set. The second set of transistors can be deleted in the standard cell. The third set of transistors can be connected to the circuits of the standard cell. This method can significantly extend circuit consolidation to improve the area benefit of multi-bit standard cells. | 11-05-2015 |
20150317420 | 3D TCAD SIMULATION - A first representation of an integrated circuit undergoing processing is transformed into a second representation. The second representation including additional dopants relative to the first representation. The transformation generates a three-dimensional dopant distribution from adding a first dopant under a first set of process conditions with a mask, by combining the two-dimensional lateral profile of the dopant with the one-dimensional depth profile of the dopant. The one-dimensional depth profile of the dopant is retrieved from a database storing selected results from earlier process simulation of the first addition of the first dopant under the first set of process conditions. The two-dimensional lateral dopant profile from adding the first dopant under the first set of process conditions with a first mask corresponding to the first dopant, is generated by convolving the mask with a lateral diffusion function, or from at least one solution to the 2D diffusion equation without convolution. | 11-05-2015 |
20150303196 | FINFET CELL ARCHITECTURE WITH POWER TRACES - A finFET block architecture suitable for use of a standard cell library, is based on an arrangement including a first set of semiconductor fins in a first region of the substrate having a first conductivity type, and a second set of semiconductor fins in a second region of the substrate, the second region having a second conductivity type. A patterned gate conductor layer including gate traces in the first and second regions, arranged over channel regions of the first and second sets of semiconductor fins is used for transistor gates. Patterned conductor layers over the gate conductor layer are arranged in orthogonal layout patterns, and can include a plurality of floating power buses over the fins in the first and second regions. | 10-22-2015 |
20150302132 | MASK3D MODEL ACCURACY ENHANCEMENT FOR SMALL FEATURE COUPLING EFFECT - A method and apparatus of a novel full chip edge-based mask three-dimensional (3D) model for performing photolithography simulation with consideration for edge coupling effect is described. The method receives a mask design layout in order to perform mask topography effect modeling. The method generates scaling parameters for edge coupling effects. Each scaling parameter has an associated combination of feature width and space. The sum of feature width and space associated with at least one scaling parameter is less than a minimum pitch. The method applies a thick mask model that includes several edge-based kernels to the mask design layout to create a mask 3D residual. To apply the thick mask model to the mask design layout, the method updates the edge-based kernels with the scaling parameters. | 10-22-2015 |
20150295021 | INTEGRATED CIRCUIT DEVICES HAVING FEATURES WITH REDUCED EDGE CURVATURE AND METHODS FOR MANUFACTURING THE SAME - A structure such as an integrated circuit device is described having a line of material with critical dimensions which vary within a distribution substantially less than that of a mask element, such as a patterned resist element, used in manufacturing the line of material. | 10-15-2015 |
20150294055 | SYSTEMS AND METHODS FOR INCREASING DEBUGGING VISIBILITY OF PROTOTYPING SYSTEMS - User's register transfer level (RTL) design is analyzed and instrumented so that signals of interest are preserved and can be located in the netlist after synthesis. Then, the user's original flow of RTL synthesis and design partition is performed. The output is analyzed to locate the signals of interest. Latches are selectively inserted to the netlist to ensure that signal values can be accessed at runtime. After that, a place and route (P&R) process is performed, and the outputs are analyzed to correlate signal names to registers (flip-flops and latches) or memory blocks locations is field programmable gate array (FPGA) devices. A correlation database is built and kept for runtime use. During runtime, a software component may be provided on a workstation for the user to query signal values corresponding to RTL hierarchical signal names. | 10-15-2015 |
20150279441 | MOST ACTIVATED MEMORY PORTION HANDLING - Activation of portions of a memory is tracked to allow an affected portion of the memory to be refreshed before it is corrupted by multiple activations. An address for the accessed portion of memory, called the aggressor row, is compared to addresses stored in a content addressable memory (CAM). If the address is not already stored in the CAM, it is stored, casting out another address if necessary, and a count based on an Others value is stored in the CAM with the address. If the address is already stored in the CAM, its associated count is incremented. If a count associated with an address exceeds a threshold based on a maximum activation count, another portion of memory, such as a victim row of memory adjacent to the aggressor row of memory, is refreshed, and the count reset. | 10-01-2015 |
20150269301 | GOAL-BASED CELL PARTITIONING IN THE PRESENCE OF OBSTACLES - Systems and techniques are provided to correctly handle obstacles during cell partitioning, thereby preventing electronic design automation (EDA) tools from being subject to performance penalties during subsequent operations that are performed by the EDA tools on the cell partitions. | 09-24-2015 |
20150269298 | NETWORK FLOW BASED FRAMEWORK FOR CLOCK TREE OPTIMIZATION - Systems and techniques for clock tree optimization are described. An electronic design automation (EDA) tool can receive a graph that represents a circuit design, wherein a set of trees in the graph can correspond to a set of clock trees in the circuit design. For each tree in the set of trees, a set of leaf node pairs can be determined. Next, for each leaf node pair, a flow can be created in the graph between the two leaf nodes in the leaf node pair. Aggregate flows can be determined for edges in the graph based on the flows. A set of edges based on the aggregate flows can be identified, and then circuitry corresponding to the set of edges can be identified. Next, the identified circuitry in the circuit design can be optimized. | 09-24-2015 |
20150261894 | FINFET CELL ARCHITECTURE WITH INSULATOR STRUCTURE - A finFET block architecture includes a first set of semiconductor fins having a first conductivity type, and a second set of semiconductor fins having a second conductivity type. An inter-block insulator is placed between outer fins of the first and second sets. A patterned gate conductor layer includes a first plurality of gate traces extending across the set of fins in the first block without crossing the inter-block insulator, and a second plurality of gate traces extending across the set of fins in the second block without crossing the inter-block insulator. Patterned conductor layers over the gate conductor layer are arranged in orthogonal layout patterns, and include an inter-block connector arranged to connect gate traces in the first and second blocks. | 09-17-2015 |
20150256171 | HIGH VOLTAGE SWITCH WITH TWO OR MORE OUTPUTS - Embodiments relate to a single multi-output high-voltage (HV) switch configured to pass multiple HV signals in semiconductor integrated circuits, such as a memory device. By utilizing a single HV switch that shares multiple components, area is reduced and fewer numbers of transistor devices are used to reduce cost. The shared components are selected such that the HV switch configuration provides functionality similar to traditional multiple HV switch configurations. Specifically, common logic shared across different branches of the single HV switch enables the single HV switch to provide multiple HV signals. | 09-10-2015 |
20150242541 | ASSERTION EXTRACTION FROM DESIGN AND ITS SIGNAL TRACES - Groups of signals in an electronic design for which interesting assertions, such as assert, assume and cover properties, can be generated are identified. A sliding temporal window of fixed depth is used to sample unique present and past value combinations of signals in the signals groups generated by one or more simulations or emulations. The values of signals in the signal groups are organized into truth tables. Minimal functional relations are extracted from the truth tables, using techniques similar to those for synthesis of partial finite memory machines from traces, and used to generate assertions. The assertions are filtered using a cost function and pertinence heuristics, and a formal verification tool used to prune unreachable properties and generate traces for reachable cover properties. Syntactically correct assert, assume and cover property statements for the generated properties are instantiated and packaged into a file suitable for further simulation or emulation or formal verification. | 08-27-2015 |
20150227670 | IDENTIFYING LAYOUT PATTERN CANDIDATES - A method, system or computer usable program product for automatically identifying layout pattern candidates in selected regions for use in analyzing semiconductor device performance issues including identifying a set of target regions and a set of reference regions from a design layout; utilizing a processor to generate a reference baseline of layout patterns from the set of reference regions; utilizing the processor to compare a frequency profile of layout patterns in the set of target regions to a frequency profile of layout patterns in the reference baseline; and based on the comparison, utilizing the processor to identify candidate layout patterns from the set of target regions for further analysis. | 08-13-2015 |
20150227646 | PLACEMENT OF SINGLE-BIT AND MULTI-BIT FLIP-FLOPS - Technology is disclosed for placement of single-bit flip-flops and multi-bit flip-flops. Single-bit flip-flops with replaced with multi-bit flip-flops and/or relative placement groups of single-bit flip-flops. | 08-13-2015 |
20150220458 | Protection Scheme for Embedded Code - A code protection scheme for controlling access to a memory region in an integrated circuit includes a processor with an instruction pipeline that includes multiple processing stages. A first processing stage receives one or more instructions. A second processing stage receives address information identifying a protected memory region of the memory from the first processing stage and protection information for an identified protected memory region. The protection information indicates a protection state assigned to each protected memory region. Based on the instruction type of the received instruction and the protection information associated with a particular protected memory region, the second processing stage determines whether to enable or disable access to the particular protected memory region by the processor or other external host. | 08-06-2015 |
20150213167 | INVARIANT SHARING TO SPEED UP FORMAL VERIFICATION - Methods and apparatuses are described for sharing inductive invariants while performing formal verification of a circuit design. Specifically, some embodiments assume at least an inductive invariant for a property to be true while proving another property. According to one definition, an inductive invariant of a property is an inductive assertion such that all states that satisfy the inductive assertion also satisfy the property. According to one definition, an inductive assertion describes a set of states that includes all legal initial states of the circuit design and that is closed under a transition relation that models the circuit design. | 07-30-2015 |
20150213159 | METHOD AND APPARATUS FOR AUTOMATIC RELATIVE PLACEMENT GENERATION FOR CLOCK TREES - Methods and apparatuses are disclosed for automatic relative placement of part of a clock tree in the course of generating a placed, routed, and optimized circuit design. | 07-30-2015 |
20150205904 | PLACING TRANSISTORS IN PROXIMITY TO THROUGH-SILICON VIAS - Roughly described, the invention involves ways to characterize, take account of, or take advantage of stresses introduced by TSV's near transistors. The physical relationship between the TSV and nearby transistors can be taken into account when characterizing a circuit. A layout derived without knowledge of the physical relationships between TSV and nearby transistors, can be modified to do so. A macrocell can include both a TSV and nearby transistors, and a simulation model for the macrocell which takes into account physical relationships between the transistors and the TSV. A macrocell can include both a TSV and nearby transistors, one of the transistors being rotated relative to others. An IC can also include a transistor in such proximity to a TSV as to change the carrier mobility in the channel by more than the limit previously thought to define an exclusion zone. | 07-23-2015 |
20150194429 | N-CHANNEL AND P-CHANNEL END-TO-END FINFET CELL ARCHITECTURE WITH RELAXED GATE PITCH - A finFET block architecture uses end-to-end finFET blocks in which the fin lengths are at least twice the contact pitch, whereby there is enough space for interlayer connectors to be placed on the proximal end and the distal end of a given semiconductor fin, and on the gate element on the given semiconductor fin. A first set of semiconductor fins having a first conductivity type and a second set of semiconductor fins having a second conductivity type can be aligned end-to-end. Interlayer connectors can be aligned over corresponding semiconductor fins which connect to gate elements. | 07-09-2015 |
20150162320 | METHOD AND APPARATUS FOR FLOATING OR APPLYING VOLTAGE TO A WELL OF AN INTEGRATED CIRCUIT - In one well bias arrangement, no well bias voltage is applied to the n-well, and no well bias voltage is applied to the p-well. Because no external well bias voltage is applied, the n-well and the p-well are floating, even during operation of the devices in the n-well and the p-well. In another well bias arrangement, the lowest available voltage is not applied to the p-well, such as a ground voltage, or the voltage applied to the n+-doped source region of the n-type transistor in the p-well. This occurs even during operation of the n-type transistor in the p-well. In yet another well bias arrangement, the highest available voltage is not applied to the n-well, such as a supply voltage, or the voltage applied to the p+-doped source region of the p-type transistor in the n-well. This occurs even during operation of the p-type transistor in the n-well. | 06-11-2015 |
20150161302 | INTEGRATED MASK-AWARE LITHOGRAPHY MODELING TO SUPPORT OFF-AXIS ILLUMINATION AND MULTI-TONE MASKS - A method and apparatus of a novel modeling scheme for performing optical lithography simulation for a multi-tone mask with a plurality of mask tones is described. The method generates a transmission function matrix based on a setting of the multi-tone mask. The method applies the transmission function matrix to transform a formula for calculating light intensity from Abbe's form to Hopkins' form while maintaining the accuracy of Abbe's form. The method then computes the light intensity using the transformed formula. | 06-11-2015 |
20150143306 | METHODS FOR FABRICATING HIGH-DENSITY INTEGRATED CIRCUIT DEVICES - An integrated circuit device having a plurality of lines is described in which the widths of the lines, and the spacing between adjacent lines, vary within a small range which is independent of variations due to photolithographic processes, or other patterning processes, involved in manufacturing the device. A sequential sidewall spacer formation process is described for forming an etch mask for the lines, which results in first and second sets of sidewall spacers arranged in an alternating fashion. As a result of this sequential sidewall spacer process, the variation in the widths of the lines across the plurality of lines, and the spacing between adjacent lines, depends on the variations in the dimensions of the sidewall spacers. These variations are independent of, and can be controlled over a distribution much less than, the variation in the size of the intermediate mask element caused by the patterning process. | 05-21-2015 |
20150137256 | FINFET CELL ARCHITECTURE WITH POWER TRACES - A finFET block architecture suitable for use of a standard cell library, is based on an arrangement including a first set of semiconductor fins in a first region of the substrate having a first conductivity type, and a second set of semiconductor fins in a second region of the substrate, the second region having a second conductivity type. A patterned gate conductor layer including gate traces in the first and second regions, arranged over channel regions of the first and second sets of semiconductor fins is used for transistor gates. Patterned conductor layers over the gate conductor layer are arranged in orthogonal layout patterns, and can include a plurality of floating power buses over the fins in the first and second regions. | 05-21-2015 |
20150113492 | SRAM LAYOUTS - Roughly described, the cell layout in an SRAM array is re-arranged such that the gate electrodes for transistors for which flexibility to use one channel length is desired, are formed along a different track from those for transistors for which flexibility to use a different channel length is desired. Not only does such a re-arrangement permit optimization of device ratios, but also in certain implementations can also reduce, rather than increase, cell area. Specific example layouts are described. The invention also involves layout files, macrocells, lithographic masks and integrated circuit devices incorporating these principles, as well as fabrication methods. | 04-23-2015 |
20150103392 | DISPLAY WITH RETROREFLECTIVE ELEMENTS - In one embodiment, an apparatus includes a retroreflector pixel that includes multiple retroreflector sub-pixels. Each retroreflector sub-pixel includes a reflective surface configured to reflect incident light. Each retroreflector sub-pixel also includes a filter element configured to filter out from the incident light an electrically-controllable amount of light over a particular wavelength range. The filter element may utilize an electrophoretic technique based on charged particles, an electrowetting technique based on a dyed fluid, or an evanescent-wave coupling technique. The apparatus may include a controller communicably coupled to the retroreflector pixel and operable to control the filter element of each retroreflector sub-pixel. | 04-16-2015 |
20150089511 | ADAPTIVE PARALLELIZATION FOR MULTI-SCALE SIMULATION - Roughly described, a task control system for managing multi-scale simulations receives a case/task list which identifies cases to be evaluated, at least one task for each of the cases, and dependencies among the tasks. A module allocates available processor cores to at least some of the tasks, constrained by the dependencies, and initiates execution of the tasks on allocated cores. A module, in response to completion of a particular one of the tasks, determines whether or not the result of the task warrants stopping or pruning tasks, and if so, then terminates or prunes one or more of the uncompleted tasks in the case/task list. A module also re-allocates available processor cores to pending not-yet-executing tasks in accordance with time required to complete the tasks and constrained by the dependencies, and initiates execution of the tasks on allocated cores. | 03-26-2015 |
20150088803 | CHARACTERIZING TARGET MATERIAL PROPERTIES BASED ON PROPERTIES OF SIMILAR MATERIALS - Roughly described, a technique for approximating a target property of a target material is provided. For each material in a plurality of anchor materials, a correspondence is provided between the value for a predetermined index property of the material and a value for the target property of the material, the values of all the index properties being different. A predictor function is identified in dependence upon the correspondence. A computer system determines a value for the target property for the target material in dependence upon the predictor function and a value for the index property for the target material. The determined value for the target property for the target material is reported to a user. The correspondence can be provided in a database on a non-transitory computer readable medium. The correspondence can be determined experimentally or analytically for each material in a plurality of anchor materials. | 03-26-2015 |
20150088481 | ITERATIVE SIMULATION WITH DFT AND NON-DFT - Electronic design automation modules for simulate the behavior of structures and materials at multiple simulation scales with different simulation modules. | 03-26-2015 |
20150088473 | SIMULATION SCALING WITH DFT AND NON-DFT - Electronic design automation modules for simulate the behavior of structures and materials at multiple simulation scales with different simulation modules. | 03-26-2015 |
20150085585 | NVM DEVICE USING FN TUNNELING WITH PARALLEL POWERED SOURCE AND DRAIN - A nonvolatile memory (“NVM”) bitcell includes a capacitor, a transistor, and a tunneling device. The capacitor, transistor, and tunneling device are each electrically coupled to different active regions and metal contacts. The three devices are coupled by a floating gate that traverses the three active regions. The tunneling device is used to program and erase the device, allowing for faster page erasure, and thus allows for rapid testing and verification of functionality. The transistor is used to read the logical state of the floating gate. The capacitor and floating gate are capacitively coupled together, removing the need for a separate selection device to perform read, write, and/or erase operations. | 03-26-2015 |
20150085566 | INPUT TRIGGER INDEPENDENT LOW LEAKAGE MEMORY CIRCUIT - Wordline-driver biasing and column-based source-biasing circuitry facilitate reduced current leakage, for example, in SoC device SRAM circuits in a manner that is independent of the read/write/standby operating mode, and without an external trigger. Wordline-driver-biasing circuitry turns off (i.e., decouples from system power) wordline-drivers that are connected to unselected wordlines during read/write operations using one of a decoder-enable signal, which is generated in response to row address values, or based on the activation of a self-timing internal clock, which is generated by the memory circuit when it is activated (i.e., switched from standby to read/write mode). Alternatively, or in addition, source-biasing circuitry applies a relatively high source-biasing voltage to the source terminals of memory cells in unselected columns during read/write operations based on column address values (i.e., a low source voltage is applied only to the selected column being written to or read from). | 03-26-2015 |
20150071393 | LOW POWER DIGITAL FRACTIONAL DIVIDER WITH GLITCHLESS OUTPUT - A digital circuit that divides a high speed digital clock by a fractional value is described. The circuit utilizes a divider circuit and shifts the divider clock by a fraction of a phase to achieve the desired fractional division. A clock mux is used to perform the clock shift, and a masking mux is used to eliminate glitches during the clock shift. | 03-12-2015 |
20150070051 | HIGH SPEED PHASE SELECTOR WITH A GLITCHLESS OUTPUT USED IN PHASE LOCKED LOOP APPLICATIONS - A digital phase selector circuit that switches an output clock between N input clock phases is described. The phase selector utilizes a special output mux and switches clock phases during a safe zone to avoid glitches. The phase selector is used in the feedback path of a PLL to implement functions such as spread spectrum or fractional reference clocks. An example with N=4 and an optimized latch mux is shown. | 03-12-2015 |
20150067629 | DIAGNOSIS AND DEBUG USING TRUNCATED SIMULATION - Patterns used to detect a failure in a semiconductor chip are analyzed to determine a subset of logic in a design where a semiconductor chip, fabricated based on the design, contains a fault in the subset. Parts of the semiconductor chip can be pre-calculated to identify a key subsection of logic, based on the patterns, with that subsection being stored in a computer readable file. Good-machine simulation is performed on the subsection of logic using truncated rank-ordered simulation. The results are compared to the results of the testing of the physical semiconductor chip. | 03-05-2015 |
20150058859 | Deferred Execution in a Multi-thread Safe System Level Modeling Simulation - Methods, systems, and machine readable medium for multi-thread safe system level modeling simulation (SLMS) of a target system on a host system. An example of a SLMS is a SYSTEMC simulation. During the SLMS, SLMS processes are executed in parallel via a plurality of threads. SLMS processes represent functional behaviors of components within the target system, such as functional behaviors of processor cores. Deferred execution may be used to defer execution of operations of SLMS processes that access a shared resource. Multi-thread safe direct memory interface (DMI) access may be used by a SLMS process to access a region of the memory in a multi-thread safe manner. Access to regions of the memory may also be guarded if they are at risk of being in a transient state when being accessed by more than one SLMS process. | 02-26-2015 |
20150058854 | Direct Memory Interface Access in a Multi-Thread Safe System Level Modeling Simulation - Methods, systems, and machine readable medium for multi-thread safe system level modeling simulation (SLMS) of a target system on a host system. An example of a SLMS is a SYSTEMC simulation. During the SLMS, SLMS processes are executed in parallel via a plurality of threads. SLMS processes represent functional behaviors of components within the target system, such as functional behaviors of processor cores. Deferred execution may be used to defer execution of operations of SLMS processes that access a shared resource. Multi-thread safe direct memory interface (DMI) access may be used by a SLMS process to access a region of the memory in a multi-thread safe manner. Access to regions of the memory may also be guarded if they are at risk of being in a transient state when being accessed by more than one SLMS process. | 02-26-2015 |
20150058586 | Guarded Memory Access in a Multi-Thread Safe System Level Modeling Simulation - Methods, systems, and machine readable medium for multi-thread safe system level modeling simulation (SLMS) of a target system on a host system. An example of a SLMS is a SYSTEMC simulation. During the SLMS, SLMS processes are executed in parallel via a plurality of threads. SLMS processes represent functional behaviors of components within the target system, such as functional behaviors of processor cores. Deferred execution may be used to defer execution of operations of SLMS processes that access a shared resource. Multi-thread safe direct memory interface (DMI) access may be used by a SLMS process to access a region of the memory in a multi-thread safe manner. Access to regions of the memory may also be guarded if they are at risk of being in a transient state when being accessed by more than one SLMS process. | 02-26-2015 |
20150046897 | GENERALIZED MOMENT BASED APPROACH FOR VARIATION AWARE TIMING ANALYSIS - A method and apparatus of a device that performs a generalized moment based variation aware timing analysis on a circuit design is described. The device receives a signal path that traverses a plurality of gates. For each of the plurality of gates, the device retrieves a statistical distribution that represents delay variation at the gate. The statistical distribution for each gate is measured by a number of statistical moments that include higher order statistical moments besides the mean and the standard deviation of the distribution. The device computes statistical moments to represent the timing variation on the signal path by propagating statistical distributions of the gates on the signal path. The device reconstructs a statistical distribution function for timing variation on the signal path based on the computed statistical moments. | 02-12-2015 |
20150041924 | N-CHANNEL AND P-CHANNEL END-TO-END FINFET CELL ARCHITECTURE - A finFET block architecture uses end-to-end finFET blocks. A first set of semiconductor fins having a first conductivity type and a second set of semiconductor fins having a second conductivity type can be aligned end-to-end. An inter-block isolation structure separates the semiconductor fins in the first and second sets. The ends of the fins in the first set are proximal to a first side of the inter-block isolation structure and ends of the fins in the second set are proximal to a second side of the inter-block isolation structure. A patterned gate conductor layer includes a first gate conductor extending across at least one fin in the first set of semiconductor fins, and a second gate conductor extending across at least one fin in the second set of semiconductor fins. The first and second gate conductors are connected by an inter-block conductor. | 02-12-2015 |
20150041921 | INCREASING ION/IOFF RATIO IN FINFETS AND NANO-WIRES - Roughly described, an integrated circuit transistor structure has a body of semiconductor material, the body having two longitudinally spaced doped source/drain volumes with a channel between, a gate stack disposed outside the body and facing at least one of the surfaces of the body along the channel. The body contains an adjustment volume, longitudinally within the channel volume and spaced behind the first surface by a first distance and spaced longitudinally from both the source/drain volumes. The adjustment volume comprises an adjustment volume material having, at each longitudinal position, an electrical conductivity which differs from that of the adjacent body material at the same longitudinal position, at least while the transistor is in an off-state. In one embodiment the adjustment volume material is a dielectric. In another embodiment the adjustment volume material is an electrical conductor. | 02-12-2015 |
20150040107 | SOLVING AN OPTIMIZATION PROBLEM USING A CONSTRAINTS SOLVER - Systems and techniques are described for solving an optimization problem using a constraints solver. A set of constraints that correspond to the optimization problem can be generated. Next, a set of upper bound constraints can be added to the set of constraints, wherein the set of upper bound constraints imposes an upper bound on one or more variables that are used in an objective function of the optimization problem. Next, the embodiments can iteratively perform the following set of operations on a computer: (a) solve the set of constraints using the constraints solver; (b) responsive to the constraints solver returning a solution, decrease the upper bound; and (c) responsive to the constraints solver indicating that no solutions exist or that the constraints solver timed out, increase the upper bound. The solution with the lowest upper bound value can be outputted as the optimal solution for the optimization problem. | 02-05-2015 |
20150040096 | EMULATION-BASED FUNCTIONAL QUALIFICATION - Techniques for emulation-based functional qualification are disclosed that use an emulation platform to replace simulation in mutation-based analysis. A method for functional qualification of an integrated circuit design includes receiving an integrated circuit design having one or more mutations. Emulation setup and activation simulation are performed in parallel to maximize computing resources. A prototype board can then be programmed according to the integrated circuit design and a verification module. A set of test patterns and response generated by a simulation of the integrated circuit using the set of test patterns are stored in a memory of the prototyping board allowing enumeration of mutants to occur at in-circuit emulation speed. | 02-05-2015 |
20150040093 | ROBUST NUMERICAL OPTIMIZATION FOR OPTIMIZING DELAY, AREA, AND LEAKAGE POWER - Systems and techniques are described for performing numerical delay, area, and leakage power optimization on a circuit design. During operation, an embodiment can iteratively perform at least the following set of operations in a loop, wherein in each iteration a current threshold voltage value is progressively decreased: (a) perform numerical delay optimization on the circuit design using a numerical delay model that is generated using gates in a technology library whose threshold voltages are equal to the current threshold voltage; (b) perform a total negative slack based buffering optimization on the circuit design; and (c) perform a worst negative slack touchup optimization on the circuit design that uses gates whose threshold voltages are greater than or equal to the current threshold voltage. Next, the embodiment can perform combined area and leakage power optimization on the circuit design. The embodiment can then perform multiple iterations of worst negative slack touchup optimization. | 02-05-2015 |
20150040090 | DISCRETIZING GATE SIZES DURING NUMERICAL SYNTHESIS - Systems and techniques are described for discretizing gate sizes during numerical synthesis. Some embodiments can receive an optimal input capacitance value for an input of an optimizable cell, wherein the input capacitance value is determined by a numerical solver that is optimizing the circuit design. Note that the circuit design may be optimized for different objective functions, e.g., best delay, minimal area under delay constraints, etc. Next, the embodiments can identify an initial library cell in a technology library whose input capacitance value is closest to the optimal input capacitance value. The embodiments can then use the initial library cell to attempt to identify a better (in terms of the objective function that is being optimized) library cell in the technology library. The delay computations used during this process are also minimized. | 02-05-2015 |
20150040089 | NUMERICAL AREA RECOVERY - Systems and techniques are described for performing area recovery on a circuit design. Some embodiments can select a gate for area recovery in accordance with a reverse-levelized processing order, wherein an output pin of a driver gate is electrically coupled to an input pin of the gate. Next, the embodiment can determine a maximum delay value from an input pin of the driver gate to an output pin of the gate that does not create new timing requirement violations or worsen existing timing requirement violations at any of the timing endpoints of the circuit design. The embodiment can then downsize the gate based on the maximum delay value, wherein said downsizing comprises inputting the maximum delay value in a closed-form expression. Timing margin computation can be used to ensure that timing violations are not worsened when the embodiment recovers area from non-timing-critical regions of the circuit design. | 02-05-2015 |
20150039664 | SOLVING A GATE-SIZING OPTIMIZATION PROBLEM USING A CONSTRAINTS SOLVER - Systems and techniques are described for solving a gate-sizing optimization problem using a constraints solver. Some embodiments can create a constraints problem based on a gate-sizing optimization problem for a portion of a circuit design. Specifically, the constraints problem can comprise a set of upper bound constraints that impose an upper bound on one or more variables that are used in the objective function of the gate-sizing optimization problem. Next, the embodiments can solve the gate-sizing optimization problem by repeatedly solving the constraints problem using a constraints solver. Specifically, prior to each invocation of the constraints solver, the upper bound can be increased or decreased based at least on a result returned by a previous invocation of the constraints solver. | 02-05-2015 |
20150034909 | ASYMMETRIC DENSE FLOATING GATE NONVOLATILE MEMORY WITH DECOUPLED CAPACITOR - A nonvolatile memory (“NVM”) bitcell includes a capacitor, an asymmetrically doped transistor, and a tunneling device. The capacitor, transistor, and tunneling device are each electrically coupled to different active regions and metal contacts. The three devices are coupled by a floating gate that traverses the three active regions. The tunneling device is formed in a native region to allow for greater dynamic range in the voltage used to induce tunneling. The FN tunneling device is used to erase the device, allowing for faster page erasure, and thus allows for rapid testing and verification of functionality. The asymmetric transistor, in conjunction with the capacitor, is used to both program and read the logical state of the floating gate. The capacitor and floating gate are capacitively coupled together, removing the need for a separate selection device to perform read and write operations. | 02-05-2015 |
20140359545 | EQUIVALENCE CHECKING USING STRUCTURAL ANALYSIS ON DATA FLOW GRAPHS - A design is verified by using equivalence checking to compare a word-level description of the design to a bit-level description of the design. A word-level data flow graph (DFG) based on the word-level description and a bit-level DFG is obtained. Structural analysis is used to reduce the graphs and partition them into smaller portions for the equivalence checking. The analysis includes searching the bit-level DFG to find partial-product encoding and removing redundancy from the bit-level DFG. A reference model with architectural information from the bit-level DFG is created based on the word-level DFG. The reference model is reduced and equivalence checked against the bit-level DFG to determine if the word-level description is equivalent to the bit-level description. | 12-04-2014 |
20140358830 | LITHOGRAPHIC HOTSPOT DETECTION USING MULTIPLE MACHINE LEARNING KERNELS - A hotspot detection system that classifies a set of hotspot training data into a plurality of hotspot clusters according to their topologies, where the hotspot clusters are associated with different hotspot topologies, and classifies a set of non-hotspot training data into a plurality of non-hotspot clusters according to their topologies, where the non-hotspot clusters are associated with different topologies. The system extracts topological and non-topological critical features from the hotspot clusters and centroids of the non-hotspot clusters. The system also creates a plurality of kernels configured to identify hotspots, where each kernel is constructed using the extracted critical features of the non-hotspot clusters and the extracted critical features from one of the hotspot clusters, and each kernel is configured to identify hotspot topologies different from hotspot topologies that the other kernels are configured to identify. | 12-04-2014 |
20140346634 | ON-CHIP INDUCTORS WITH REDUCED AREA AND RESISTANCE - An integrated circuit that includes an on-chip inductor wrapped around an interface pad. On-chip inductors are arranged around an interface pad to reduce the area occupied by the inductor. Furthermore, arranging the on-chip inductors in an upper level metal layer, such us the redistribution layer (RDL), the top metal interconnect layer (MTop), or the second-to-top metal interconnect layer (MTop-1) reduces the on-chip inductor parasitic resistance, reducing the loss of signal. | 11-27-2014 |
20140344772 | SEMI-LOCAL BALLISTIC MOBILITY MODEL - A transistor model defines the carrier mobility as a combination of both drift-diffusion mobility and ballistic mobility. The ballistic mobility is calculated based on the assumption that the kinetic energy of carriers near an injection point is no greater than the potential energy difference of carriers near that injection point. The abruptness of the onset of velocity saturation, as well as the asymptotic velocity associated therewith is made dependent on the degree to which the velocity is ballistically limited. The model further takes into account the inertial effects on the velocity and/or charge flux associated with carriers. The model computes the mobility and hence the velocity of carriers in accordance with their positions in the channel both along the direction of the current flow as well as the direction perpendicular to the current flow. | 11-20-2014 |
20140344637 | SEQUENTIAL LOGIC SENSITIZATION FROM STRUCTURAL DESCRIPTION - A method of sensitizing a sequential circuit is described. This sensitizing generates stimuli to drive any circuit output to a predetermined value or transition. The method includes creating a directed graph of the sequential circuit. Nodes of the graphs can be topologically sorted. In one embodiment, feedback loops in the directed graph can be removed before topologically sorting the nodes. Final vectors for the sequential circuit can be generated based on the sorted nodes. Notably, the final vectors are expressed only by primary inputs to the sequential circuit. Using only primary inputs in the final vectors accurately replicates the sequential circuit under test, thereby ensuring accurate timing, power, and noise arcs are measured. | 11-20-2014 |
20140337811 | SUB-MODULE PHYSICAL REFINEMENT FLOW - A computer system is provided that enables a designer of a circuit design to fracture and reconstitute a larger design for both computer modeling of the functionality and the physical implementation or rendering of the circuit design. More particularly, the designer may refine or re-work a sub-module of the larger sub-circuit without having to create a corresponding sub-module in the physical implementation. This capability thus avoids the significant complexity required for sub-module refinement in the current state of the art, and provides the designer with a much simpler flow. | 11-13-2014 |
20140330758 | FORMAL VERIFICATION RESULT PREDICTION - A design verification problem includes a design description and a property to be verified. Feature data is identified from the design verification problem and a result is predicted for the design verification problem based on the feature data. A plurality of verification engines is then orchestrated based on the prediction. Supervised machine learning may be used for the result prediction. Feature data and verification results from a plurality of training test cases are used to train a classifier to create a prediction model. The prediction model uses the feature data of the design verification problem to make a result prediction for the design verification model. | 11-06-2014 |
20140324374 | EXTRACTING ATTRIBUTE FAIL RATES FROM CONVOLUTED SYSTEMS - A method, system or computer usable program product for extracting attribute fail rates for manufactured devices including testing manufactured devices having a set of attributes to provide a set of test results stored in memory; generating a yield model of the manufactured devices parsed by the set of attributes; populating the yield model based on the set of test results; and utilizing a processor to perform statistical analysis of the populated yield model to extract fail rates of the selected subset of attributes. | 10-30-2014 |
20140317378 | Scheduling in a Multicore Architecture - This invention relates to scheduling threads in a multicore processor. Executable transactions may be scheduled using at least one distribution queue, which lists executable transactions in order of eligibility for execution, and multilevel scheduler which comprises a plurality of linked individual executable transaction schedulers. Each of these includes a scheduling algorithm for determining the most eligible executable transaction for execution. The most eligible executable transaction is outputted from the multilevel scheduler to the at least one distribution queue. | 10-23-2014 |
20140306741 | Phase-Locked Loop System and Operation - A phase-locked loop system has a controlled oscillator that provides an output clock signal based on a oscillator control signal, a feedback path configured to provide a feedback signal based on the output clock signal, a phase detector configured to provide a phase dependent signal based on the feedback signal and a reference clock signal, a phase evaluation block configured to provide the oscillator control signal based on the phase dependent signal, a frequency detector that determines whether the frequency ratio between the output clock signal and the reference clock signal has a desired value, and a control logic. The control logic is configured to, during a start-up period, disable the phase evaluation block upon determination of the desired value of the frequency ratio; detect, after disabling the phase evaluation block, a subsequent clock edge of the reference clock signal; and enable, in response to the detection of the subsequent clock edge, the phase evaluation block. | 10-16-2014 |
20140304671 | MANIPULATING PARAMETERIZED CELL DEVICES IN A CUSTOM LAYOUT DESIGN - A system, apparatus and computer-implemented method for manipulating a parameterized cell device into a custom layout design. The method begins by receiving at least one parameterized cell representing a physical circuit from, for example, a database or configuration file. The parameterized cell has a plurality of configurable attributes. The method continues by adjusting one of the configurable attributes of the parameterized cell according to a capability associated with the one attribute. The attributes may include one or more of a parameter mapping capability, a port mapping capability, an abutment capability, a directional extension capability, a channel width capability, and a boundary layer capability. The method then calculates a new configuration for the parameterized cell based upon the adjustment, and applies the new configuration for the parameterized cell to a layout of the represented physical circuit. | 10-09-2014 |
20140289694 | DUAL-STRUCTURE CLOCK TREE SYNTHESIS (CTS) - Dual-structure clock tree synthesis (CTS) is described. Some embodiments can construct a set of upper-level clock trees, wherein each leaf of each upper-level clock tree is a root of a lower-level clock tree. Each upper-level clock tree can be optimized to reduce an impact of on-chip-variation and/or cross-corner variation on clock skew. Next, for each leaf of each upper-level clock tree, the embodiments can construct a lower-level clock tree to distribute a clock signal from the leaf of the upper-level clock tree to a set of clock sinks. The lower-level clock tree can be optimized to reduce latency, power consumption, and/or area. | 09-25-2014 |
20140289690 | ON-CHIP-VARIATION (OCV) AND TIMING-CRITICALITY AWARE CLOCK TREE SYNTHESIS (CTS) - On-chip-variation (OCV) and timing-criticality aware clock tree synthesis (CTS) is described. Some embodiments can construct a first set of clock tree topologies for timing sequential circuit elements in a set of critical paths, wherein said constructing can comprise optimizing the first set of clock tree topologies to reduce an impact of OCV on clock skew. Next, the embodiments can construct a second set of clock tree topologies for timing sequential circuit elements that are not in the set of critical paths, wherein said constructing can comprise optimizing the second set of clock tree topologies to reduce latency, power consumption, and/or area. | 09-25-2014 |
20140289685 | DYNAMIC POWER DRIVEN CLOCK TREE SYNTHESIS (CTS) - Dynamic power driven clock tree synthesis is described. Some embodiments can select one or more cells from a cell library based on power ratios of cells in the cell library. The embodiments can then construct a clock tree based on the one or more cells. | 09-25-2014 |
20140282593 | Scheduling in a multicore architecture - The disclosure relates to scheduling threads in a multicore processor. Executable transactions may be scheduled using at least one distribution queue, which lists executable transactions in order of eligibility for execution, and multilevel scheduler which comprises a plurality of linked individual executable transaction schedulers. Each of these includes a scheduling algorithm for determining the most eligible executable transaction for execution. The most eligible executable transaction is outputted from the multilevel scheduler to the at least one distribution queue. | 09-18-2014 |
20140282350 | AUTOMATIC CLOCK TREE SYNTHESIS EXCEPTIONS GENERATION - Systems and techniques are described for automatically generating clock tree synthesis (CTS) exceptions. The process can use on one or more criteria to identify sequential circuit elements that can be ignored during clock skew minimization. For example, the process can identify sequential circuit elements whose clock skew cannot be balanced with other sequential circuit elements due to structural reasons, identify sequential timing elements that do not have a timing relationship with other sequential timing elements in the clock tree, and/or identify sequential circuit elements whose data pins have a sufficiently large slack so that clock skew is not expected to cause timing violations at any of the data pins. Next, the process can generate clock tree exceptions based on the identified sequential circuit elements. | 09-18-2014 |
20140282343 | PRIORITIZED SOFT CONSTRAINT SOLVING - A design problem can include a mixture of hard constraints and soft constraints. The soft constraints can be prioritized and the design problem solved. One or more soft constraints may not be honored in the midst of the solving of the design problem. Debugging can be performed and the unsatisfied soft constraints identified. Root-cause analysis can evaluate the challenges within the design problem which caused soft constraints not to be honored. | 09-18-2014 |
20140282339 | AUTOMATIC TAP DRIVER GENERATION IN A HYBRID CLOCK DISTRIBUTION SYSTEM - A hybrid clock distribution system uses a distribution fabric to distribute clock signals across longer physical distances and local sub-distribution networks to distribute clock signals more locally and to implement logic functions such as clock gating. A set of tap drivers connect the distribution fabric to the sub-distribution networks. A design tool automatically generates and places the set of tap drivers. | 09-18-2014 |
20140282335 | PHASE DETERMINATION FOR EXTRACTION FROM SCATTERING PARAMETERS - Scattering (S) parameters can be evaluated for a plurality of conductors on a semiconductor device to determine phase based on traversal around a Smith chart type representation. A propagation function for the plurality of conductors can be derived from S parameters, which in turn, can be used to derive resistance, inductance, capacitance, and/or conductance parameters. A Smith chart representation is used to obtain zero crossing information for determination of accurate phase information. | 09-18-2014 |
20140282317 | ARRIVAL EDGE USAGE IN TIMING ANALYSIS - A logic design is analyzed using static timing analysis and timing edge tracking for various nets within the logic design. Crosstalk analysis is performed on the logic design to evaluate timing impacts. To reduce pessimism of crosstalk analysis for a victim net, arrival edges are tracked for the victim net. The switching times of the aggressor net are compared to the edges of the victim net during crosstalk analysis. | 09-18-2014 |
20140282316 | SOLVING MULTIPLICATION CONSTRAINTS BY FACTORIZATION - A design description for verification includes a set of constraints on random variables within the design description. The set of constraints includes at least one multiplication constraint involving at least two random variables. A computer-based tool obtains designs and analyzes the design description to find the set of constraints and identify the multiplication constraint. The computer-based tool then performs factorization to solve for the multiplication constraint and to determine a set of potentially valid factoring values for the random variables used in the multiplication constraint. The design problem is then solved by the computer-based tool using the factoring values. If two multiplication constraints involve a common variable, the factorization finds a set of common factoring values between the two multiplication constraints to use for the common variable. | 09-18-2014 |
20140282315 | GRAPHICAL VIEW AND DEBUG FOR COVERAGE-POINT NEGATIVE HINT - The present invention provides a graphical view of this connected network that allows the user to navigate throughout a network. The graph view consists of a series of nodes that correspond to a set of test, testbench, design or coverage items in the simulation. Various nodes in the network are colored or shaped differently to represent either test, class, stimulus, testbench, design or coverage points. The graph may be drawn so that all items that occur at the same time are lined up in the same horizontal or vertical region, to give the user an intuitive view of time going left to right or top to bottom. | 09-18-2014 |
20140282298 | PERFORMING IMAGE CALCULATION BASED ON SPATIAL COHERENCE - Computer-implemented techniques for pixel source optics calculations using spatial coherence are disclosed. Pixelated sources are used for source-mask co-optimization to enhance semiconductor lithography. Calculation of a partially coherent imaging system is used for optical-lithography simulation. The spatial coherence property of neighboring source points is used to reduce imaging calculation complexity. Two or more neighboring points are treated as one pseudo-spatially coherent area element. | 09-18-2014 |
20140282290 | SUB-RESOLUTION ASSIST FEATURE IMPLEMENTATION USING SHOT OPTIMIZATION - A design layout for a semiconductor chip includes information on shapes desired to be fabricated. Clusters of photolithographic exposure “shots” are generated and subject to a measure of shot density to approximate a mask shape that generates the desired fabricated shapes when exposed during wafer fabrication. A simulation is run on the clusters of shots to estimate the resulting fabrication shapes that the clusters of shots create. The clusters of shots are modified to align the estimated fabrication shapes more closely with desired fabrication shapes. The process of simulating and modifying the shots is iterative, repeating until the estimated fabrication shapes are within a desired error difference of the planned fabrication shape. | 09-18-2014 |
20140281777 | Localizing Fault Flop in Circuit by Using Modified Test Pattern - A method for localizing at least one scan flop associated with a fault in an integrated circuit. A first test pattern, including a first scan-in data and first control data, is generated. Based on the first control data of the first test pattern, a first fault data is generated by applying the first scan-in data of the first test pattern to scan flops in a test circuit of the integrated circuit. If the first fault data indicates that a fault may be present in the integrated circuit, a second test pattern, including a second scan-in data and a second control data is generated. | 09-18-2014 |
20140281774 | Two-Level Compression Through Selective Reseeding - A scan test system and technique compresses CARE bits and X-control input data into PRPG seeds, thereby providing a first compression. The scan test system includes a plurality of compressor and decompressor structures (CODECs). Each block of the design includes at least one CODEC. An instruction decode unit (IDU) receives scan inputs and determines whether a seed extracted from the scan inputs is broadcast loaded in the CODECs, multicast loaded in a subset of the CODECs, or individual loaded in a single CODEC. This sharing of seeds, exploits the hierarchical nature of large designs with many PRPGs, provides a second compression. Results on large industrial designs demonstrate significant data and cycle compression increases while maintaining test coverage, diagnosability, and performance. | 09-18-2014 |
20140281114 | Memory Interface and Method of Interfacing Between Functional Entities - A data and signal interface for controlling the transfer of data and signals between a memory array and macro function such as that of a digital signal processor (DSP) core. In one embodiment, the interface comprises a plurality of memory ports which interface with X/Y memory banks, a plurality of function ports, each with a function controller, which interface with DSP functions, a crossbar connecting the memory and function ports, and an arbitration unit for arbitrating memory access by the function ports. The memory interface advantageously allows multiple simultaneous accesses of memory banks via a plurality of macro functions, each access under the control of a parent processor instruction. A standardized protocol used for memory read/write operations is also disclosed. | 09-18-2014 |
20140278263 | Specification-Guided User Interface for Optical Design Systems - An optical design system generates a design state overview of a design of an optical system, the design state overview summarizing a current state and a target state of the design by describing a plurality of specifications for the optical system, the specification descriptions including target ranges for the specifications based on the target state of the design and further including current values for the specifications based on the current state of the design. The optical design system displays the design state overview. The optical design system updates the design state overview in response to the optical design system changing the current design for the optical system. | 09-18-2014 |
20140269105 | CIRCUIT FOR GENERATING NEGATIVE BITLINE VOLTAGE - An integrated circuit for generating a negative bitline voltage comprises a bitline connectable to a memory cell and a multitude of capacitors arranged in groups thereof connected to the bitline. A step signal generator can generate a consecutive sequence of step signals to be applied to a group of capacitors. The circuit may be part of an integrated memory circuit device to drive the bitline to a negative voltage to implement a write assist scheme. | 09-18-2014 |
20140258964 | AUTOMATIC SYNTHESIS OF COMPLEX CLOCK SYSTEMS - A global optimization method to synthesize and balance the clock systems in a multimode, multi-corner, and multi-domain design environment is described. The method builds a graph representation for a clock network. The method determines an optimal clock network balancing solution for the clock network by applying linear programming to the graph. To apply linear programming to the graph, the method generates a set of constraints for the graph and determines a proper insertion delay for each edge of the graph by solving for a minimal skew based on the set of constraints. The method implements the optimal clock network balancing solution. | 09-11-2014 |
20140258963 | PLACEMENT AND ROUTING ON A CIRCUIT - Methods and apparatuses to place and route cells on integrated circuit chips along paths is described. In one embodiment, the method to layout an integrated circuit, the method comprises routing a wire to connect a first cell of the integrated circuit and a second cell of the integrated circuit, and placing a third cell of the integrated circuit after said routing the wire to connect the first cell and the second cell. | 09-11-2014 |
20140258954 | RANKING VERIFICATION RESULTS FOR ROOT CAUSE ANALYSIS - Verification-result ranking techniques for root cause analysis are disclosed using violation report analysis and violation weighting. Violation reports are unwieldy and result from a variety of design and process checks. The check coverage can overlap, causing a specific violation to trigger multiple reported violations. High turn around times for violation report analysis increase the risk that selective violation analysis will inadvertently suppress real design bugs. This reduces the odds that static checker reports alone will meet design sign-off criteria. Determining relationships among a plurality of violations for a design permits clustering violations into hot spots. Identification of primary and subsequent contributors to the plurality of violations is based on the relationships among violations. The hot spot with the highest weight is identified, and then subsequent violations are identified to maximize violation coverage. The result is greater efficiency of design violation identification and resolution. | 09-11-2014 |
20140258953 | HIGH PERFORMANCE DESIGN RULE CHECKING TECHNIQUE - Roughly described, a design rule data set is developed offline from the design rules of a target fabrication process. A design rule checking method involves traversing the corners of shapes in a layout region, and for each corner, populating a layout topology database with values that depend on respective corner locations. After the layout topology database is populated, the values are compared to values in the design rule data set to detect any design rule violations. Violations can be reported in real time, while the user is manually editing the layout. Preferably corner traversal is performed using scan lines oriented perpendicularly to edge orientations, and scanning in the direction of the edge orientations. Scans stop only at corner positions and populate the layout topology database with what information can be gleaned based on the current scan line. The different scans need not reach each corner simultaneously. | 09-11-2014 |
20140257544 | METHOD AND APPARATUS FOR PROCESS WINDOW MODELING - A photolithographic modeling process is disclosed. Optical and non-optical parts of a model of the photolithographic process are calibrated. With the non-optical part of the model one or more model corrections are determined between (i) modeled critical dimension data from an aerial image generated by the optical part of the model, and (ii) empirical critical dimension data from tangible structures made at only a first process combination of a first dose and a first defocus in the photolithographic process. Critical dimension data of the photolithographic process are predicted at a second process combination of a second dose and a second defocus in the photolithographic process. | 09-11-2014 |
20140253211 | LOW VOLTAGE LEVEL SHIFTER FOR LOW POWER APPLICATIONS - A level shifter circuit for low power applications that can shift the level of a digital signal that is below the threshold voltage of output transistors. The level shifter uses core transistors in the input stage and includes an intermediate stage that limits the voltage applied to the drain of the core transistors. The intermediate stage may include two transistors whose gate is connected to a reference voltage and turns off when the voltage at their source is equal to a threshold voltage below the reference voltage, thus limiting the maximum voltage applied to the transistors present in the input stage. | 09-11-2014 |
20140245239 | DETECTION AND REMOVAL OF SELF-ALIGNED DOUBLE PATTERNING ARTIFACTS - Mask design techniques for detection and removal of undesirable artifacts in SADP processes using multiple patterns are disclosed. Artifacts or spurs result from lithographic and chemical processing of semiconducting wafers. The spurs are undesirable because they can cause unwanted connections or act as electrical antennas. Spurs are detected using rule-based techniques and reduced by modifying lithographic masks. The severity of the detected spurs is determined, again using rule-based techniques. The effects of detected spurs can be reduced by modifying the decomposition of the drawn patterns into the two masks used for lithography. Mandrel masks are modified by add dummy mandrel material, and trim masks are modified by removing trim material. The resulting multi-pattern arrangement is used to fabricate the critical design elements that make up the semiconductor wafers. | 08-28-2014 |
20140245237 | HYBRID EVOLUTIONARY ALGORITHM FOR TRIPLE-PATTERNING - According to one embodiment of the present invention, a computer-implemented method for validating a design includes generating, using the computer, a first graph representative of the design, when the computer is invoked to validate the design, and decompose, using the computer, the first graph into at least three sets using a hybrid evolutionary algorithm to form a colored graph. | 08-28-2014 |
20140244233 | EXECUTING A HARDWARE SIMULATION AND VERIFICATION SOLUTION - One embodiment of the present invention provides systems and techniques to execute a hardware simulation and verification solution on a multiprocessor system. The hardware simulation and verification solution can be partitioned into different modules which can include a simulation kernel to simulate changes in signal values, a value change dump module to store the changes in the signal values on a computer-readable storage medium, a functional coverage module to check functionality, a toggle coverage module to check signal toggling, an assertion engine to check complex behaviors, and a testbench module to generate test scenarios. Embodiments of the present invention can execute different modules on different processors, thereby improving performance. | 08-28-2014 |
20140244226 | COMPACT OPC MODEL GENERATION USING VIRTUAL DATA - A method, system or computer usable program product for building a fast lithography OPC model that predicts semiconductor manufacturing process outputs on silicon wafers including providing a first principles model of the semiconductor manufacturing process, providing a set of empirical data for storage in memory, utilizing a processor to develop a rigorous model for a process condition from the first principles model and the set of empirical data, and utilizing the processor running the rigorous model to generate emulated data for the process condition to develop a virtual model for predicting the semiconductor manufacturing process outputs. | 08-28-2014 |
20140237437 | LOOK-UP BASED FAST LOGIC SYNTHESIS - Systems and techniques are described for performing circuit synthesis. Some embodiments create a lookup table based on information contained in a cell library. The lookup table is then used during circuit synthesis. Specifically, some embodiments optimize cells in a reverse-levelized cell ordering. For a given cell, a table lookup is performed to obtain a set of optimal cell configurations, and the cell is replaced with a cell configuration selected from the set of optimal cell configurations. Some embodiments concurrently optimize cells for timing, area, and power leakage based on the timing criticality of the cells. | 08-21-2014 |
20140237006 | METHOD FOR MANAGING DESIGN FILES SHARED BY MULTIPLE USERS AND SYSTEM THEREOF - A method for managing design files shared by multiple users is provided. A plurality of design files are stored in a design library. A lock table is moved to a memory of a first computer when information of the lock table indicates that the design files were locked by a first process corresponding to a first user, wherein the memory is only accessible to performance of the first process. The lock table is moved from the memory to a common memory of the first computer when one design file is locked by a second process corresponding to a second user. The first and second processes are being performed in the first computer. The lock table is moved from the memory to the design library when the one design file is locked by the second process corresponding to the second user, wherein the second process is performed in a second computer. | 08-21-2014 |
20140223400 | NUMERICAL DELAY MODEL FOR A TECHNOLOGY LIBRARY CELL TYPE - Methods and systems for determining a numerical delay model based on one or more discretized delay models are described. A discretized delay model is a delay model in which the delay behavior is represented using a set of discrete data points of delay behavior. A numerical delay model is a delay model that can be used by a numerical solver to optimize a cost function. In general, computing delay using a numerical delay model is significantly faster than computing delay using discretized delay models. This performance improvement is important when optimizing a design for various metrics like timing, area and leakage power, because repeated delay computations are required in circuit optimization approaches. | 08-07-2014 |
20140223395 | BOOSTING TRANSISTOR PERFORMANCE WITH NON-RECTANGULAR CHANNELS - Roughly described, the invention includes layouts and masks for an integrated circuit, in which the diffusion shape for a transistor includes a transversely extending jog on one or both transversely opposite sides, the jog having inner and outer corners, at least one of which is located relative to the gate conductor longitudinally such that during lithographic printing of the diffusion shape onto the integrated circuit, the corner will round and extend at least partly into the channel region. The invention also includes aspects for a system and method for introducing such jogs, and for an integrated circuit device having a non-rectangular channel region, the channel region being wider where it meets the source region than at some other longitudinal position under the gate. | 08-07-2014 |
20140223394 | METHODS FOR MANUFACTURING INTEGRATED CIRCUIT DEVICES HAVING FEATURES WITH REDUCED EDGE CURVATURE - A structure, such as an integrated circuit device, is described that includes a line of material with critical dimensions which vary within a distribution substantially less than that of a mask element, such as a patterned resist element, used in etching the line. Techniques are described for processing a line of crystalline phase material which has already been etched using the mask element, in a manner which straightens an etched sidewall surface of the line. The straightened sidewall surface does not carry the sidewall surface variations introduced by photolithographic processes, or other patterning processes, involved in forming the mask element and etching the line. | 08-07-2014 |
20140217514 | N-CHANNEL AND P-CHANNEL END-TO-END FINFET CELL ARCHITECTURE WITH RELAXED GATE PITCH - A finFET block architecture uses end-to-end finFET blocks in which the fin lengths are at least twice the contact pitch, whereby there is enough space for interlayer connectors to be placed on the proximal end and the distal end of a given semiconductor fin, and on the gate element on the given semiconductor fin. A first set of semiconductor fins having a first conductivity type and a second set of semiconductor fins having a second conductivity type can be aligned end-to-end. Interlayer connectors can be aligned over corresponding semiconductor fins which connect to gate elements. | 08-07-2014 |
20140215427 | Optimizing Designs of Integrated Circuits - Methods and systems for optimizing and/or designing integrated circuits. One exemplary method includes determining fanout of a driving component in a representation of an integrated circuit (IC) being designed, determining for the driving component, the loads in the representation of the IC driven by the driving component, and determining use of existing wiring resources used to connect the loads to the driving component. The method further includes optimizing, based on the use of existing wiring resources, the fanout of the driving component, and the loads being driven by the driving component, a design of the IC. | 07-31-2014 |
20140208280 | MODELING MECHANICAL BEHAVIOR WITH LAYOUT-DEPENDENT MATERIAL PROPERTIES - Computer-implemented techniques for modeling the mechanical behavior of integrated circuits using layout-dependent material properties are disclosed. The back end of line wiring that connects an integrated circuit to a substrate undergoes stresses and strains due to many heating and cooling cycles during a chip's packaging and lifecycle. Depending on integrated circuit design style, there may be vastly different thermal profiles across the integrated circuit. The mechanical behavior caused by the thermal cycles of the wire, vias, and insulators comprising the BEOL materials is simulated. Extraction of the integrated circuit structural information, regarding the BEOL materials, yields anisotropic information. Layout-dependent material volume fractions are computed using integrated circuit structural information. Anisotropic mechanical properties are determined based on the structural information. Mechanical responses are calculated based on the anisotropic material properties and the calculated material-volume fractions. | 07-24-2014 |
20140208087 | MICROPROCESSOR ARCHITECTURE HAVING EXTENDIBLE LOGIC - A microprocessor architecture having extendible logic. One or more customized applications are available to the instruction pipeline. The customizable applications may include software, extension logic instruction or register, dynamically configurable hardware logic, or combinations of these. In order to enable the operating system to interface with the customized extension applications, at least one software extension is provided to the operating system. When a specific extension is requested a software exception is generated by the OS. In response to the exception, the least one software extension is called to handle context switch and dynamic configuration of the extendible logic of the microprocessor. | 07-24-2014 |
20140196014 | System and Method of Debugging Multi-Threaded Processes - A system and method of debugging a multi-threaded process with at least one running thread and at least one suspended thread is disclosed. Embodiments utilize a blocking function to block the thread of a process while other threads are allowed to run. The blocking function may be executed in a suspended thread by a debugger under control of a thread blocking controller. The other threads may implement interprocess communication channels for enabling communication between the process and another application. A simulated user interface (UI) of a debugger enables interaction with users while a hardware simulation thread is blocked, where blocking of the hardware simulation thread may be implemented by a thread blocking component implemented externally to the debugger. Where a thread blocking controller is implemented within the debugger, a debugger UI may interact with a user while the hardware simulation thread is blocked and interprocess communication threads are running | 07-10-2014 |
20140189634 | PRIORI CORNER AND MODE REDUCTION - Systems and techniques are described for performing a priori corner and mode reduction. Some embodiments create a synthetic corner in which (1) a cell delay for each library cell in a set of library cells corresponds to a maximum delay over multiple temperature corners, and/or (2) a cell delay for each library cell in a set of library cells corresponds to a maximum delay over multiple parasitic corners. Some embodiments can identifying, for a given corner, a portion of the circuit design that is common across multiple modes, and then replace the multiple modes with a single mode for optimizing and verifying timing constraints of the portion of the circuit design that is common across the multiple modes. The circuit design can then be optimized over the reduced set of modes and/or corners. | 07-03-2014 |
20140189632 | MULTIPLE-INSTANTIATED-MODULE (MIM) AWARE PIN ASSIGNMENT - Systems and techniques for multiple-instantiated-module (MIM)-aware pin assignment are described. An aggregate cost function can be determined, wherein the aggregate cost function is aggregated across all instances of an MIM for placing a pin at a particular location on the boundary of the MIM. The aggregate cost function can then be used by a pin assignment engine to place the pin in the MIM. A pin assignment engine can place one pin at a time, or place multiple pins at a time by trying to optimize the aggregate cost over multiple pins. Some embodiments can propagate pin-alignment constraints through one or more instances of one or more MIMs in the circuit design layout, and then perform pin assignment while observing the pin-alignment constraints. In some embodiments, pin assignment can be performed on MIMs in decreasing order of the number of pin-alignment constraints that are imposed on the MIMs. | 07-03-2014 |
20140189629 | PATTERN-BASED POWER-AND-GROUND (PG) ROUTING AND VIA CREATION - Systems and techniques for pattern-based power-and-ground (PG) routing and via rule based via creation are described. A pattern for routing PG wires can be received. Next, an instantiation strategy may be received, wherein the instantiation strategy specifies an area of an integrated circuit (IC) design layout where PG wires based on the pattern are to be instantiated and specifies one or more net identifiers that are to be assigned to the instantiated PG wires. The PG wires can be instantiated in the IC design layout based on the pattern and the instantiation strategy. Additionally, a set of via rules can be received, wherein each via rule specifies a type of via that is to be instantiated at an intersection between two PG wires that are in two different metal layers. Next, one or more vias can be instantiated in the IC design layout based on the set of via rules. | 07-03-2014 |
20140189627 | INCREMENTAL CLOCK TREE SYNTHESIS - Methods and apparatuses are described for optimizing local clock skew, and/or for synthesizing clock trees in an incremental fashion. For optimizing local clock skew, the circuit design can be partitioned into clock skew groups. Next, for each clock skew group, an initial clock tree can be constructed that substantially minimizes worst case clock skew in the clock skew group, and then the initial clock tree can be further optimized by substantially minimizing worst case local clock skew in the clock skew group. For performing incremental clock tree synthesis, a portion of a clock tree in the circuit design can be selected based on a set of modifications to the circuit design. Next, a new clock tree can be determined to replace the selected portion of the clock tree. The circuit design can then be modified by replacing the selected portion of the clock tree with the new clock tree. | 07-03-2014 |
20140189624 | ABSTRACT CREATION - Systems and techniques for creating a circuit abstraction are described. During operation, an embodiment can identify a set of side loads based on a set of timing paths. According to one definition, a side load of a timing path is a circuit element that is not on the timing path (i.e., the timing path does not pass through the circuit element), but whose input is electrically connected to an output of at least one circuit element that is on the timing path. Next, the embodiment can creating the circuit abstraction by retaining circuit elements and nets on each timing path in the set of timing paths, and retaining an identifier for each side load in the set of side loads. The circuit abstraction can then be used to update timing information during one or more stages of an electronic design automation flow. | 07-03-2014 |
20140189620 | NETLIST ABSTRACTION - Systems and techniques for creating a netlist abstraction are described. During operation, an embodiment can receive a netlist for a circuit design, wherein circuit elements in the circuit design are organized in a logical hierarchy (LH). Next, the embodiment can receive a set of LH nodes in the LH. The embodiment can then create the netlist abstraction by, for each LH node in the set of LH nodes, replacing a portion of the netlist that is below the LH node by a star netlist, wherein the star netlist includes a center object that is electrically connected to a set of satellite objects, wherein each satellite object corresponds to a port of the LH node. | 07-03-2014 |
20140189617 | DISPLAYING A CONGESTION INDICATOR FOR A CHANNEL IN A CIRCUIT DESIGN LAYOUT - Methods and apparatuses are described for creating, editing, and viewing a floorplan of a circuit design. Specifically, some embodiments enable a user to perform a graphical operation at an inference point in a circuit design layout, wherein the location of the inference point is determined based on existing graphical objects in the circuit design layout. Some embodiments substantially instantaneously update a congestion indicator in a circuit design layout in response to modifying the circuit design layout. Some embodiments substantially instantaneously update pin locations of a block or partition in response to changing the size or shape of the block or partition. Some embodiments enable a user to view a circuit design layout based on the logical hierarchy, and also based on at least one additional attribute type such as voltage, power, or clock domain. | 07-03-2014 |
20140189616 | INCREMENTAL CONCURRENT PROCESSING FOR EFFICIENT COMPUTATION OF HIGH-VOLUME LAYOUT DATA - Some embodiments of the present invention overcome I/O bottlenecks of an EDA work flow by keeping layout data distributed during handoffs among different processing stages. Specifically, some embodiments leverage a concurrent computation paradigm where data is propagated incrementally between stages, and where data processing among consecutive stages and the I/O between stages are executed concurrently. Specifically, different data processing stages can partition the layout data differently, and portions of the layout data that are not required by a data processing stage can be either passed-through or passed-around the data processing stage. | 07-03-2014 |
20140181779 | TIMING BOTTLENECK ANALYSIS ACROSS PIPELINES TO GUIDE OPTIMIZATION WITH USEFUL SKEW - Techniques and systems for guiding circuit optimization are described. Some embodiments compute a set of aggregate slacks for a set of chains of logic paths in a circuit design. Each chain of logic paths starts from a primary input or a sequential circuit element that only launches a signal but does not capture a signal and ends at a primary output or a sequential circuit element that only captures a signal but does not launch a signal. Next, the embodiments guide circuit optimization of the circuit design based on the set of aggregate slacks. | 06-26-2014 |
20140181777 | AUTOMATIC CLOCK TREE ROUTING RULE GENERATION - Systems and techniques are described for automatically generating a set of non-default routing rules for routing a net in a clock tree based on one or more metrics. The metrics can include a congestion metric, a latency metric, a crosstalk metric, an electromigration metric, and a clock tree level. Next, the embodiments can generate the set of non-default routing rules for routing the net based on one or more metrics. A routing rule can specify how wide the wires are supposed to be and how far apart adjacent wires are to be placed. A non-default routing rule can specify a wire width that is different from the default width and/or specify a spacing (i.e., the distance between two wires) that is different from the default spacing. | 06-26-2014 |
20140181776 | WHAT-IF PARTITIONING AND TIMING - Methods and apparatuses are described for facilitating a user to explore and evaluate different options during floorplanning. Some embodiments display a graphical representation of a circuit design floorplan, wherein the graphical representation includes a set of blocks and a set of flylines between blocks, wherein each block corresponds to a portion of the circuit design, and wherein each flyline corresponds to one or more relationships between two blocks. Additionally, a set of metrics associated with one or more blocks or one or more flylines can be displayed. Next, in response to receiving a modification to one or more blocks in the graphical representation, the embodiments can update the set of metrics without performing expensive netlist modification, placement, routing, and/or propagation of timing information through multiple levels of logic, and then display the updated set of metrics. | 06-26-2014 |
20140181773 | SHAPING INTEGRATED WITH POWER NETWORK SYNTHESIS (PNS) FOR POWER GRID (PG) ALIGNMENT - Embodiments are described in which shaping is integrated with power network synthesis (PNS) for power grid (PG) alignment. Specifically, some embodiments create placement constraints based on the PG that is expected to be created by PNS, and then perform shaping (or perform legalization) on the circuit design based on the placement constraints. This ensures that the physical partitions (e.g., instances of multiply-instantiated-blocks) are aligned with the power grid during shaping. | 06-26-2014 |
20140181766 | MULTI-MODE SCHEDULER FOR CLOCK TREE SYNTHESIS - Techniques and systems for performing clock tree synthesis (CTS) across multiple modes are described. Some embodiments traverse one or more clock trees from the root of each clock tree to a set of sinks of the clock tree. During the traversal, each clock gate can be marked with a traversal level, and each sink can be marked with one or more clocks and one or more modes that are associated with the sink. A task queue can then be created based on the information collected during the clock tree traversal and populated with different types of tasks based on skew balancing requirements across different modes, and the task queue can be provided to a CTS engine to achieve high-quality skew-balanced clock trees across all modes. | 06-26-2014 |
20140181765 | LOOK-UP BASED BUFFER TREE SYNTHESIS - Systems and techniques are described for performing buffer tree synthesis. Some embodiments create a lookup table based on information contained in a cell library. The lookup table is then used during buffer tree synthesis. | 06-26-2014 |
20140181762 | LITHOGRAPHY AWARE LEAKAGE ANALYSIS - A method for performing leakage analysis includes receiving information specifying an integrated circuit. A neighborhood of shapes associated with the integrated circuit is then determined Leakage information associated with the integrated circuit is generated based on the neighborhood of shapes. The neighborhood of shapes may be determined by determining a first set of spacings to a boundary of a first cell from an internal shape. A second set of spacings may be determined from the boundary of the first cell to a shape of a second cell. A lithography process may be characterized using the first and second set of spacings. | 06-26-2014 |
20140181447 | Structured Block Transfer Module, System Architecture, and Method for Transferring - Structured block transfer module, system architecture, and method for transferring content or data. Circuit allowing content in one memory to be shifted, moved, or copied to another memory with no direction from a host, the circuit comprising: a connection manager, at least one copy engine, and a connection between the connection manager and the copy engine. Method for transferring the contents of one of a number of blocks of source memory to one of a number of possible destination memories comprising: selecting source memory; selecting available destination memory; marking the selected destination as no longer available; copying contents of selected source memory into selected destination memory; and marking selected source as available. | 06-26-2014 |
20140181343 | Structured Block Transfer Module, System Architecture, and Method for Transferring - Structured block transfer module, system architecture, and method for transferring content or data. Circuit allowing content in one memory to be shifted, moved, or copied to another memory with no direction from a host, the circuit comprising: a connection manager, at least one copy engine, and a connection between the connection manager and the copy engine. Method for transferring the contents of one of a number of blocks of source memory to one of a number of possible destination memories comprising: selecting source memory; selecting available destination memory; marking the selected destination as no longer available; copying contents of selected source memory into selected destination memory; and marking selected source as available. | 06-26-2014 |
20140173545 | PLACING TRANSISTORS IN PROXIMITY TO THROUGH-SILICON VIAS - Roughly described, the invention involves ways to characterize, take account of, or take advantage of stresses introduced by TSV's near transistors. The physical relationship between the TSV and nearby transistors can be taken into account when characterizing a circuit. A layout derived without knowledge of the physical relationships between TSV and nearby transistors, can be modified to do so. A macrocell can include both a TSV and nearby transistors, and a simulation model for the macrocell which takes into account physical relationships between the transistors and the TSV. A macrocell can include both a TSV and nearby transistors, one of the transistors being rotated relative to others. An IC can also include a transistor in such proximity to a TSV as to change the carrier mobility in the channel by more than the limit previously thought to define an exclusion zone. | 06-19-2014 |
20140165024 | STATISTICAL FORMAL ACTIVITY ANALYSIS WITH CONSIDERATION OF TEMPORAL AND SPATIAL CORRELATIONS - Techniques for statistical formal activity analysis with consideration of temporal and/or spatial correlations are described herein. According to one embodiment, a machine-implemented method for circuit analysis comprises unrolling a sequential circuit having a feedback loop into a plurality of unrolled circuits and introducing a spatial correlation via an encoding circuit coupled to the plurality of unrolled circuits for an activity analysis of the sequential circuit, the spatial correlation representing a dependency relationship between logic states of an input and logic states of other signals. | 06-12-2014 |
20140165023 | METHOD OF RECORDING AND REPLAYING CALL FRAMES FOR A TEST BENCH - A computer-implemented method to debug testbench code of a testbench associated with a circuit design by recording a trace of call frames along with activities of the circuit design. By correlating and displaying the recorded trace of call frames, the method enables users to easily trace as execution history of subroutines executed by the testbench thereby to debug the testbench code. In addition, users can trace source code of the testbench code by using the recorded trace of call frames. Furthermore, users can debug the testbench code utilizing a virtual simulation, which is done by post-processing records of the virtual simulation stored in a database. | 06-12-2014 |
20140165019 | SEMICONDUCTOR HOLD TIME FIXING - Computer implemented techniques are disclosed for fixing signal hold-time violations in semiconductor chips. Analysis includes estimation of hold-time requirements using ideal clocks. Allocation of placement regions within the design and near the macro circuits allows for later placement and wiring use during layout hold-time fixing. The placement region sizes are based on estimates of the needed buffers. Nets, within the design for detail routing, are ordered such that nets with hold-time violations are wired later, thus fixing hold-time violations without scaling or adding further buffers. Hold times are re-evaluated once wiring of track routes is complete. | 06-12-2014 |
20140157216 | MANAGING MODEL CHECKS OF SEQUENTIAL DESIGNS - A method, system or computer usable program product for model checking a first circuit model including determining whether the first circuit model is functionally equivalent to one of a set of prior circuit models stored in persistent memory, and in response to determining functional equivalence, utilizing a processor to provide test results for the functionally equivalent prior circuit model. | 06-05-2014 |
20140157215 | SYSTEM AND METHOD OF EMULATING MULTIPLE CUSTOM PROTOTYPE BOARDS - An emulation system integrates multiple custom prototyping boards for emulating a circuit design. A first custom prototyping board including at least one FPGA and an interface connected to a first set of wires coupling to the at least one FPGA. A second custom prototyping board includes at least one second FPGA and an interface connected to a second set of wires coupling to the at least second FPGA. An adaptor board connects to the first custom prototyping board and the second custom prototyping board through the first interface and the second interface. The adapter board controls emulation of the circuit design and controls communication through the partitioned circuit using at least one of the first set of wires and at least one the second set of wires. | 06-05-2014 |
20140156249 | MODELING A BUS FOR A SYSTEM DESIGN INCORPORATING ONE OR MORE PROGRAMMABLE PROCESSORS - Systems and methods for modeling a bus for a system design are provided. In an embodiment, the method operates by accepting a virtual bus model, wherein the model simulates behavior for a bus master and slave device, such that the model accurately simulates the timing and behavior of the transfer of data from master to slave, and, from slave to master devices. The method routes a transaction issued by the master device to the slave device. The transaction has storage for transaction data, or a pointer to transaction data, to be transferred through the transaction. The transaction data is transferred in one or more data payloads and the sender of data sets the length of data payloads to be returned. The data payloads are sent from the sender of data to the receiver of data and may contain one or more bus data beats. This method accurately models the bus timing and behavior of the delivery of one or more data beats as one data payload. | 06-05-2014 |
20140149955 | LOW-OVERHEAD MULTI-PATTERNING DESIGN RULE CHECK - Roughly described, a system enables quick and accurate depiction to a user of multi-patterning layout violations so that they may be corrected manually and in real time, and without interfering with normal manual editing process. In one embodiment, the system involves iteratively building tree structures with nodes identifying islands and arcs identifying multi-patterning spacing violations between the connected islands. The system detects coloring violations during the building of these tree structures, using the relationships previously inserted. The coloring violations preferably are reported to a user in the form of visual indications of the cycles among the candidate spacing violations, with the candidate spacing violations also themselves indicated visually and individually. The user can see intuitively how to move the islands around, and in which directions and by what distance, in order to remove a multi-patterning spacing violation and thereby break the cycle. | 05-29-2014 |
20140145253 | ASYMMETRIC DENSE FLOATING GATE NONVOLATILE MEMORY WITH DECOUPLED CAPACITOR - A nonvolatile memory (“NVM”) bitcell with one or more active regions capacitively coupled to the floating gate but that are separated from both the source and the drain. The inclusion of capacitors separated from the source and drain allows for improved control over the voltage of the floating gate. This in turn allows CHEI (or IHEI) to be performed with much higher efficiency than in existing bitcells, thereby the need for a charge pump to provide current to the bitcell, ultimately decreasing the total size of the bitcell. The bitcells may be constructed in pairs, further reducing the space requirements of the each bitcell, thereby mitigating the space requirements of the separate capacitor/s. The bitcell may also be operated by CHEI (or IHEI) and separately by BTBT depending upon the voltages applied at the source, drain, and capacitor/s. | 05-29-2014 |
20140143743 | Automated Circuit Design - A method implemented on a data processing system for circuit synthesis is discussed. In one embodiment, the method comprises determining a net of a circuit design, the net driving one or more first loads to use a first type of routing resources and one or more second loads to use a second type of routing resources, and splitting the net into a first net and a second net, the first net driving the one or more first loads, the second net driving the one or more second loads. | 05-22-2014 |
20140137056 | Packet Switch Based Logic Replication - A method for debugging comprising configuring a switching logic mapping source subchannels to destination subchannels, as virtual channels to forward the packets from the source subchannels to the destination subchannels. The method further comprising configuring a single queue coupled to the switching logic to record packets from the source subchannels into a packet stream for a delay period to distribute to the destination subchannels for the destination logic to emulate the source logic synchronously with the plurality of clock domains with the delay period. | 05-15-2014 |
20140136900 | Method for Ranking Fault-Test Pairs Based on Waveform Statistics in a Mutation-Based Test Program Evaluation System - Ranking of fault-test pairs is performed using first and second multitudes of waveform statistics. The first multitude of waveform statistics includes first value-change information regarding variations in logics HIGH and LOW for each bit of each reference output resulting from a test run of the design code. The second multitude of waveform statistics includes second value-change information regarding variations in logics HIGH and LOW for each bit of each faulty output resulting from a test run of the design code injected with a fault. Relative differences between the first and second multitudes of waveform statistics for each bit of each faulty output with respect to the corresponding reference output are determined. A waveform difference based on the relative differences for each signal of each faulty output is determined. A ranking result of fault-test pairs is determined according to the waveform differences of the faulty outputs. | 05-15-2014 |
20140115556 | ANALYSIS OF STRESS IMPACT ON TRANSISTOR PERFORMANCE - Roughly described, a method for approximating stress-induced mobility enhancement in a channel region in an integrated circuit layout, including approximating the stress at each of a plurality of sample points in the channel, converting the stress approximation at each of the sample points to a respective mobility enhancement value, and averaging the mobility enhancement values at all the sample points. The method enables integrated circuit stress analysis that takes into account stresses contributed by multiple stress generation mechanisms, stresses having vector components other than along the length of the channel, and stress contributions (including mitigations) due to the presence of other structures in the neighborhood of the channel region under study, other than the nearest STI interfaces. The method also enables stress analysis of large layout regions and even full-chip layouts, without incurring the computation costs of a full TCAD simulation. | 04-24-2014 |
20140115304 | COMPRESSED INSTRUCTION CODE STORAGE - Computer implemented techniques are disclosed for identification of repeated binary strings and for storing those binary strings in order to compress code. The binary strings can be longer instructions, data, or addresses. A table of binary strings is generated based on repeated occurrences, and a reference index is provided for accessing specific entries within the table. An opcode uses a shorter string as an index through which to access the table. The longer string is executed when the longer string is an instruction. When the longer string is an address or data, the appropriate address or data are accessed. | 04-24-2014 |
20140114634 | MODELING AND CORRECTING SHORT-RANGE AND LONG-RANGE EFFECTS IN E-BEAM LITHOGRAPHY - Processes and apparatuses are described for modeling and correcting electron-beam (e-beam) proximity effects during e-beam lithography. An uncalibrated e-beam model, which includes a long-range component and a short-range component, can be calibrated based on one or more test layouts. During correction, a first resist intensity map can be computed based on the long-range component of the calibrated e-beam model and a mask layout. Next, a target pattern in the mask layout can be corrected by, iteratively: (1) computing a second resist intensity map based on the short-range component of the calibrated e-beam model and the target pattern; (2) obtaining a combined resist intensity map by combining the first resist intensity map and the second resist intensity map; and (3) adjusting the target pattern based on the combined resist intensity map and the design intent. | 04-24-2014 |
20140109040 | Generation of Instruction Set from Architecture Description - Generating an instruction set for an architecture. A hierarchical description of an architecture is accessed. Groups in the hierarchical description that can be pre-encoded without increasing final width of said instruction set are pre-encoded. The hierarchical description is permutated into a plurality of variations. Each variation comprises a leaf-group and one or more sub-graphs to be encoded. For each said variation, the leaf-group and the one or more sub-graphs are encoded to produce a potential instruction set for each variation. One of the potential instruction sets is selected. | 04-17-2014 |
20140109034 | Timing Closure Methodology Including Placement with Initial Delay Values - An automated method for designing an integrated circuit layout using a computer based upon an electronic circuit description and based upon cells which are selected from a cell library, each of the cells having an associated area, comprising the steps of: (a) placing each of the cells in the integrated circuit layout so that the cells can be coupled together by wires to form a circuit path having an associated predetermined delay constraint wherein the cells are coupled together based upon the electronic circuit description input to the computer; (b) connecting the cells together with the wires to form the circuit path; and (c) adjusting an area of at least one of the cells to satisfy the associated predetermined delay constraint of the circuit path. | 04-17-2014 |
20140109027 | ESD/ANTENNA DIODES FOR THROUGH-SILICON VIAS - Roughly described, an antenna diode is formed at least partially within the exclusion zone around a TSV, and is connected to the TSV by way of a metal 1 layer conductor at the same time that the TSV is connected to either the gate poly or a diffusion region of one or more transistors placed outside the exclusion zone. | 04-17-2014 |
20140108870 | Concurrent Host Operation And Device Debug Operation WIth Single Port Extensible Host Interface (XHCI) Host Controller - An improved USB host controller and method supports concurrent host and device debug operations with only one usable USB port. The described embodiments save silicon cost and avoid additional connectors, which are undesirable in ever-smaller devices. | 04-17-2014 |
20140101638 | AUTOMATIC GENERATION OF INSTRUCTION-SET DOCUMENTATION - A method and system for the automatic generation of user guides. Specifically, the method of the present invention includes accessing an abstract processor model of a processor, wherein said abstract processor model is represented using a hierarchical architecture description language (ADL). The abstract processor model includes a plurality of instructions arranged in a hierarchical structure. An internal representation of the abstract processor model is generated by flattening the abstract processor model. The flattening process generates a plurality of rules grouped by common convergent instructions. Each rule describes an instruction path through the hierarchical structure that converges at a corresponding convergent instruction. An instruction-set documentation is automatically generated from the plurality of rules, wherein the instruction-set documentation is arranged convergent instruction by convergent instruction. | 04-10-2014 |
20140095101 | AUGMENTED POWER-AWARE DECOMPRESSOR - Decompressor circuitry includes a first segment and a second segment each comprising memory elements (MEs) and (i) said first segment receives the plurality of static variables originating from the tester, and (ii) and said second segment, receives the plurality of dynamic variables originating from the tester. | 04-03-2014 |
20140092507 | MITIGATING CROSS-DOMAIN TRANSMISSION OF ELECTROSTATIC DISCHARGE (ESD) EVENTS - An electrostatic discharge (ESD) device is implemented within a power domain to mitigate imparting ESD induced voltages on other power domains for reducing integrated circuit (IC) failures. A first power domain includes an interface with a first terminal where an ESD event is received. The interface includes a second terminal coupled to a component within a second power domain. The ESD device is disposed between the first terminal and second terminal to intercept the ESD event. In one embodiment, the ESD device includes a blocking device. The blocking device operatively decouples the first terminal and second terminal in response to a trigger signal received during an ESD event. By operatively decoupling the terminals, transmission of the ESD induced voltages is substantially mitigated. Embodiments of the ESD device can be implemented using standard cell libraries to simplify integration. | 04-03-2014 |
20140089868 | AUTOMATED REPAIR METHOD AND SYSTEM FOR DOUBLE PATTERNING CONFLICTS - A method of performing double patterning (DPT) conflict repairs is described. In this method, even cycles adjacent to odd cycles in a layout can be identified (also called adjacent even/odd cycles herein). The identifying can include forming graph constructs of the layout. Route guidances for break-link operations and split-node operations can be prioritized for the adjacent even/odd cycles. A list including the route guidances for the break-link operations and the split-node operations can be generated. The list can be ordered based on the prioritizing. | 03-27-2014 |
20140082579 | ARCHITECTURAL PHYSICAL SYNTHESIS - Methods and apparatuses to design an integrated circuit are discussed. In one embodiment, the method of designing an integrated circuit comprises partitioning a chip resource into a plurality of sections, and calculating the rank of the sections based on a quality metric. The method further comprises removing the sections with the lowest ranks from consideration by a placement transform. | 03-20-2014 |
20140075402 | Method of Fast Analog Layout Migration - A computer implemented method for forming an integrated circuit (IC) layout is presented. The method includes forming a constraint tree when a computer is invoked to receive a first layout of the IC and generating a second layout of the IC in accordance with the constraint tree. | 03-13-2014 |
20140075398 | Method and Apparatus for Process Window Modeling - A photolithographic modeling process is disclosed. Optical and non-optical parts of a model of the photolithographic process are calibrated. With the non-optical part of the model one or more model corrections are determined between (i) modeled critical dimension data from an aerial image generated by the optical part of the model, and (ii) empirical critical dimension data from tangible structures made at only a first process combination of a first dose and a first defocus in the photolithographic process. Critical dimension data of the photolithographic process are predicted at a second process combination of a second dose and a second defocus in the photolithographic process. | 03-13-2014 |
20140068619 | Scheduling in a multicore architecture - This invention relates to scheduling threads in a multicore processor. Executable transactions may be scheduled using at least one distribution queue, which lists executable transactions in order of eligibility for execution, and multilevel scheduler which comprises a plurality of linked individual executable transaction schedulers. Each of these includes a scheduling algorithm for determining the most eligible executable transaction for execution. The most eligible executable transaction is outputted from the multilevel scheduler to the at least one distribution queue. | 03-06-2014 |
20140068533 | INFORMATION THEORETIC SUBGRAPH CACHING - Computer-implemented techniques are disclosed for verifying circuit designs using subgraph caching. A device under test (DUT) is modeled as a graph. The graph is partitioned into one or more subgraphs and problems are generated for each subgraph. Graph and subgraph problem generation is repeated numerous times throughout the verification process. Problems and sub-problems are generated and solved. When a subgraph problem is solved, the problem's variables, values, and information can be stored in a cache. The storage can be based on entropy of variables used in the graph and subgraph problems. The subgraph problem storage cache can be searched for previously stored problems which match another problem in need of a solution. By retrieving subproblem variables, values, and information from the cache, the computational overhead of circuit design verification is reduced as problems are reused. Caching can be accomplished using an information theoretic approach. | 03-06-2014 |
20140065821 | LATCH-UP SUPPRESSION AND SUBSTRATE NOISE COUPLING REDUCTION THROUGH A SUBSTRATE BACK-TIE FOR 3D INTEGRATED CIRCUITS - Roughly described, an integrated circuit device has a conductor extending entirely through the substrate, connected on one end to the substrate topside surface and on the other end to the substrate backside surface. In various embodiments the conductor is insulated from all RDL conductors on the backside of the substrate, and/or is insulated from all conductors and device features on any below-adjacent chip in a 3D integrated circuit structure. Methods of fabrication are also described. | 03-06-2014 |
20140061943 | LATCH-UP SUPPRESSION AND SUBSTRATE NOISE COUPLING REDUCTION THROUGH A SUBSTRATE BACK-TIE FOR 3D INTEGRATED CIRCUITS - Roughly described, an integrated circuit device has a conductor extending entirely through the substrate, connected on one end to the substrate topside surface and on the other end to the substrate backside surface. In various embodiments the conductor is insulated from all RDL conductors on the backside of the substrate, and/or is insulated from all conductors and device features on any below-adjacent chip in a 3D integrated circuit structure. Methods of fabrication are also described. | 03-06-2014 |
20140059508 | Determining A Design Attribute By Estimation And By Calibration Of Estimated Value - A computer-implemented method of determining an attribute of a circuit includes using a computationally expensive technique to simulate the attribute (such as timing delay or slew) of a portion of the circuit, at predetermined values of various parameters (e.g. nominal values of channel length or metal width), to obtain at least a first value of the attribute. The method also uses a computationally inexpensive technique to estimate the same attribute, thereby to obtain at least a second value which is less accurate than the first value. Then the computationally inexpensive technique is repeatedly used on other values of the parameter(s), to obtain a number of additional second values of the attribute. Applying to the additional second values, a function obtained by calibrating the at least one second value to the at least one first value, can yield calibrated estimates very quickly, which represent the attribute's variation relatively accurately. | 02-27-2014 |
20140059399 | TEST DESIGN OPTIMIZER FOR CONFIGURABLE SCAN ARCHITECTURES - Roughly described, a scan-based test architecture is optimized in dependence upon the circuit design under consideration. In one embodiment, a plurality of candidate test designs are developed. For each, a plurality of test vectors are generated in dependence upon the circuit design and the candidate test design, preferably using the same ATPG algorithm that will be used downstream to generate the final test vectors for the production integrated circuit device. A test protocol quality measure such as fault coverage is determined for each of the candidate test designs, and one of the candidate test designs is selected for implementation in an integrated circuit device in dependence upon a comparison of such test protocol quality measures. Preferably, only a sampling of the full set of test vectors that ATPG could generate, is used to determine the number of potential faults that would be found by each particular candidate test design. | 02-27-2014 |
20140056076 | VERY DENSE NONVOLATILE MEMORY BITCELL - An asymmetric non-volatile memory bitcell is described. The bitcell comprises source and drain regions comprising carriers of the same conductivity type. A floating gate rests on top of the well, and extends over a channel region, and at least a portion of the source and drain regions. The drain region comprises additional carriers of a second conductivity type, allowing band to band tunneling. The source region comprises additional carriers of a first conductivity type, thereby increasing source-gate capacitance. Thus, the bitcell incorporates a select device, thereby decreasing the overall size of the bitcell. The bitcell may be created without any additional CMOS process steps, or through the addition of a single extra mask step. | 02-27-2014 |
20140054722 | FINFET CELL ARCHITECTURE WITH POWER TRACES - A finFET block architecture suitable for use of a standard cell library, is based on an arrangement including a first set of semiconductor fins in a first region of the substrate having a first conductivity type, and a second set of semiconductor fins in a second region of the substrate, the second region having a second conductivity type. A patterned gate conductor layer including gate traces in the first and second regions, arranged over channel regions of the first and second sets of semiconductor fins is used for transistor gates. Patterned conductor layers over the gate conductor layer are arranged in orthogonal layout patterns, and can include a plurality of floating power buses over the fins in the first and second regions. | 02-27-2014 |
20140053124 | THERMAL ANALYSIS BASED CIRCUIT DESIGN - Methods and apparatuses for circuit design to reduce power usage, such as reducing temperature dependent power usage, and/or to improve timing, such as reducing temperature dependent delay or transition time. At least one embodiment of the method implemented on a data processing system for circuit design, the method comprises determining for a first design of a circuit a first temperature solution and a first power dissipation solution, the first power dissipation solution and the first temperature solution being interdependent, and transforming the first design of the circuit into a second design of the circuit using the first temperature solution to reduce leakage power of the circuit under one or more design constraints. | 02-20-2014 |
20140053120 | ARCHITECTURAL PHYSICAL SYNTHESIS - The present invention discloses methods and apparatuses to design an integrated circuit. According to one aspect, a method of designing an integrated circuit comprises determining a state of a design of the integrated circuit at a high level design representation of the integrated circuit, wherein the state of the design of the integrated circuit comprises a netlist with at least one of timing data, resource information, placement information, routing information, and power data. The method further comprises determining a first transform for the state, changing the state of the design at the high level design representation of the integrated circuit using the first transform, and determining a second transform based on the changed state. | 02-20-2014 |
20140047403 | Statistical Corner Evaluation For Complex On-Chip Variation Model - The invention provides a method for performing statistical static timing analysis using a novel on-chip variation model, referred to as Sensitivity-based Complex Statistical On-Chip Variation (SCS-OCV). | 02-13-2014 |
20140046647 | ACTIVE TRACE ASSERTION BASED VERIFICATION SYSTEM - A method is presented for responding to user input by displaying when a circuit has a property expressed by an assertion based on data indicating values of signals of the circuit at a succession of times. The assertion expresses the property as a first sequence of expressions, and separately defines for each expression a corresponding evaluation time relative to the succession of times at which the expression is to be evaluated. The circuit has the property only if every expression of the first sequence evaluates true at its corresponding evaluation time. The method includes displaying a representation of each expression of the first sequence and identifying each variable that caused that expression to evaluate false and distinctively marking that variable's symbol relative to other variable symbols within the display for each expression of the first sequence that evaluates false at its corresponding evaluation time. | 02-13-2014 |
20140040851 | OPTIMIZING A CIRCUIT DESIGN FOR DELAY USING LOAD-AND-SLEW-INDEPENDENT NUMERICAL DELAY MODELS - Systems and techniques are described for optimizing a circuit design. Specifically, gate sizes in the circuit design are optimized by iteratively performing a set of operations that include, but are not limited to: selecting a portion of the circuit design (e.g., according to a reverse-levelized processing order), selecting an input-to-output arc of a driver gate in the portion of the circuit design, selecting gates in the portion of the circuit design for optimization, modeling a gate optimization problem based on the selected input-to-output arc of the driver gate and the selected gates, solving the gate optimization problem to obtain a solution using one or more solvers, and discretizing the solution. Discretizing the solution involves identifying library cells that exactly or closely match the gate sizes specified in the solution. These library cells can then be used to model other gate optimization problems in the current or subsequent iterations. | 02-06-2014 |
20140035053 | FINFET CELL ARCHITECTURE WITH INSULATOR STRUCTURE - A finFET block architecture includes a first set of semiconductor fins having a first conductivity type, and a second set of semiconductor fins having a second conductivity type. An inter-block insulator is placed between outer fins of the first and second sets. A patterned gate conductor layer includes a first plurality of gate traces extending across the set of fins in the first block without crossing the inter-block insulator, and a second plurality of gate traces extending across the set of fins in the second block without crossing the inter-block insulator. Patterned conductor layers over the gate conductor layer are arranged in orthogonal layout patterns, and include an inter-block connector arranged to connect gate traces in the first and second blocks. | 02-06-2014 |
20140033162 | DETERMINING OPTIMAL GATE SIZES BY USING A NUMERICAL SOLVER - Systems and techniques are described for optimizing a circuit design by using a numerical solver. The gates sizes are optimized by modeling a set of gate optimization problems and solving the set of gate optimization problems by using a numerical solver. Modeling each gate optimization problem can include selecting a portion of the circuit design that includes a driver gate that drives one or more inputs of each gate in a set of gates, and modeling a gate optimization problem for the portion of the circuit design based on circuit information for the portion of the circuit design. A differentiable objective function for delay can be created using numerical models for the delays in the circuit. In some embodiments, gradients of the differentiable objective function can be computed to enable the use of a conjugate-gradient-based numerical solver. | 01-30-2014 |
20140033161 | ACCURATE APPROXIMATION OF THE OBJECTIVE FUNCTION FOR SOLVING THE GATE-SIZING PROBLEM USING A NUMERICAL SOLVER - Systems and techniques are described for optimizing a circuit design by using a numerical solver. Some embodiments construct a set of lower bound expressions for a parameter that is used in an approximation of an objective function. Next, the embodiments evaluate the set of lower bound expressions to obtain a set of lower bound values. The embodiments then determine a maximum lower bound value from the set of lower bound values. Next, while solving a gate sizing problem using the numerical solver, the embodiments evaluate the approximate objective function and the partial derivatives of the approximate objective function by using the maximum lower bound value of the parameter. The maximum lower bound value of this parameter determines the accuracy of the approximation of the objective function. | 01-30-2014 |
20140033158 | Multiple Level Spine Routing - A computer implemented method for routing a net includes selecting, using one or more computer systems, a first spine routing track from a first multitude of routing tracks in accordance with a first cost function, and further in accordance with data associated with the net and the first multitude of routing tracks. The method further includes generating, using one or more computer systems, a first spine wire on the selected first spine routing track. | 01-30-2014 |
20140033157 | Multiple Level Spine Routing - A computer implemented method for routing a net includes generating, using one or more computer systems, a first wire associated with the net in accordance with data associated with the net including a multitude of pins and partitioning, using the one or more computer systems, the multitude of pins into at least a first group of pins in accordance with a first cost function. The method further includes connecting, using the one or more computer systems, a second wire associated with the first group of pins to the first wire, and connecting, using the one or more computer systems, a third wire from a pin of the first group of pins to the second wire. | 01-30-2014 |
20140033156 | ROUTING METHOD FOR FLIP CHIP PACKAGE AND APPARATUS USING THE SAME - Disclosed herein are rouging methods and devices for a flip-chip package. The flip chip includes several outer pads and several inner pads. The routing method includes: setting an outer sequence based on the arrangement order of the outer pads; setting several inner sequences based on the connection relationships between inner pads and the outer pads; calculating the longest common subsequence of each inner sequence and the outer sequence, defining the connection relationships between the inner pads and the outer pads corresponding to the longest common subsequence as direct connections, and defining the connection relationships between the inner pads and the outer pads that do not correspond to the longest common subsequence as detour connections; establishing the routing scheme of the flip chip based on the connection relationships between the inner pads and the outer pads. | 01-30-2014 |
20140033151 | EQUIVALENCE CHECKING BETWEEN TWO OR MORE CIRCUIT DESIGNS THAT INCLUDE DIVISION AND/OR SQUARE ROOT CIRCUITS - Methods and apparatuses are described for proving equivalence between two or more circuit designs that include one or more division circuits and/or one or more square-root circuits. Some embodiments analyze the circuit designs to determine an input relationship between the inputs of two division (or square-root) circuits. Next, the embodiments determine an output relationship between the outputs of two division (or square-root) circuits based on the input relationship. The embodiments then prove equivalence between the circuit designs by using the input and output relationships. | 01-30-2014 |
20140033150 | FORMAL VERIFICATION OF BIT-SERIAL DIVISION AND BIT-SERIAL SQUARE-ROOT CIRCUIT DESIGNS - Methods and apparatuses are described for formally verifying a bit-serial division circuit design or a bit-serial square-root circuit design. Some embodiments formally verify a bit-serial division circuit design using a set of properties that can be efficiently proven using a bit-level solver. In some embodiments, the set of properties that are used for verifying a bit-serial division circuit design does not include any terms that multiply a w-bit partial quotient with the divisor. Some embodiments formally verify a bit-serial square-root circuit design using a set of properties that can be efficiently proven using a bit-level solver. In some embodiments, the set of properties that are used for verifying a bit-serial square-root circuit design does not include any terms that compute a square of a w-bit partial square-root. | 01-30-2014 |
20140032199 | Fast 3D Mask Model Based on Implicit Countors - Computer-readable medium and methods for photolithographic simulation of scattering. A design layout comprising a layout polygon is received. A skeleton representation of a mask shape that is created responsive to e-beam writing of the layout polygon is generated. The skeleton representation is defined by a plurality of skeleton points. Individual scattering patterns for the skeleton points are selected from a lookup table of pre-determined scattering patterns. Each of the individual scattering patterns representing an amount of optical scattering for a corresponding one of the skeleton points. A simulated wafer image is produced responsive to the individual scattering patterns. | 01-30-2014 |
20140032156 | LAYOUT-AWARE TEST PATTERN GENERATION AND FAULT DETECTION - Methods and apparatuses to generate test patterns for detecting faults in an integrated circuit (IC) are described. During operation, the system receives a netlist and a layout for the IC. The system then generates a set of faults associated with the netlist to model a set of defects associated with the IC. Next, the system determines a set of likelihoods of occurrence for the set of faults based at least on a portion of the layout associated with each fault in the set of faults. The system subsequently generates a set of test patterns to target the set of faults, wherein the set of test patterns are generated based at least on the set of likelihoods of occurrence associated with the set of faults. | 01-30-2014 |
20140026141 | RESOURCE MANAGEMENT IN A MULTICORE ARCHITECTURE - A resource management and task allocation controller for installation in a multicore processor having a plurality of interconnected processor elements providing resources for processing executable transactions, at least one of said elements being a master processing unit, the controller being adapted to communicate, when installed, with each of the processor elements including the master processing unit, and comprising control logic for allocating executable transactions within the multicore processor to particular processor elements in accordance with pre-defined allocation parameters. | 01-23-2014 |
20140025857 | RESOURCE MANAGEMENT IN A MULTICORE ARCHITECTURE - A resource management and task allocation controller for installation in a multicore processor having a plurality of interconnected processor elements providing resources for processing executable transactions, at least one of said elements being a master processing unit, the controller being adapted to communicate, when installed, with each of the processor elements including the master processing unit, and comprising control logic for allocating executable transactions within the multicore processor to particular processor elements in accordance with pre-defined allocation parameters. | 01-23-2014 |
20140019925 | METHOD FOR TESTING A COMPUTER PROGRAM - A method for testing a circuit specification after changing a first version of the circuit specification into a second version of the circuit specification due to a revision of the circuit specification includes receiving a first set of mutations that can be or have been inserted into the first version of the circuit specification and a second set of mutations that can be inserted into the second version of the circuit specification computer program. Changed and unchanged mutations are identified in the first set of mutations and in the second set of mutations based on a comparison between the second version of the circuit specification and against the first version of the circuit specification. Information configured to test the second version of the circuit specification is generated using at least a portion of the identified mutations classified as the changed mutations. | 01-16-2014 |
20140015135 | SELF-ALIGNED VIA INTERCONNECT USING RELAXED PATTERNING EXPOSURE - Self-aligned via interconnects using relaxed patterning exposure. In accordance with a first method embodiment, a method for controlling a computer-aided design (CAD) system for designing physical features of an integrated circuit includes accessing a first pattern for first metal traces on a first metal layer, accessing a second pattern for second metal traces on a second metal layer, vertically adjacent to the first metal layer and accessing a precise pattern of intended interconnections between the first and second metal traces. The precise pattern of intended interconnections is operated on to form an imprecise via pattern that indicates a plurality of general areas in which vias are allowed. The imprecise via pattern is for use in an integrated circuit manufacturing process to form, in conjunction with operations to form the first and second metal layers, a plurality of self-aligned vias for interconnecting the intended interconnections. | 01-16-2014 |
20140007037 | ESTIMATING OPTIMAL GATE SIZES BY USING NUMERICAL DELAY MODELS | 01-02-2014 |
20140003133 | SRAM LAYOUTS | 01-02-2014 |
20130346056 | Generation of Memory Structural Model Based on Memory Layout - A memory structural model is generated directly from memory configuration information and memory layout information in an efficient manner. Information on strap distribution is generated by analyzing configuration information of the memory and the corresponding memory layout. Information on scrambling of addresses in the memory layout is generated by programming the memory layout with physical bit patterns, extracting corresponding logical bit patterns and then analyzing the discrepancy between the physical bit patterns and the logical bit patterns. The strap distribution information and the address scrambling information are combined into the memory structural model used for designing an efficient test and repair engine. | 12-26-2013 |
20130346046 | Simulation with Dynamic Run-Time Accuracy Adjustment - Systems and methods for simulation with dynamic run-time accuracy adjustment. In one embodiment, a first portion of a sequence of software instruction is simulated by a first simulation model, during a simulation. During the same simulation, a second portion of the sequence is simulated by a second simulation model. State information may be transferred from the first simulation model to the second simulation model. A change from simulating the first portion of a sequence of software instructions by the first simulation model to simulating the second portion of the sequence by the second simulation model may be made responsive to a computer-based determination of an advantage obtained by the change. | 12-26-2013 |
20130339915 | CAPACITANCE EXTRACTION FOR ADVANCED DEVICE TECHNOLOGIES - A method and apparatus to provide a capacitance to a design an integrated circuit is described. In one embodiment, the method receive a layout of the integrated circuit and applying canonical hierarchical models to the layout, wherein the canonical hierarchical models include a first type canonical model to capture a first capacitance of a device having a plurality of first conductors and a second type canonical model to capture a second capacitance between at least a portion of the device and one or more second conductors of the integrated circuit. The method further includes determining a capacitance for the layout based on the applying. | 12-19-2013 |
20130334613 | N-CHANNEL AND P-CHANNEL END-TO-END FINFET CELL ARCHITECTURE - A finFET block architecture uses end-to-end finFET blocks. A first set of semiconductor fins having a first conductivity type and a second set of semiconductor fins having a second conductivity type can be aligned end-to-end. An inter-block isolation structure separates the semiconductor fins in the first and second sets. The ends of the fins in the first set are proximal to a first side of the inter-block isolation structure and ends of the fins in the second set are proximal to a second side of the inter-block isolation structure. A patterned gate conductor layer includes a first gate conductor extending across at least one fin in the first set of semiconductor fins, and a second gate conductor extending across at least one fin in the second set of semiconductor fins. The first and second gate conductors are connected by an inter-block conductor. | 12-19-2013 |
20130334610 | N-CHANNEL AND P-CHANNEL END-TO-END FINFET CELL ARCHITECTURE WITH RELAXED GATE PITCH - A finFET block architecture uses end-to-end finFET blocks in which the fin lengths are at least twice the contact pitch, whereby there is enough space for interlayer connectors to be placed on the proximal end and the distal end of a given semiconductor fin, and on the gate element on the given semiconductor fin. A first set of semiconductor fins having a first conductivity type and a second set of semiconductor fins having a second conductivity type can be aligned end-to-end. Interlayer connectors can be aligned over corresponding semiconductor fins which connect to gate elements. | 12-19-2013 |
20130328117 | FLOATING GATE NON-VOLATILE MEMORY BIT CELL - A solid-state non-volatile memory (NVM) device includes a memory bit cell. The memory bit cell includes a field effect transistor (FET) fabricated on a substrate and having a floating gate. The floating gate includes a thick oxide layer. The FET includes drain and source, each fabricated within the substrate and coupled to the floating gate and a channel region with native doping. The drain is fabricated to have a halo region. A method for fabricating a solid-state NVM device includes fabricating solid state device including NVM bit cell which provides multiple storage and includes an FET on substrate. The method also includes fabricating floating gate of the FET including thick gate oxide layer, and fabricating drain and source of FET within the substrate, drain and source coupled to the floating gate and channel region with native doping. Further, the method includes fabricating halo region within the substrate at the drain. | 12-12-2013 |
20130326449 | INCREMENTAL ELMORE DELAY CALCULATION - Systems and techniques for incrementally updating Elmore pin-to-pin delays are described. During operation, an embodiment receives a representation of a physical topology of a routed net that electrically connects a driver pin to a set of load pins. The embodiment then computes a set of incremental Elmore delay coefficients based on the representation. Next, using the Elmore delay coefficients, the embodiment computes a set of delays based on the representation, wherein each delay in the set of delays corresponds to a delay between the driver pin and a corresponding load pin in the set of load pins. As load pin capacitances change during circuit optimization, the set of incremental Elmore delay coefficients can then be used to update the delays between the driver pin and the load pins in a very computationally efficient manner. | 12-05-2013 |
20130326283 | DEBUG IN A MULTICORE ARCHITECTURE - A method of monitoring thread execution within a multicore processor architecture which comprises a plurality of interconnected processor elements for processing the threads, the method comprising receiving a plurality of thread parameter indicators of one or more parameters relating to the function and/or identity and/or execution location of a thread or threads, comparing at least one of the thread parameter indicators with a first plurality of predefined criteria each representative of an indicator of interest, and generating an output consequential upon thread parameter indicators which have been identified to be of interest as a result of the said comparison. | 12-05-2013 |
20130326282 | DEBUG IN A MULTICORE ARCHITECTURE - A method of monitoring thread execution within a multicore processor architecture which comprises a plurality of interconnected processor elements for processing the threads, the method comprising receiving a plurality of thread parameter indicators of one or more parameters relating to the function and/or identity and/or execution location of a thread or threads, comparing at least one of the thread parameter indicators with a first plurality of predefined criteria each representative of an indicator of interest, and generating an output consequential upon thread parameter indicators which have been identified to be of interest as a result of the said comparison. | 12-05-2013 |
20130318488 | EXCLUDING LIBRARY CELLS FOR DELAY OPTIMIZATION IN NUMERICAL SYNTHESIS - Methods and systems for excluding library cells are described. Some embodiments receive a generic logical effort value and optionally a generic parasitic delay value for a timing arc of a library cell type. Next, library cells of the library cell type are excluded whose specific logical effort values for the timing arc are greater than the generic logical effort value by more than a first threshold and/or optionally whose specific parasitic delay values for the timing arc are greater than the generic parasitic delay value by more than a second threshold. A new generic logical effort value and optionally a new generic parasitic delay value can be determined based on at least some of the remaining library cells. The process of excluding library cells and determining new generic logical effort values and optionally new generic parasitic delay values can be performed iteratively. | 11-28-2013 |
20130314824 | PREVENTING ELECTROSTATIC DISCHARGE (ESD) FAILURES ACROSS VOLTAGE DOMAINS - An electrostatic discharge (ESD) device implemented within a power domain to mitigate ESD events imparted from another power domain for reducing integrated circuit (IC) failures. A first power domain includes an interface where ESD events are received and an output that can impart ESD event voltages on other components. A second power domain includes an ESD device coupled to the output of the first power domain and a protected IC. In one embodiment, the ESD device includes a floating device with an input terminal coupled to the interface output. By floating the device receiving the ESD event in the second power domain, damaging ESD induced voltages are reduced. Embodiments of the ESD device can be implemented using standard cell libraries to simplify integration. | 11-28-2013 |
20130305207 | METHOD FOR DETECTING AND DEBUGGING DESIGN ERRORS IN LOW POWER IC DESIGN - A method for detecting anomalies in signal behaviors in a simulation of a low power IC includes receiving a circuit design and a power specification of the IC, determining at least one power sequence checking rule from the power specification, simulating the circuit design and the power specification to obtain a dump file, identifying at least one anomaly of the at least one power sequence checking rule based on the dump file, and generating information relevant to the identified anomaly of the at least one power sequence checking rule. The method further includes setting up a context in a debugger for debugging the anomaly by displaying a waveform of misbehaved signals associated with the anomaly in a waveform window, and a portion of the circuit design and/or a portion of the power specification associated with the anomaly in a text window. | 11-14-2013 |
20130297279 | QUASI-DYNAMIC SCHEDULING AND DYNAMIC SCHEDULING FOR EFFICIENT PARALLEL SIMULATION - An approach for simulating an electronic circuit design uses the influence of a set of input changes of regions of the circuit design to schedule which levels within regions of a circuit should be simulated. The state of one or more inputs of one or more regions of the circuit design is checked to determine if inputs to these regions changed. For each input having an input change, a logic level depth associated with the input is computed. Using the computed logic levels, a maximum logic level depth of the one or more regions is computed for a set of input changes. Thus, for each region that has an input with a state indicating an input change, simulation may be scheduled for first logic level through and including the determined maximum logic level in each region of the circuit design in parallel. | 11-07-2013 |
20130297278 | RETIMING A DESIGN FOR EFFICIENT PARALLEL SIMULATION - An approach for simulating a circuit design partitions the circuit design into pipeline regions that include one or more pipeline levels. A path length is computed for each combinational region within a pipeline region to compute an achievable timing goal for each pipeline region. A target retiming goal is determined for the set of pipeline regions based on the computed achievable timing goals of the pipeline regions. A pipeline region is identified from the set of pipeline regions that does not satisfy the target timing goal. A measure of slack is computed for each pipeline level in the identified pipeline region. Using the computed slack, path lengths of combinational regions in the pipeline levels of the identified pipeline region are iteratively retimed. The resulting circuit design is simulated using the retimed path lengths if the retimed critical path of the pipeline region satisfies the target timing goal. | 11-07-2013 |
20130290919 | SELECTIVE EXECUTION FOR PARTITIONED PARALLEL SIMULATIONS - Computer implemented techniques for the partitioned simulation of parallel architectures are disclosed. A high-level design for simulation is obtained. A graph representation for the high-level design is determined. The graph for the high-level design is partitioned into sub-graphs. A subset of the sub-graphs is selected for simulation based on input-change bits of the sub-graphs. The subset of the sub-graphs is subsequently evaluated on parallel architectures in order to produce a simulation result for the high-level design. | 10-31-2013 |