Storart Technology Co., Ltd. Patent applications |
Patent application number | Title | Published |
20160036464 | Multi-Code Chien's Search Circuit for BCH Codes with Various Values of m in GF(2m) - The present invention discloses a multi-code Chien's search circuit for BCH codes with various values of m in GF(2 | 02-04-2016 |
20150256200 | METHOD AND CIRCUIT FOR SHORTENING LATENCY OF CHIEN'S SEARCH ALGORITHM FOR BCH CODEWORDS - A method for shortening latency of Chien's search and related circuit are disclosed. The method includes the steps of: determining a shifted factor, p; receiving a BCH codeword; computing a syndrome from the BCH codeword; finding an error-location polynomial based on the syndrome; and processing Chien's search for the error-location polynomial to find out roots thereof. p is a number of successive zeroes from the first bit of the BCH codeword, the Chien's search starts iterative calculations by substituting a variable of the error-location polynomial with a nonzero element in Galois Field, GF(2 | 09-10-2015 |
20150199282 | SCRAMBLE RANDOM SEED PREDICTION METHOD WITH STORAGE DEVICE BUILT-IN DATA COPY BACK PROCEDURE - A scramble random seed prediction method with the storage device built-in data copy back procedure is disclosed. The method may predict a scramble random seed before first time programming. The data may be programmed with the scramble random seed based on the pager number of the block B, not block A, before programming data to block A. After data is moved from block A to block B with the storage device built-in data copy back procedure, the data in block B may be have the best scramble random seed. Therefore, compared to the conventional method of scrambling data or data movement, the moved data of this invention may be much more stable with the storage device data copy back procedure. | 07-16-2015 |
20150188574 | DECODER FOR LDPC CODE AND BCH CODE AND DECODING METHOD THEREOF - A decoder for A LDPC code and A BCH code and decoding method thereof are provided. The decoder decodes the encoded data based on the LDPC code and the BCH code simultaneously. Then the decoder outputs decoded data after the decoding procedure has been finished. Additionally, in the decoding procedure for decoding the encoded data based on the BCH code, the decoded result which the encoded data is decoded based on the LDPC code is utilized, so as to increase the processing speed for decoding the encoded data, and enhance the overall decoding performance. | 07-02-2015 |
20150179279 | METHOD FOR REPLACING THE ADDRESS OF SOME BAD BYTES OF THE DATA AREA AND THE SPARE AREA TO GOOD ADDRESS OF BYTES IN NON-VOLATILE STORAGE SYSTEM - A method for replacing the address of some bad bytes (bad columns) of the data area and the spare area to the good address of bytes (good columns) in non-volatile storage system is disclosed. The steps of the method are: waiting for a command from a host; judging if there is still some data to be processed; if no, go back to the previous step; if yes, go to next step; judging if a bad column is used; if no, process data access and go back to the step of judging if there is still some data to be processed; and if yes, process data accessing as original operation and increase the address by one. | 06-25-2015 |
20150109040 | SELF-FEEDBACK RANDOM GENERATOR AND METHOD THEREOF - A self-feedback random generator comprises a digital-to -analog converter, a digital oscillator, a frequency-modulating unit and a first D-type flip-flop. The digital-to-analog converter receives a digital random-code signal and the digital random-code signal is converted to corresponding analog random signal. The frequency-modulating unit modulates frequency of first digital oscillating signal so as to increase random of frequency of first digital oscillating signal according to voltage value of the analog random signal, and accordingly outputs a second digital oscillating signal. The first D-type flip-flop receives the second digital oscillating signal and a clock signal, and reads the second digital oscillating signal through utilizing the clock signal so as to outputs the digital random-code signal, wherein frequency of the clock signal is smaller than frequency of the first digital oscillating signal, and random of frequency of the second digital oscillating signal corresponds to random of the digital random-code signal. | 04-23-2015 |
20140317467 | METHOD OF DETECTING AND CORRECTING ERRORS WITH BCH ENGINES FOR FLASH STORAGE SYSTEM - A method of detecting and correcting errors with BCH engines for flash storage system is provided and the steps of the method comprise: deciding the number i of sub-channels CH1˜CHi divided from a data channel; deriving a width selection of each sub-channel CHi; checking if the sum of width of each sub-channel CHi is equal to the data channel or not; if yes, run next step; if not, go back to the precious step; and connecting each BCH engine BCHi to each sub-channel CHi with a bus by one-by-one mapping. | 10-23-2014 |