STMicroelectronics Pte Ltd Patent applications |
Patent application number | Title | Published |
20160099373 | WAFER LEVEL PACKAGING, OPTICAL DETECTION SENSOR AND METHOD OF FORMING SAME - An optical detection sensor functions as a proximity detection sensor that includes an optical system and a selectively transmissive structure. Electromagnetic radiation such as laser light can be emitted through a transmissive portion of the selectively transmissive structure. A reflected beam can be detected to determine the presence of an object. The sensor is formed by encapsulating the transmissive structure in a first encapsulant body and encapsulating the optical system in a second encapsulant body. The first and second encapsulant bodies are then joined together. In a wafer scale assembling the structure resulting from the joined encapsulant bodies is diced to form optical detection sensors. | 04-07-2016 |
20150332995 | ELECTRONIC DEVICE INCLUDING COMPONENTS IN COMPONENT RECEIVING CAVITY AND RELATED METHODS - An electronic device may include a surface mount integrated circuit (IC) package to be attached to a printed circuit board (PCB). The surface mount IC package may include at least one IC and an encapsulating material surrounding the at least one IC and having a component receiving cavity defined therein on a bottom surface thereof to be positioned adjacent the PCB. The surface mount IC package may also include electrical leads coupled to the at least one IC and extending outwardly from the encapsulating material to be coupled to the PCB. The electronic device may also include at least one electronic component carried within the component receiving cavity and that includes electrical contacts to be coupled to the PCB. | 11-19-2015 |
20150253276 | FLEXIBLE ELECTROCHEMICAL MICRO-SENSOR - A universal electrochemical micro-sensor can be used either as a biosensor or an environmental sensor. Because of its small size and flexibility, the micro-sensor is suitable for continuous use to monitor fluids within a live subject, or as an environmental monitor. The micro-sensor can be formed on a reusable glass carrier substrate. A flexible polymer backing, together with a set of electrodes, forms a reservoir that contains an electrolytic fluid chemical reagent. During fabrication, the glass carrier substrate protects the fluid chemical reagent from degradation. A conductive micromesh further contains the reagent while allowing partial exposure to the ambient biological or atmospheric environment. The micromesh density can be altered to accommodate fluid reagents having different viscosities. Flexibility is achieved by attaching a thick polymer tape and peeling away the micro-sensor from the glass carrier substrate. The final structure is thereby transferred to the polymer tape, providing a flexible product. | 09-10-2015 |
20150237245 | LOW PROFILE CAMERA MODULE WITH IMAGE COMPENSATION - A low-cost resin lens is disclosed for use in miniature cameras. The resin lens features a low profile that is particularly well-suited to consumer products such as smart phones. The resin lens is mounted to an integrated circuit die that is attached to a standard four-layer substrate. The integrated circuit die includes electronic and/or optoelectronic circuits to support digital image capture, transfer, and processing. Image correction software adjusts the image to correct for distortion introduced by the resin lens. | 08-20-2015 |
20150235929 | ELECTRONIC DEVICE WITH HEAT DISSIPATER - An electronic device includes an integrated circuit chip mounted to a heat slug. The heat slug has a peripheral region having first thickness along a first direction, the peripheral region surrounding a recess region (having a second, smaller, thickness along the first direction) that defines a chip mounting surface along a second direction perpendicular to the first direction. The recess region defines side borders and a nook extends into the heat slug along the side borders. An insulating body embeds the integrated circuit one chip and heat slug. Material of the insulating body fills the nook. | 08-20-2015 |
20150194303 | METHOD FOR MAKING SEMICONDUCTOR DEVICES INCLUDING REACTANT TREATMENT OF RESIDUAL SURFACE PORTION - A method for making semiconductor devices may include forming a phosphosilicate glass (PSG) layer on a semiconductor wafer, with the PSG layer having a phosphine residual surface portion. The method may further include exposing the phosphine residual surface portion to a reactant plasma to integrate at least some of the phosphine residual surface portion into the PSG layer. The method may additionally include forming a mask layer on the PSG layer after the exposing. | 07-09-2015 |
20150145137 | METHOD TO PROVIDE THE THINNEST AND VARIABLE SUBSTRATE THICKNESS FOR RELIABLE PLASTIC AND FLEXIBLE ELECTRONIC DEVICE - An electronic device is formed by depositing polyimide on a glass substrate. A conductive material is deposited on the polyimide and patterned to form electrodes and signal traces. Remaining portions of the electronic device are formed on the polyimide. A second polyimide layer is then formed on the first polyimide layer. The glass substrate is then removed, exposing the electrodes and the top surface of the electronic device. | 05-28-2015 |
20150140479 | METHOD OF PROCESSING A SEMICONDUCTOR WAFER SUCH AS TO MAKE PROTOTYPES AND RELATED APPARATUS - A method of processing a semiconductor wafer may include providing a rotatably alignable photolithography mask that includes different mask images. Each mask image may be in a corresponding different mask sector. The method may also include performing a series of exposures with the rotatably alignable photolithography mask at different rotational alignments with respect to the semiconductor wafer so that the different mask images produce at least one working semiconductor wafer sector, and at least one non-working semiconductor wafer sector. | 05-21-2015 |
20150138436 | CAMERA MODULE - One or more embodiments are directed to optical module assemblies, such as a camera module assembly, and methods of forming same. One embodiment is directed to an optical module assembly that includes a substrate having a first surface. An optical device is secured to the first surface of the substrate and electrically coupled to the substrate. A molded body is located on the first surface of the substrate outward of the optical device. The molded body includes a first recess. A lens assembly is secured to the molded body over the first recess by an adhesive material located in the first recess. In some embodiments, the molded body of the optical module assembly further includes a second recess spaced apart from the first recess. A transparent material is secured to the molded body over the second recess by an adhesive material located in the second recess. | 05-21-2015 |
20150138420 | LIQUID CRYSTAL CELL CONNECTION TO LENS MOUNT OF CAMERA MODULE - Electronics modules and methods of making electronics modules are provided. An electronics module includes a substrate having an electronic circuit mounted thereon, a lens mount affixed to the substrate, the lens mount having a lens assembly mounted therein, and a liquid crystal cell affixed to the lens mount over the lens assembly, the liquid crystal cell having electrical terminals, wherein the lens mount includes adhesive containment pockets that are filled with a conductive adhesive so as to contact the electrical terminals of the liquid crystal cell, wherein the adhesive containment pockets include contacts that are electrically connected to the substrate. In some embodiments, the electronics module is a camera module. | 05-21-2015 |
20150137148 | OPTICAL SENSOR PACKAGE - One or more embodiments are directed to system in package (SiP) for optical devices, including proximity sensor packaging. One embodiment is directed to an optical package that includes a stacked arrangement with a plurality of optical devices arranged over an image sensor processor die that is coupled to a first substrate. Between the two optical devices and the image sensor processor die there is provided at least a second substrate. In one embodiment, the optical package is a proximity sensor package and the optical devices include a light-emitting diode die and a light-receiving diode die. In one embodiment, the light-emitting diode die is secured to a surface of the second substrate and the light-receiving diode die is secured to a surface of a third substrate. The second and the third substrate may be secured to a surface of the image sensor processor die or to a surface of encapsulation material. | 05-21-2015 |
20150103297 | OPTICAL ASSEMBLY INCLUDING ELECTRICALLY CONDUCTIVE COUPLING MEMBER AND RELATED METHODS - An optical assembly may include a substrate, a housing carried by the substrate and having at least one adhesive-receiving recess in an upper surface thereof, and a lens carried by the housing. The optical assembly may also include a liquid crystal focus cell adjacent the lens and including cell layers and pairs of electrically conductive contacts associated therewith. The optical assembly may also include at least one electrically conductive member within the at least one adhesive-receiving recess and coupling together each pair of the electrically conductive contacts, and an adhesive body in the at least one adhesive-receiving recess covering the at least one electrically conductive member. | 04-16-2015 |
20150084171 | NO-LEAD SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME - A non-lead (QFN) semiconductor package is disclosed. The package includes a die attach pad and a semiconductor die supported by the die attached pad. The semiconductor die includes a plurality of pads on an active surface thereof. The package further includes a plurality of terminal leads, an encapsulant that encapsulates the semiconductor die, and a redistribution layer including a plurality of interconnections electrically connecting the pads to the terminal leads. A method of making the package is also disclosed. | 03-26-2015 |
20150060891 | OPTOELECTRONICS ASSEMBLY AND METHOD OF MAKING OPTOELECTRONICS ASSEMBLY - An electronics assembly includes a semiconductor die assembly, an enclosure affixed to the semiconductor die assembly, the enclosure defining first and second chambers over the semiconductor die assembly, and first and second optical elements mounted in the first and second chambers, respectively. The semiconductor die assembly includes a semiconductor die encapsulated in a molded material, an encapsulation layer located on the top surface of the semiconductor die, and at least one patterned metal layer and at least one dielectric layer over the encapsulation layer. Conductive pillars extend through the encapsulation layer for electrical connection to the semiconductor die. The encapsulation layer blocks optical crosstalk between the first and second chambers. A method is provided for making the electronics assembly. | 03-05-2015 |
20150035133 | ELECTRONIC MODULES AND METHODS OF MAKING ELECTRONIC MODULES - A method is described for making electronic modules includes molding onto a substrate panel a matrix panel defining a plurality of cavities, attaching semiconductor die to the substrate panel in respective cavities of the molded matrix panel, electrically connecting the semiconductor die to the substrate panel, affixing a cover to the molded matrix panel to form an electronic module assembly, mounting the electronic module assembly on a carrier tape, and separating the electronic module assembly into individual electronic modules. An electronic module is described which includes a substrate, a wall member molded onto the substrate, the molded wall member defining a cavity, at least one semiconductor die attached to the substrate in the cavity and electrically connected to the substrate, and a cover affixed to the molded wall member over the cavity. | 02-05-2015 |
20150028187 | IMAGE SENSOR DEVICE WITH INFRARED FILTER ADHESIVELY SECURED TO IMAGE SENSOR INTEGRATED CIRCUIT AND RELATED METHODS - An image sensor device may include a mounting substrate having an IC-receiving cavity therein and a filter-receiving opening aligned with the IC-receiving cavity, an image sensor integrated circuit (IC) within the IC-receiving cavity and having an image sensing area aligned with the filter-receiving opening, and an adhesive bead on the image sensor IC surrounding the image sensing area. Furthermore, an infrared (IR) filter may be within the filter-receiving opening and have peripheral portions contacting the adhesive bead. | 01-29-2015 |
20140294046 | MICROELECTRONIC ENVIRONMENTAL SENSING MODULE - Sensors for air flow, temperature, pressure, and humidity are integrated onto a single semiconductor die within a miniaturized Venturi chamber to provide a microelectronic semiconductor-based environmental multi-sensor module that includes an air flow meter. One or more such multi-sensor modules can be used as building blocks in dedicated application-specific integrated circuits (ASICs) for use in environmental control appliances that rely on measurements of air flow. Furthermore, the sensor module can be built on top of existing circuitry that can be used to process signals from the sensors. By integrating the Venturi chamber with accompanying environmental sensors, correction factors can be obtained and applied to compensate for temporal humidity fluctuations and spatial temperature variation using the Venturi apparatus. | 10-02-2014 |
20140293558 | LENS MOUNT WITH CONDUCTIVE GLUE POCKET FOR GROUNDING TO A CIRCUIT BOARD - A lens mount is attached to a circuit board and covers electrical components on the circuit board. An electrically insulating device is positioned between the lens mount and the circuit board. The circuit board includes a grounding pad adjacent the electrically insulating device. The lens mount includes an aperture aligned with the grounding pad and the electrically insulating device. A conductive glue is dispensed into the aperture to electrically ground the lens mount to the grounding pad. The electrically insulating device seals the conductive glue from the electrical components. A method of grounding a lens mount to a circuit board is provided. | 10-02-2014 |
20140293120 | CONTACT HAVING AN ANGLED PORTION - Described herein are various embodiments of contacts that include different portions angled with respect to one another and methods of manufacturing devices that include such contacts. In some embodiments, a module may include a first portion of a contact that is disposed within a housing and a second portion that is disposed outside of the housing, with the second portion angled with respect to the first portion. Manufacturing such devices may include depositing a conductive material to electrically connect the contact to a contact pad of a substrate. In some embodiments, a deposition process for depositing the conductive material may have a minimum dimension, which defines a minimum dimension of a conductive material once deposited. In some such embodiments, a distance between a terminal end of the contact pin and the contact pad may be greater than the minimum dimension of the deposition process. | 10-02-2014 |
20140292344 | ACCUMULATED POWER CONSUMPTION SENSOR: APPLICATION IN SMART BATTERIES SYSTEMS - A device is provided for monitoring the total current discharged from a battery. The device includes a bridge circuit of resistors in which one of the resistors has a resistance which varies according to the current which has passed through it. Whenever the battery passes a current to a load, a small portion of the current is passed through the bridge circuit. | 10-02-2014 |
20140292317 | DURABLE MINIATURE GAS COMPOSITION DETECTOR HAVING FAST RESPONSE TIME - A miniature oxygen sensor makes use of paramagnetic properties of oxygen gas to provide a fast response time, low power consumption, improved accuracy and sensitivity, and superior durability. The miniature oxygen sensor disclosed maintains a sample of ambient air within a micro-channel formed in a semiconductor substrate. O | 10-02-2014 |
20140291867 | APPARATUS AND METHOD TO ATTACH A WIRELESS COMMUNICATION DEVICE INTO A SEMICONDUCTOR PACKAGE - A semiconductor package includes an RFID chip positioned between a first die and a second die attached to a support substrate. The RFID chip is free of electrical connections to the dice and the support substrate. The RFID chip is sized to correspond to an interposer board. Data pertaining to operating characteristics of the dice are stored to and read from the RFID chip during back-end processing to determine abnormalities and improve yield. Said data may be stored to a database corresponding to the RFID chip in the package. A method of making a semiconductor package having an RFID chip positioned between dice is provided. The package is traceable by customers via the data stored to the RFID chip and the database. | 10-02-2014 |
20140291829 | ADHESIVE BONDING TECHNIQUE FOR USE WITH CAPACITIVE MICRO-SENSORS - A micro-sensor device that includes a passivation-protected ASIC module and a micro-sensor module bonded to a patterned cap provides protection for signal conditioning circuitry while allowing one or more sensing elements in the micro-sensor module to be exposed to an ambient environment. According to a method of fabricating the micro-sensor device, the patterned cap can be bonded to the micro-sensor module using a planarizing adhesive that is chemically compatible with the sensing elements. In one embodiment, the adhesive material is the same material used for the dielectric active elements, for example, a photo-sensitive polyimide film. | 10-02-2014 |
20140291812 | SEMICONDUCTOR PACKAGES HAVING AN ELECTRIC DEVICE WITH A RECESS - Embodiments are directed to a package that includes an electric device having a recess. In one embodiment, the electric device is a sensor and the recess reduces signal drift of the sensor caused by thermal expansion of the package. In another embodiment, the recess is substantially filled with adhesive material, thus increasing adhesion between the electric device and a substrate of the package while at the same time allowing for lower adhesive fillets. | 10-02-2014 |
20140291782 | METHODS AND DEVICES FOR PACKAGING INTEGRATED CIRCUITS - Methods and devices for packaging integrated circuits. A packaged device may include an integrated circuit, a first packaging component including a patterned surface, and a second packaging component. The patterned surface of the first packaging component may be adhesively coupled to a surface of the second packaging component or a surface of the integrated circuit. The integrated circuit may be at least partially enclosed between the first and second packaging components. A packaging method may include patterning a surface of a packaging component of an integrated circuit package. The surface of the packaging component may be for adhesively coupling to a second component to at least partially enclose an integrated circuit in the integrated circuit package. | 10-02-2014 |
20140291677 | INTEGRATED MULTI-SENSOR MODULE - A semiconductor-based multi-sensor module integrates miniature temperature, pressure, and humidity sensors onto a single substrate. Pressure and humidity sensors can be implemented as capacitive thin film sensors, while the temperature sensor is implemented as a precision miniature Wheatstone bridge. Such multi-sensor modules can be used as building blocks in application-specific integrated circuits (ASICs). Furthermore, the multi-sensor module can be built on top of existing circuitry that can be used to process signals from the sensors. An integrated multi-sensor module that uses differential sensors can measure a variety of localized ambient environmental conditions substantially simultaneously, and with a high level of precision. The multi-sensor module also features an integrated heater that can be used to calibrate or to adjust the sensors, either automatically or as needed. Such a miniature integrated multi-sensor module that features low power consumption can be used in medical monitoring and mobile computing, including smart phone applications. | 10-02-2014 |
20140252507 | SELF-SEALING MEMBRANE FOR MEMS DEVICES - Embodiments of the present disclosure are related to MEMS devices having a suspended membrane that are secured to and spaced apart from a substrate with a sealed cavity therebetween. The membrane includes openings with sidewalls that are closed by a dielectric material. In various embodiments, the cavity between the membrane and the substrate is formed by removing a sacrificial layer through the openings. In one or more embodiments, the openings in the membrane are closed by depositing the dielectric material on the sidewalls of the openings and the upper surface of the membrane. | 09-11-2014 |
20140191387 | METHOD OF FABRICATING LAND GRID ARRAY SEMICONDUCTOR PACKAGE - A fan-out wafer level package is provided with a semiconductor die embedded in a reconstituted wafer. A redistribution layer is positioned over the semiconductor die, and includes a land grid array on a face of the package. A copper heat spreader is formed in the redistribution layer over the die in a same layer as a plurality of electrical traces configured to couple circuit pads of the semiconductor die to respective contact lands of the land grid array. In operation, the heat spreader improves efficiency of heat transfer from the die to the circuit board. | 07-10-2014 |
20140175649 | ELECTRONIC DEVICE INCLUDING ELECTRICALLY CONDUCTIVE VIAS HAVING DIFFERENT CROSS-SECTIONAL AREAS AND RELATED METHODS - An electronic device may include a bottom interconnect layer having a first electrically conductive via therein. The electronic device may also include an integrated circuit (IC) carried by said bottom interconnect layer, and an encapsulation material on the bottom interconnect layer and surrounding the IC. The encapsulation layer may have a second electrically conductive via therein aligned with the first electrically conductive via. The second electrically conductive via may have a cross-sectional area larger than a cross-sectional area of the first electrically conductive via. | 06-26-2014 |
20140133215 | RESISTOR THIN FILM MTP MEMORY - An integrated circuit is formed having an array of memory cells located in the dielectric stack above a semiconductor substrate. Each memory cell has two adjustable resistors and two heating elements. A dielectric material separates the heating elements from the adjustable resistors. One heating element alters the resistance of one of the resistors by applying heat thereto to write data to the memory cell. The other heating element alters the resistance of the other resistor by applying heat thereto to erase data from the memory cell. | 05-15-2014 |
20140113410 | SYSTEM IN PACKAGE MANUFACTURING METHOD USING WAFER-TO-WAFER BONDING - Embodiments of the present disclosure are related to manufacturing system-in-packages at wafer-level. In particular, various embodiments are directed to adhering a first wafer to a second wafer and adhering solder balls to contact pads of the first wafer. In one embodiment, a first wafer having first and second surfaces is provided. The first wafer includes bond pads located on the first surface that are coupled to a respective semiconductor device located in the first wafer. A second wafer having an electrical component located therein is provided. A conductive adhesive is provided on at least one of the first wafer and the second wafer. Conductive balls are provided on the bond pads on the first surface of the first wafer. The conductive balls and the conductive adhesive are heated to cause the conductive balls to adhere to the bond pad and the conductive adhesive to adhere the first wafer to the second wafer. | 04-24-2014 |
20140111875 | METHOD FOR MAKING PAIRED LENSES WITH AN OPAQUE BARRIER BETWEEN, AND PRODUCT MADE - A method comprises depositing an optical filter layer on a glass wafer, then cutting the wafer into dice. The dice are positioned on a carrier and encapsulated in a molding compound to form a reconstituted wafer, and the wafer is back-ground and polished. Lens faces are positioned on opposing surfaces of the glass dice and spacers are positioned on one side of the wafer. The wafer is then cut into lens modules, each having two side-by-side lenses with an opaque molding compound barrier between. The individual modules are attached to devices that require dual lenses, such as, e.g., proximity sensors that use a light source and a light receiver or detector. | 04-24-2014 |
20140103521 | ELECTRONIC DEVICE HAVING A CONTACT RECESS AND RELATED METHODS - An electronic device may include a bottom interconnect layer and an integrated circuit (IC) carried by the bottom interconnect layer. The electronic device may further include an encapsulation material on the bottom interconnect layer and laterally surrounding the IC. The electronic device may further include electrically conductive pillars on the bottom interconnect layer extending through the encapsulation material. At least one electrically conductive pillar and adjacent portions of encapsulation material may have a reduced height with respect to adjacent portions of the IC and the encapsulation material and may define at least one contact recess. The at least one contact recess may be spaced inwardly from a periphery of the encapsulation material. | 04-17-2014 |
20140091443 | SURFACE MOUNT PACKAGE FOR A SEMICONDUCTOR INTEGRATED DEVICE, RELATED ASSEMBLY AND MANUFACTURING PROCESS - A surface mount package of a semiconductor device, has: an encapsulation, housing at least one die including semiconductor material; and electrical contact leads, protruding from the encapsulation to be electrically coupled to contact pads of a circuit board; the encapsulation has a main face designed to face a top surface of the circuit board, which is provided with coupling features designed for mechanical coupling to the circuit board to increase a resonant frequency of the mounted package. The coupling features envisage at least a first coupling recess defined within the encapsulation starting from the main face, designed to be engaged by a corresponding coupling element fixed to the circuit board, thereby restricting movements of the mounted package. | 04-03-2014 |
20140084308 | OVERMOLD WITH SINGLE ATTACHMENT USING OPTICAL FILM - A sensor package is provided having a light sensitive component and a light emitting component attached to a same substrate. Light from the light emitting component is emitted from the package through a first opening and reflected back into the package to the light sensitive component through a second opening in the package. A glass attachment is placed between the light emitting component and the light sensitive component. A portion of the glass is removed and filled with an opaque substance to prevent light travelling between the light emitting component and the light sensitive component in the package. | 03-27-2014 |
20140083557 | PHOTORESIST DELIVERY SYSTEM INCLUDING CONTROL VALVE AND ASSOCIATED METHODS - A photoresist delivery system includes a photoresist pump, a photoresist reservoir coupled to the photoresist pump, and a photoresist container. A control valve is between the photoresist reservoir and the photoresist container and is movable from a closed position to an open position upon engagement of the photoresist container with the photoresist reservoir to replenish photoresist therein. | 03-27-2014 |
20140077667 | WAFER HANDLING STATION INCLUDING CASSETTE MEMBERS WITH LATERAL WAFER CONFINING BRACKETS AND ASSOCIATED METHODS - A wafer handling station includes a housing defining a chamber, and a wafer cassette assembly positionable in the chamber. The wafer cassette assembly includes a vertical support, and cassette members carried by the vertical support in spaced relation. Each cassette member includes a base coupled to the vertical support, wafer contact pads on an upper surface of the base and configured to support a wafer thereon, and a pair of wafer brackets carried by the base and configured to engage respective edges of the wafer to laterally confine the wafer. | 03-20-2014 |
20140061823 | MEMBRANE STRUCTURE FOR ELECTROCHEMICAL SENSOR - A micro-electrochemical sensor contains magnetic compounds inserted within a substrate that exert a magnetic force of attraction on paramagnetic beads held in contact with an electrode. The magnetic compounds can be contained within a fluid that is introduced into a void in the substrate. The electrode can be spaced apart from the magnetic compounds by a dielectric multi-layer membrane. During the fabrication process, different layers within the membrane-electrode structure can be tuned to have compressive or tensile stress so as to maintain structural integrity of the membrane, which is thin compared with the size of the void beneath it. During a process of forming the structure of the sensor, the tensile stress in a TiW adhesion layer can be adjusted to offset a composite net compressive stress associated with the dielectric layers of the membrane. The membrane can also be used in forming both the electrode and the void. | 03-06-2014 |
20140061447 | RADIATION SENSOR - A sensor package includes a radiation source and a radiation detector provided on a substrate. A cover member is mounted on or affixed to the substrate over the source and detector. The cover member includes an opaque housing, a first transparent portion provided over the source, a second transparent portion provided over the detector and a transparent insert within the housing and positioned at one of said transparent portions. An opaque protrusion is provided on the housing separating a region associate with the first transparent portion (and radiation source) from a region associated with the second transparent portion (and detector), the protrusion attached to a surface of the substrate. | 03-06-2014 |
20140057394 | METHOD FOR MAKING A DOUBLE-SIDED FANOUT SEMICONDUCTOR PACKAGE WITH EMBEDDED SURFACE MOUNT DEVICES, AND PRODUCT MADE - A manufacturing process includes forming a reconstituted wafer, including embedding semiconductor dice in a molding compound layer and forming through-wafer vias in the layer. A fan-out redistribution layer is formed on a front side of the wafer, with electrical traces interconnecting the dice, through-wafer vias, and contact pads positioned on the redistribution layer. Solder balls are positioned on the contact pads and a molding compound layer is formed on the redistribution layer, reinforcing the solder balls. A second fan-out redistribution layer is formed on a back side of the wafer, with electrical traces interconnecting back ends of the through-wafer vias and contact pads positioned on a back face of the second redistribution layer. Flip-chips and/or surface-mounted devices are coupled to the contact pads of the second redistribution layer and encapsulated in an underfill layer formed on the back face of the second redistribution layer. | 02-27-2014 |
20140054727 | METHOD OF SELECTIVELY DEGLAZING P205 - A method of forming a transistor is disclosed, in which gate-to-substrate leakage is addressed by forming and maintaining a conformal oxide layer overlying the transistor gate. Using the method disclosed for an n-type device, the conformal oxide layer can be formed as part of the source-drain doping process. Subsequent removal of residual phosphorous dopants from the surface of the oxide layer is accomplished without significant erosion of the oxide layer. The removal step uses a selective deglazing process that employs a hydrolytic reaction, and an acid-base neutralization reaction that includes an ammonium hydroxide component. | 02-27-2014 |
20140000804 | FIXING TECHNOLOGY FOR COMPONENT ATTACH | 01-02-2014 |
20130322039 | CAP FOR A MICROELECTROMECHANICAL SYSTEM DEVICE WITH ELECTROMAGNETIC SHIELDING, AND METHOD OF MANUFACTURE - A cap for a microelectromechanical system device includes a first layer of, e.g., Bismaleimide Triazine (BT) resin material in which a through-aperture is formed, laminated to a second layer of BT resin material that closes the aperture in the first layer, forming a cavity. The first and second layers are laminated with a thermosetting adhesive that is sufficiently thick to encapsulate particles that may remain from a routing operation for forming the apertures. The interior of the cavity, including exposed portions of the adhesive, and the exposed face of the first layer are coated with an electrically conductive paint. The cap is adhered to a substrate over the MEMS device using an electrically conductive adhesive, which couples the conductive paint layer to a ground plane of the substrate. The layer of conductive paint serves as a shield to prevent or reduce electromagnetic interference acting on the MEMS device. | 12-05-2013 |
20130320471 | WAFER LEVEL OPTICAL SENSOR PACKAGE AND LOW PROFILE CAMERA MODULE, AND METHOD OF MANUFACTURE - A wafer-level camera sensor package includes a semiconductor substrate with an optical sensor on a front surface. Through-silicon-vias (TSV) extend through the substrate and provide I/O contact with the sensor from the back side of the substrate. A glass cover is positioned over the front surface, and the cover and substrate are embedded in a molding compound layer (MCL), the front surface of the MCL lying coplanar with the front of the cover, and the back surface lying coplanar with the back of the substrate. Surface-mount devices, electromagnetic shielding, and through-wafer-connectors can be embedded in the MCL. A redistribution layer on the back surface of the MCL includes bottom contact pads for mounting the package, and conductive traces interconnecting the contact pads, TSVs, surface-mount devices, shielding, and through-wafer-connectors. Anisotropic conductive adhesive is positioned on the front of the MCL for physically and electrically attaching a lens array. | 12-05-2013 |
20130314972 | RESISTOR THIN FILM MTP MEMORY - An integrated circuit is formed having an array of memory cells located in the dielectric stack above a semiconductor substrate. Each memory cell has two adjustable resistors and two heating elements. A dielectric material separates the heating elements from the adjustable resistors. One heating element alters the resistance of one of the resistors by applying heat thereto to write data to the memory cell. The other heating element alters the resistance of the other resistor by applying heat thereto to erase data from the memory cell. | 11-28-2013 |
20130248887 | OPTICAL ELECTRONIC PACKAGE - An optical electronic package includes transmitting chip and a receiving chip fixed to a wafer. A transparent encapsulation structure is formed by a transparent plate and a transparent encapsulation block that are formed over the transmitter chip and at least a portion of the receiver chip, with the transparent encapsulation block embedding the transmitter chip. An opaque encapsulation block extends over the transparent plate and includes an opening that reveals a front area of the transparent plate. The front area is situated above an optical transmitter of the transmitting chip and is offset laterally relative to an optical sensor of the receiving chip. | 09-26-2013 |
20130171816 | APPARATUS AND METHOD FOR PLACING SOLDER BALLS - A system and process for forming a ball grid array on a substrate includes defining a plurality of openings in a resist layer on the substrate, and forming a plurality of openings in the resist layer, each positioned over a contact pad of the substrate. Flux is then deposited in the openings, and solder balls are positioned in each opening with the flux. Solder bumps are formed by reflowing the solder balls in the respective openings. The resist layer is then removed, leaving an array of solder bumps on the substrate. The flux can be deposited by depositing a layer of flux, then removing the flux, except a portion that remains in each opening. Solder balls can be positioned by moving a ball feeder across the resist layer and dropping a solder ball each time an aperture in the ball feeder aligns with an opening in the resist layer. | 07-04-2013 |
20130170169 | CIRCUIT MODULE WITH MULTIPLE SUBMODULES - An embodiment of a circuit module includes module nodes, a first submodule, a second submodule, and a conductive structure. The first submodule has a first submodule node, and the second submodule is disposed over the first submodule and has a second submodule node. The conductive structure couples the first submodule node to one of the module nodes and couples the second submodule node to one of the module nodes. Another embodiment of a circuit module includes module nodes, a first submodule, a second submodule, and a conductive structure. The first submodule has first submodule nodes, and the second submodule is disposed over the first submodule and has second submodule nodes. The conductive structure couples one of the first and second submodule nodes to one of the module nodes and couples one of the first submodule nodes to one of the second submodule nodes. | 07-04-2013 |
20130170164 | ADHESIVE DAM - On a circuit substrate on which an adhesive is used to couple electronic or structural components to the substrate, an adhesive dam is positioned to prevent the adhesive from interfering with the operation of the circuit. A contact pad can be provided at a selected location and with a selected shape, and solder deposited on the pad, then reflowed to form the dam. The dam can be a structure soldered to a contact pad, or the dam can be supported at its ends by another structure of the device, so that, at the location where it functions to contain the adhesive, it is not attached to the substrate. | 07-04-2013 |
20130169312 | SYSTEM AND METHOD FOR REDUCING INPUT CURRENT SPIKE FOR DRIVE CIRCUITRY - A circuit includes a plurality of logic gates and a drive circuit. The plurality of logic gates are coupled between a first supply node and a second supply node. Each logic gate has at least one input and consumes a short circuit current during a logic state transition. The drive circuit is coupled to the inputs of the plurality of logic gates to deliver a copy of an input signal to each logic gate, wherein the input signal copies arrive at the inputs of the logic gates at substantially different times. The circuit may be incorporated in a touch screen panel and a display. | 07-04-2013 |
20130168899 | TOP GATE MOLD WITH PARTICLE TRAP - A top-gate molding system for encapsulating semiconductor devices includes a plurality of mold cavities formed between a middle plate and a bottom plate, and a runner system formed between an upper plate and the middle plate. The runner system includes a runner with a plurality of reservoirs along its length, with a gate extending from each of the reservoirs to one of the cavities. A particle trap is positioned on the bottom of the runner between a sprue and a first one of the reservoirs, to capture contaminating particles in a flow of molding compound before the particles enter any of the reservoirs. The particle trap can be, for example, a notch or a channel extending transversely across the bottom of the runner, or a dummy reservoir upstream of the first of the plurality of reservoirs. | 07-04-2013 |
20130168858 | EMBEDDED WAFER LEVEL BALL GRID ARRAY BAR SYSTEMS AND METHODS - A bar formed from a reconstituted wafer and containing one or more conductive material filled voids is used to electrically and physically connect the top and bottom packages in a package-on-package (PoP) package. The bar is disposed in the fan out area of the lower package forming the PoP package. | 07-04-2013 |
20130168815 | TEMPERATURE SWITCH WITH RESISTIVE SENSOR - The present disclosure is directed to a device and a method for forming a precision temperature sensor switch with a Wheatstone bridge configuration of four resistors and a comparator. When the temperature sensor detects a temperature above a threshold, the switch will change states. The four resistors in the Wheatstone bridge have the same resistance, with three of the resistors having a low temperature coefficient of resistance and the fourth resistor having a high temperature coefficient of resistance. As the temperature increases, the resistance of the fourth resistor will change. The change in resistance of the fourth resistor will change a voltage across the bridge. The voltage across the bridge is coupled to the comparator and compares the voltage with the threshold temperature, such that when the threshold temperature is exceeded, the comparator switches the output off. | 07-04-2013 |
20130168377 | ADAPTER FOR COUPLING A DIFFUSION FURNACE SYSTEM - An adapter is provided for fluidly coupling a process chamber, such as a diffusion furnace or a process tube, and a fluid source, such as a torch chamber or combustion chamber, of a system for processing semiconductor material. The process tube and the torch chamber include joint segments that can engage directly together to fluidly couple the torch chamber to the process tube for introducing a fluid, such as an oxidizing gas or vapor, into the process tube. The process chamber and the torch chamber are formed of materials having different rates of thermal expansion. The adapter is configured to couple the joint segments of the torch chamber and the process tube while accommodating the differences in thermal expansion between the materials. The adapter may be formed of quartz to couple a quartz torch chamber with a silicon carbide process tube. | 07-04-2013 |
20130168355 | METHODS AND APPARATUS FOR TMAH ETCHING - Methods and apparatus for etching materials using tetramethylammonium hydroxide (TMAH) are described. The methods may involve including an additive when applying the TMAH to the material to be etched. The additive may be a gas, and in in some situations may be clean dry air. The clean dry air may be provided with the TMAH to minimize or prevent the formation of hillocks in the etched structure. Apparatus for performing the methods are also described. | 07-04-2013 |
20130164867 | EMBEDDED WAFER LEVEL OPTICAL PACKAGE STRUCTURE AND MANUFACTURING METHOD - A method of forming an embedded wafer level optical package includes attaching a sensor die, PCB bars and an LED on adhesive tape laminated on a carrier, attaching a dam between two light sensitive sensors of the sensor die, encapsulating the sensor die, the PCB bars, the LED, and the dam in an encapsulation layer, debonding the carrier, grinding a top surface of the encapsulation layer, forming vias through the encapsulation layer to the sensor die and the LED, filling the vias with conductive material, metalizing the top surface of the encapsulation layer, dielectric coating of the top surface of the encapsulation layer, dielectric coating of a bottom surface of the encapsulation layer, patterning the dielectric coating of the bottom surface of the encapsulation layer, and plating the patterned dielectric coating of the bottom surface of the encapsulation layer. | 06-27-2013 |
20130147052 | OFFSET OF CONTACT OPENING FOR COPPER PILLARS IN FLIP CHIP PACKAGES - An integrated circuit die has a dielectric layer positioned over all the contact pads on the integrated circuit die. Openings are provided in the dielectric layer over each of the contact pads of the integrated circuit die in order to permit electrical coupling to be made between the integrated circuit and circuit boards outside of the die. For those contact pads located in the central region of the die, the opening in the dielectric layer is in a central region of the contact pad. For those contact pads located in a peripheral region of the die, spaced adjacent the perimeter die, the opening in the dielectric layer is offset from the center of the contact pad and is positioned closer to the central region of the die than the center of the contact pad is to the central region of the die. | 06-13-2013 |
20130147024 | BALANCED LEADFRAME PACKAGE STRUCTURE AND METHOD OF MANUFACTURING THE SAME - An integrated circuit package structure includes a bottom portion having a cavity, an integrated circuit attached to a top surface of the stepped cavity, a leadframe attached to the bottom portion, wire bonding for electrically coupling the integrated circuit to the leadframe, and a top portion conformally covering the integrated circuit and the bottom portion. | 06-13-2013 |
20130141834 | CAPACITANCE TRIMMING WITH AN INTEGRATED HEATER - The present disclosure is directed to a device and a method for achieving a precise capacitance of a capacitor. The method includes trimming a first capacitance of the capacitor to a second capacitance, the capacitor having a first conductive layer separated from a second conductive layer by a dielectric layer. Changing a first dielectric constant of the dielectric layer to a second dielectric constant, where the first dielectric constant corresponding to the first capacitance and the second dielectric constant corresponding to the second dielectric constant includes heating the dielectric layer above a threshold temperature for a time period. The heat is provided by either one of the plates of the capacitor or from a separate heater. | 06-06-2013 |
20130139587 | TUNABLE HUMIDITY SENSOR WITH INTEGRATED HEATER - A capacitive humidity sensor includes a first electrode, a humidity sensitive dielectric layer, and a second electrode. The humidity sensitive dielectric layer is between the first and the second electrodes. The humidity sensitive dielectric layer is etched at selected regions to form hollow regions between the first and second electrodes. | 06-06-2013 |
20130127041 | BALL GRID ARRAY TO PIN GRID ARRAY CONVERSION - Ball grid array to pin grid array conversion methods are provided. An example method can include coupling a plurality of solder balls to a respective plurality of pin grid array contact pads. Each of the plurality of solder balls is encapsulated in a fixed material. A portion of the plurality of solder balls and a portion of the fixed material is removed to provide a plurality of exposed solder balls. The exposed solder balls are softened and each of a plurality of pin members is inserted in a softened, exposed, solder ball. The plurality of pin members forms a pin grid array package. | 05-23-2013 |
20130121057 | RESISTOR THIN FILM MTP MEMORY - An integrated circuit is formed having an array of memory cells located in the dielectric stack above a semiconductor substrate. Each memory cell has two adjustable resistors and two heating elements. A dielectric material separates the heating elements from the adjustable resistors. One heating element alters the resistance of one of the resistors by applying heat thereto to write data to the memory cell. The other heating element alters the resistance of the other resistor by applying heat thereto to erase data from the memory cell. | 05-16-2013 |
20130119282 | WAFER LEVEL PACKAGING, OPTICAL DETECTION SENSOR AND METHOD OF FORMING SAME - An optical detection sensor and method of forming same. The optical detection sensor be a proximity detection sensor that includes an optical system and a selectively transmissive structure. Electromagnetic radiation such as laser light can be emitted through a transmissive portion of the selectively transmissive structure. A reflected beam can be detected to determine the presence of an object. | 05-16-2013 |
20130113098 | THROUGH VIA PACKAGE - An integrated circuit package includes an integrated circuit die in a reconstituted substrate. The active side is processed then covered in molding compound while the inactive side is processed. The molding compound on the active side is then partially removed and solder balls are placed on the active side. | 05-09-2013 |
20130105991 | EMBEDDED WAFER LEVEL PACKAGE FOR 3D AND PACKAGE-ON-PACKAGE APPLICATIONS, AND METHOD OF MANUFACTURE | 05-02-2013 |
20130105973 | EMBEDDED WAFER LEVEL PACKAGE FOR 3D AND PACKAGE-ON-PACKAGE APPLICATIONS, AND METHOD OF MANUFACTURE | 05-02-2013 |
20130100185 | ALCu HARD MASK PROCESS - A process for forming a metal interconnection in an integrated circuit includes forming a first metal layer and a second metal layer on the first metal layer. Photoresist is placed on the second metal layer and patterned to form a mask. The second metal layer is etched. The mask is then removed and the first metal layer is patterned with the second metal layer acting as mask for the first metal layer. | 04-25-2013 |
20130093072 | LEADFRAME PAD DESIGN WITH ENHANCED ROBUSTNESS TO DIE CRACK FAILURE - A leadframe includes a die pad and a protective wall surrounding the die pad. A semiconductor die is situated on the die pad. Indentations are formed on the four inner corners of the protective wall adjacent the corners of the semiconductor die. | 04-18-2013 |
20130069203 | GETTERING METHOD FOR DIELECTRICALLY ISOLATED DEVICES - A silicon on insulater (SOI) wafer is provided. A dielectric layer is formed on an active silicon substrate of the wafer. The dielectric layer is patterned and etched to expose selected portions of the silicon substrate. Impurities are then introduced into the exposed portions of the silicon substrate to act as gettering regions. The dielectric layer is then removed and an epitaxial layer of silicon is grown on the silicon substrate. Trenches are etched in the epitaxial layer of silicon through the gettering regions, partially removing the gettering regions and any contaminants contained therein. Remaining portions of the gettering regions still act as gettering regions during subsequent process steps. | 03-21-2013 |
20130062764 | SEMICONDUCTOR PACKAGE WITH IMPROVED PILLAR BUMP PROCESS AND STRUCTURE - A flip chip structure formed on a semiconductor substrate includes a first plurality of copper pillars positioned directly over, and in electrical contact with respective ones of a plurality of contact pads on the front face of the semiconductor substrate. A layer of molding compound is positioned on the front face of the substrate, surrounding and enclosing each of the first plurality of pillars and having a front face that is coplanar with front faces of each of the copper pillars. Each of a second plurality of copper pillars is positioned on the front face of one of the first plurality of copper pillars, and a solder bump is positioned on a front face of each of the second plurality of pillars. | 03-14-2013 |
20130010826 | MICROSENSOR WITH INTEGRATED TEMPERATURE CONTROL - Microsensors that include an integrated thermal energy source and an integrated temperature sensor are capable of providing localized heating and temperature control of individual sensing regions within the microsensor. Localized temperature control allows analyte detection to be carried out at the same temperatures or substantially the same temperatures at which the sensor is calibrated. By carrying out the sensing near the calibration temperature, more accurate results can be obtained. In addition, the temperature of the sensing region can be controlled so that chemical reactions involving the analyte in the sensing region occur near their peak reaction rate. Carrying out the sensing near the peak reaction rate improves the sensitivity of the sensor which is important as sensor dimensions decrease and the magnitude of the generated signals decreases. | 01-10-2013 |
20130001740 | HEAT SPREADER FOR THERMALLY ENHANCED FLIP-CHIP BALL GRID ARRAY PACKAGE - A heat spreader is provided for use with a thermally enhanced flip-chip ball grid array package. In the package, a semiconductor die is positioned front-side down on a package substrate, coupled thereto via solder balls. Passive devices can also be coupled to the substrate alongside the die. The heat spreader is positioned over the substrate and die, in thermal contact with the die. A projection in the center of the heat spreader makes contact with the back surface of the die via a thermal interface material, to draw heat from the die for improved cooling. The projection enables close contact with a thinned die while accommodating thicker passive devices positioned around the die on the substrate. | 01-03-2013 |
20120282767 | METHOD FOR PRODUCING A TWO-SIDED FAN-OUT WAFER LEVEL PACKAGE WITH ELECTRICALLY CONDUCTIVE INTERCONNECTS, AND A CORRESPONDING SEMICONDUCTOR PACKAGE - A semiconductor packaging process includes drilling apertures in a reconstituted wafer, then filling the apertures with conductive paste by wiping a quantity of the paste across a back surface of the wafer so that paste is forced into the apertures. The paste is cured to form conductive posts. The wafer is thinned, and redistribution layers are formed on front and back surfaces of the wafer, with the posts acting as interconnections between the redistribution layers. In an alternative process, blind apertures are drilled. A dry film resist is applied to the front surface of the wafer, and patterned to expose the apertures. Conductive paste is applied from the front. To prevent paste from trapping air pockets in the apertures, the wiping process is performed under vacuum. After curing the paste, the wafer is thinned to expose the cured paste in the apertures, and redistribution layers are formed. | 11-08-2012 |
20120244664 | REDUCING WARPAGE FOR FAN-OUT WAFER LEVEL PACKAGING - Fan-out wafer level packaging includes an integrated circuit having a top surface, a bottom surface, a plurality of side surfaces, and a bond pad defined on the top surface. A layer of encapsulant substantially surrounds the side surfaces of the integrated circuit, the layer of encapsulant having a height substantially equal to a height of the integrated circuit. A bump is spaced apart from the integrated circuit, and a redistribution layer electrically couples the bond pad of the integrated circuit to the bump. | 09-27-2012 |
20120171875 | RECONSTITUTED WAFER WARPAGE ADJUSTMENT - A system and method for reducing warpage of a semiconductor wafer. The system includes a device for securing the semiconductor wafer in a heating area. The device includes a holding mechanism for securing an edge of the semiconductor wafer. The device further includes a pressure reducing device that reduces the pressure underneath the semiconductor device, which further secures the semiconductor device in the heating area. The heating area includes a plurality of heating and cooling zones in which the semiconductor wafer is subjected to various temperatures. | 07-05-2012 |
20120171774 | CHEMICAL SENSOR WITH REPLACEABLE SAMPLE COLLECTION CHIP - A chemical sensor is provided on a first semiconductor die. A potentiostat is provided on a second semiconductor die. An analog to digital converter and a microcontroller are provided on a third semiconductor die. The first die is configured to be connected to the second die. The second die is configured to be connected to the third die. The chemical sensor detects a chemical in the surrounding environment and outputs a signal to the analog to digital converter. The analog to digital converter converts the signal to a digital signal and outputs the digital signal to the microcontroller. The microcontroller provides a measurement of the concentration of the chemical in the surrounding environment. | 07-05-2012 |
20120171713 | SINGLE CHIP HAVING THE CHEMICAL SENSOR AND ELECTRONICS ON THE SAME DIE - A semiconductor die includes a chemical sensor, a digital to analog converter, and microcontroller formed therein. The chemical sensor detects the presence of a chemical and outputs an analog signal to the digital to analog converter. The analog to digital converter converts the analog signal to a digital signal. The analog to digital converter outputs the digital signal to the microcontroller. Microcontroller calculates a value of the concentration of the selected chemical. | 07-05-2012 |
20120171372 | AUTOMATIC SHUTTER FOR ADHESIVE DISPENSER - In automated gluing systems for semiconductor device manufacture, an automatic shutter system is provided for use with an adhesive dispenser that is configured to deposit adhesive for joining elements during final assembly processes. A shutter is configured to interpose itself between a needle tip of the dispenser and a working surface, on which devices in process are positioned, while the dispenser is in a ready position and not actually delivering adhesive, and to withdraw from the interposed position as, or immediately before the needle tip descends to a dispensing position to deposit adhesive on a device. In this way, drops of adhesive that fall from the needle tip while in the ready position are captured by the shutter and prevented from falling onto a device in process in an unintended location of the device. | 07-05-2012 |
20120170352 | THERMO PROGRAMMABLE RESISTOR BASED ROM - An integrated circuit is formed having an array of memory cells located in the dielectric stack above a semiconductor substrate. Each memory cell has an adjustable resistor and a heating element. A dielectric material separates the heating element from the adjustable resistor. The heating element alters the resistance of the resistor by applying heat thereto. The magnitude of the resistance of the adjustable resistor represents the value of data stored in the memory cell. | 07-05-2012 |
20120168944 | THROUGH HOLE VIA FILLING USING ELECTROLESS PLATING - An embedded wafer level ball grid array (eWLB) is formed by embedding a semiconductor die in a molding compound. A trench is formed in the molding compound with a laser drill. A first layer of copper is deposited on the sidewall of the trench by physical vapor deposition. A second layer of copper is then formed on the first layer of copper by an electroless process. A third layer of copper is then formed on the second layer by electroplating. | 07-05-2012 |
20120168943 | PLASMA TREATMENT ON SEMICONDUCTOR WAFERS - A semiconductor package and method of forming the same is described. The semiconductor package is formed from a semiconductor die cut from a semiconductor wafer that has a passivation layer. The semiconductor wafer is exposed to ionized gas causing the passivation layer to roughen. The semiconductor wafer is cut to form a plurality of semiconductor dies each with a roughened passivation layer. The plurality of semiconductor dies are placed on an adhesive layer to form a reconstituted wafer, and an encapsulation layer is formed enclosing the adhesive layer and the plurality of semiconductor dies. The passivation layer is removed and the semiconductor package formed includes electrical contacts for establishing electrical connections external to the semiconductor package. | 07-05-2012 |
20120168942 | THROUGH HOLE VIA FILLING USING ELECTROLESS PLATING - An embedded wafer level ball grid array (eWLB) is formed by embedding a semiconductor die in a molding compound. A trench is formed in the molding compound with a laser drill. A first layer of copper is deposited on the sidewall of the trench by physical vapor deposition. A second layer of copper is then formed on the first layer of copper by an electroless process. A third layer of copper is then formed on the second layer by electroplating. | 07-05-2012 |
20120168938 | PLASMA TREATMENT ON SEMICONDUCTOR WAFERS - A semiconductor wafer has integrated circuits formed thereon and a top passivation layer applied. The passivation layer is patterned and selectively etched to expose contact pads on each semiconductor die. The wafer is exposed to ionized gas causing the upper surface of passivation layer to roughen and to slightly roughen the upper surface of the contact pads. The wafer is cut to form a plurality of semiconductor dies each with a roughened passivation layer. The plurality of semiconductor dies are placed on an adhesive layer and a reconstituted wafer formed. Redistribution layers are formed to complete the semiconductor package having electrical contacts for establishing electrical connections external to the semiconductor package, after which the wafer is singulated to separate the dice. | 07-05-2012 |
20120168929 | LOW COST THERMALLY ENHANCED HYBRID BGA AND METHOD OF MANUFACTURING THE SAME - A semiconductor package is formed having a substrate juxtaposed on at least two sides of a semiconductor die. Both the substrate and the semiconductor die are affixed to a conductive layer that draws heat generated during use of the semiconductor package away from the semiconductor die and the substrate. There are also electrical contacts affixed to the substrate and the semiconductor die. The electrical contacts facilitate electrical connection between the semiconductor die, the substrate, and any external devices or components making use of the semiconductor die. The substrate, semiconductor die, and at least a portion of some of the electrical contacts are enclosed by an encapsulating layer insulating the components. Portions of the electrical contacts not enclosed by the encapsulating layer are affixed to an outside device, such as a printed circuit board. | 07-05-2012 |
20120168888 | IMAGE SENSOR CIRCUIT, SYSTEM, AND METHOD - A process of forming optical sensors includes sealing an imaging portion of each of a plurality of optical sensors on a sensor wafer with a transparent material. The operation of sealing leaves a bonding portion of each of the optical sensors exposed. The process further includes cutting the wafer into a plurality of image sensor dies after sealing the optical sensors such that each image sensor die includes one of the optical sensors sealed with a corresponding portion of the transparent material. | 07-05-2012 |
20120168882 | INTEGRATED CHEMICAL SENSOR - A integrated circuit die includes a chemical sensor, a thermal sensor, and a humidity sensor formed therein. The chemical sensor, thermal sensor, and humidity sensor include electrodes formed in a passivation layer of the integrated circuit die. The integrated circuit die further includes transistors formed in a monocrystalline semiconductor layer. | 07-05-2012 |
20120168754 | THIN FILM METAL-DIELECTRIC-METAL TRANSISTOR - A transistor is formed having a thin film metal channel region. The transistor may be formed at the surface of a semiconductor substrate, an insulating substrate, or between dielectric layers above a substrate. A plurality of transistors each having a thin film metal channel region may be formed. Multiple arrays of such transistors can be vertically stacked in a same device. | 07-05-2012 |
20120167392 | RAZOR WITH CHEMICAL AND BIOLOGICAL SENSOR - A razor has an electrochemical sensor for sensing various characteristics, such as biological, chemical, temperature, humidity, and pressure. The electrochemical sensor is positioned within a razor head of the razor, but may be attached to and enclosed in the razor head housing or attached to a razor blade of the razor. The electrochemical sensor may be positioned at different locations within the housing and on the razor blades. The electrochemical sensor may be positioned such that a sensing surface is exposed to a shaving surface of a patient. The razor may also have various electrical components for processing signals generated by the electrochemical sensor and determining the presence or concentration of a chemical or biological marker. The data associated with the signals may be displayed, transmitted to a separate computing device, or stored in a memory. | 07-05-2012 |
20120162788 | LENS ALIGNMENT APPARATUS AND METHOD - Lens alignment apparatuses, methods and optical devices are disclosed. In accordance with various embodiments, a lens alignment apparatus may include at least one lens element positioned in a lens body. A lens alignment interface coupled to the lens element may be configured to permit the lens element to be angularly deflected relative to an axis of symmetry of the lens body. In other embodiments, a method of improving the resolution of an optical device may include translating a lens along an optical axis to maximize resolution at a first location, and determining a resolution in a second location in the imaging plane. The resolution in the second location may be improved by angularly deflecting the lens, and the position of the lens may then be fixed. | 06-28-2012 |
20120161332 | METHOD FOR PRODUCING VIAS IN FAN-OUT WAFERS USING DRY FILM AND CONDUCTIVE PASTE, AND A CORRESPONDING SEMICONDUCTOR PACKAGE - A process for manufacturing semiconductor packages is provided, that includes drilling blind apertures in a reconstituted wafer, adhering a dry film resist on the wafer over the apertures, and patterning the film to expose a space around each of the apertures. The apertures and spaces are then filled with conductive paste by wiping a quantity of the paste across a surface of the film so that paste is forced into the spaces and apertures. The spaces around the apertures define contact pads whose thickness is constrained by the thickness of the film, preferably to about 10 μm or less. To prevent paste from trapping air pockets in the apertures, the wiping process can be performed in a chamber from which much or all of the air has been evacuated. After curing the paste, the wafer is thinned from the back to expose the cured paste in the apertures. | 06-28-2012 |
20120161319 | BALL GRID ARRAY METHOD AND STRUCTURE - A process for making an integrated circuit, a wafer level integrated circuit package or an embedded wafer level package includes forming copper contact pads on a substrate or substructure. The substructure may include devices and the contact pads may be used for forming electrical couplings to the devices. For example, copper plating may be applied to a substructure and the copper plating etched to form copper contact pads on the substructure. An etching process may be applied to remove barrier layer material on the substructure, such as adjacent to the copper pads. For example, a hydrogen peroxide etch may be applied to remove titanium-tungsten from a surface of the substructure. The pads are again etched to remove barrier layer etchant, byproducts and/or oxide from the pads. Contamination control steps may be performed, such as quick-dump-and-rinse (QDR) and spin-rinse-and-dry (SRD) processing. | 06-28-2012 |
20120153358 | INTEGRATED HEAT PILLAR FOR HOT REGION COOLING IN AN INTEGRATED CIRCUIT - The thermal energy transfer techniques of the disclosed embodiments utilize passive thermal energy transfer techniques to reduce undesirable side effects of trapped thermal energy at the circuit level. The trapped thermal energy may be transferred through the circuit with thermally conductive structures or elements that may be produced as part of a standard integrated circuit process. The localized and passive removal of thermal energy achieved at the circuit level rather just at the package level is both more effective and more efficient. | 06-21-2012 |
20120139076 | THERMOELECTRIC COOLER SYSTEM, METHOD AND DEVICE - A semiconductor thermoelectric cooler includes P-type and N-type thermoelectric cooling elements. The P-type and N-type thermoelectric elements have a first portion having a first cross-sectional area and a second portion having a second cross-sectional area larger than the first cross-sectional area. The P-type and N-type thermoelectric cooling elements may, for example, be T-shaped or L-shaped. In another example, the thermoelectric cooling elements have a first surface having a first shape configured to couple to a first electrical conductor and a second surface opposite the first surface and having a second shape, different from the first shape, and configured to couple to a second electrical conductor. For example, the first surface may have a rectilinear shape of a first area and the second surface may have a rectilinear shape of a second area different from the first area. The semiconductor thermoelectric cooler may be manufactured using thin film technology. | 06-07-2012 |
20120139075 | THERMOELECTRIC COOLER SYSTEM, METHOD AND DEVICE - A semiconductor thermoelectric cooler is configured to direct heat through channels of the cooler. The thermoelectric cooler has multiple electrodes and a first dielectric material positioned between side surfaces of the electrodes. A second dielectric material, different from the first dielectric material, is in contact with top surfaces of the electrodes. The first dielectric material extends above the top surface of the electrodes, separating portions of the second dielectric material, and is in contact with a portion of the top surfaces of the electrodes. The first dielectric material has a thermal conductivity different than a thermal conductivity of the second dielectric material. A ratio of the first dielectric material to the second dielectric material in contact with the top surface of the electrodes may be selected to control the heat retention. The semiconductor thermoelectric cooler may be manufactured using thin film technology. | 06-07-2012 |
20120112873 | VIALESS INTEGRATION FOR DUAL THIN FILMS - THIN FILM RESISTOR AND HEATER - A process is described for integrating two closely spaced thin films without deposition of the films through deep vias. The films may be integrated on a wafer and patterned to form a microscale heat-trimmable resistor. A thin-film heating element may be formed proximal to a thin-film resistive element, and heat generated by the thin-film heater can be used to permanently trim a resistance value of the thin-film resistive element. Deposition of the thin films over steep or abrupt topography is minimized by using a process in which the thin films are deposited in a sequence that falls between depositions of thick metal contacts to the thin films. | 05-10-2012 |
20120098104 | SHIELDING TECHNIQUES FOR AN INTEGRATED CIRCUIT - Described herein are techniques for forming, during wafer processing, a conductive shielding layer for a chip formed from a wafer. The conductive shielding layer can be formed on multiple sides of a chip prior to dicing the wafer to separate the chip from the wafer. A wafer may be processed to form trenches that extend substantially through the wafer. The trenches may be formed opposite scribe lines that identify boundaries between chips of the wafer and may extend through the wafer toward the scribe lines. A shielding layer may be formed along the trenches. | 04-26-2012 |
20120042823 | SUSCEPTOR SUPPORT SYSTEM - The present disclosure is directed to a susceptor support that includes a hub and a plurality of arms extending radially from the hub, where each arm has a terminal end positioned away from the hub. The susceptor support also includes a plurality of elongated rectangular tips formed at the terminal end of each arm, each tip having a length and a width, wherein the length is greater than the width. | 02-23-2012 |
20120038043 | MANUFACTURING FAN-OUT WAFER LEVEL PACKAGING - Fan-out wafer level packaging includes an integrated circuit having a top surface, a bottom surface and a bond pad defined on the top surface, and a substrate having a cavity. An adhesive layer is positioned between a top surface of the cavity and the bottom surface of the integrated circuit, and a bump is positioned proximate a top surface of the fan-out wafer level packaging, the bump spaced apart from the integrated circuit. A redistribution layer is configured to electrically couple the bond pad of the integrated circuit to the bump. | 02-16-2012 |
20090057544 | CAMERA MODULE LENS CAP - A camera module lens cap is provided to protect a camera module in a mobile device where the camera module is exposed. The camera module lens cap includes an optically transparent member for positioning adjacent a camera lens, and a housing for carrying the optically transparent member. The housing includes an overhanging lip for engaging a base of the camera module. | 03-05-2009 |