SMSC Holdings S.a.r.l.
|SMSC Holdings S.a.r.l. Patent applications|
|Patent application number||Title||Published|
|20130336435||Communication System and Method for Synchronizing a Plurality of Network Nodes After a Network Lock Condition Occurs - A communication system and method is provided herein for synchronizing a plurality of network nodes after a network lock condition occurs within a network. According to one embodiment, the method may generate a local trigger signal simultaneously at each of the plurality of network nodes by compensating for unique phase delays attributed to each of the plurality of network nodes. As described herein, the local trigger signals may be used for synchronizing devices, such as multimedia devices, which may be coupled to the network nodes. More specifically, the local trigger signals may be used to synchronize events occurring within devices, which are coupled to different nodes of the network.||12-19-2013|
|20130318205||MULTI-MEDIA FILE EMULATION DEVICE - An emulation device is used to stream media content from a digital media server to a digital media renderer. The emulation system receives a pulse code modulation data stream from the digital media server via a network interface, and stores the data in a buffer. The emulation system is attachable to the digital media renderer, and is recognized as a storage device containing an emulated media file. When the digital media renderer plays the emulated media file, the emulation device reads the PCM data from the buffer to use as sound or video data of the emulated media file.||11-28-2013|
|20130297829||POINT-TO-POINT SERIAL PERIPHERAL INTERFACE FOR DATA COMMUNICATION BETWEEN DEVICES CONFIGURED IN A DAISY-CHAIN - The present disclosure provides an improved point-to-point serial peripheral interface, a system comprising an improved point-to-point serial peripheral interface, and a method for use in a system comprising an improved point-to-point serial peripheral interface. A master comprises a SPI initiating port. Each slave comprises at least one SPI receiving port and at least one SPI forwarding port. The master provides a set of SPI signals to the SPI receiving port of the first slave in the chain, and the entire SPI signals are forwarded via the SPI forwarding port of each of the slaves until the SPI transaction reaches a target slave, which is identified by an in-band device addressing mechanism.||11-07-2013|
|20130223515||Flicker Reduction Circuit and Method for Compressed Video Transmission - A system, circuit and method are provided herein for reducing perceived flicker in video images transmitted using compression and bit rate control. According to one embodiment of the method, a parameter used in the video compression scheme is stored. The parameter stored is one that is subject to adjustment during normal operation of the video compression scheme. Compressed video frame data issued by a compression encoder is used to test for a still-picture condition. When a still-picture condition is detected, the value of the parameter used by the video compression scheme is fixed to the stored value for the duration of the still-picture condition. An embodiment of the system includes an encoder, buffer, bit rate controller, and flicker reduction circuit. An embodiment of the flicker reduction circuit includes a still-picture detection circuit operably coupled to a compressed data path beginning at the output of the encoder.||08-29-2013|
|20130073777||Switching System which Allows Primary USB Connection in Response to USB Signaling - System and method controlling connectivity within a device. A device may be coupled to a host device. In response to the coupling, low power logic (e.g., an embedded device) of the device may be coupled to the host device. The low power logic may perform enumeration with the host device using only power provided by the host device. The low power logic may also charge a battery of the device using power provided by the host device. Device circuitry of the device may provide a signal for coupling to the host device. In response, the device circuitry may be coupled to the host device and may perform device enumeration with the host device.||03-21-2013|
|20120275493||Low-Power Class D Amplifier Using Multistate Analog Feedback Loops - An audio amplifier system may include an audio CODEC/output (AOP) path featuring analog class-D amplifiers, and using Natural Sampling Pulse Width Modulation (PWM) to convert an analog input into a series of Rail-to-Rail pulses. The audio signal may be encoded in the average value of the PWM pulse train and may be recovered from the PWM signal by analog low pass filtering. The Class-D amplifiers may be designed with a negative feedback loop/network to compare the output signal with the input signal and suppress non-idealities introduced by the Class-D switching stage. Furthermore, operation of the AOP may be designed according to a separate signal transfer function and a separate noise transfer function, and 2||11-01-2012|
|20120274370||Reducing Spurs in Injection-Locked Oscillators - Various embodiments of a radio-frequency (RF) transmitter receiver circuit that utilizes an injection locked oscillator may allow for the introduction of a DC offset to correct the RF signal. The DC offset may be adjusted to eliminate (or minimize) even order harmonics to correct for RF effects. The DC offset correction may be performed around the injection locked oscillator to target even order terms.||11-01-2012|
|20120201126||Fault Tolerant Network Utilizing Bi-Directional Point-to-Point Communications Links Between Nodes - A data communication system and an associated network node implementation is disclosed that, in certain embodiments, uses single-channel bi-directional communication links between nodes to send frames of data. The network nodes can be connected together in a ring or daisy chain topology with data frames sent in alternating directions through the bi-directional links. Such networks initially configured in a physical ring topology can tolerate single point failures by automatically switching to a logical daisy chain topology.||08-09-2012|
Patent applications by SMSC Holdings S.a.r.l.