Shanghai IC R&D Center Co., Ltd. Patent applications |
Patent application number | Title | Published |
20140351779 | INTEGRATED CIRCUIT (IC) DESIGN METHOD WITH ENHANCED CIRCUIT EXTRACTION MODELS - A method is provided for designing an IC chip. The method includes receiving data from a pre-layout design process for the IC chip, routing a plurality of interconnecting wires to connect various devices of the IC chip, and extracting various circuit parameters. The method also includes simulating the IC chip using the extracted various circuit parameters to detect logic or timing error in the IC chip. The extracting the various circuit parameters includes establishing a statistical interconnect technology profile (ITP) file containing at least interconnect parasitic parameters based on correlations of interconnect layer geometric parameter variations. | 11-27-2014 |
20140217550 | METAL FILM RESISTOR STRUCTURE AND MANUFACTURING METHOD - A method is provided for manufacturing a semiconductor device with a metal film resistor structure. The method includes providing an insulation layer on the semiconductor device. A lower copper interconnect is formed in the insulation layer. The method also includes forming a cap layer on the insulation layer and the lower copper interconnect and etching the cap layer based on a single photolithography mask to form a window exposing portion of the lower copper interconnect and portion of the insulation layer. Further, the method includes forming a metal film layer on the cap layer and inside the window such that exposed portion of the lower copper interconnect is connected with part of the metal film layer within the window. The method also includes performing a chemical mechanical polishing (CMP) process to form a metal film resistor based on the metal film layer. The metal film resistor is connected with the portion of the lower copper interconnect. | 08-07-2014 |
20140151455 | RADIO FREQUENCY IDENTIFICATION (RFID) TAG AND MANUFACTURING METHODS THEREOF - A radio frequency identification (RFID) device is disclosed. The RFID device includes a silicon substrate having a top side and a bottom side. The RFID device also includes a plurality of circuitry layers formed on the top side of the substrate, and the plurality of circuitry layers include at least a core circuitry and an on-chip antenna. Further, the RFID device includes a plurality of deep openings formed in the substrate on the bottom side under the plurality of circuitry layers. The plurality of deep openings are arranged in an array and through a substantial portion of the substrate, and a remaining portion of the substrate unreached by the plurality of deep openings separates the plurality of deep openings and the plurality of circuitry layers. | 06-05-2014 |
20140138835 | COPPER INTERCONNECT STRUCTURE AND METHOD FOR MANUFACTURING THE SAME - A method is disclosed for manufacturing a semiconductor device with a copper interconnect structure. The method includes providing a substrate, forming a first interconnect dielectric layer on the substrate, and forming a second interconnect dielectric layer on a surface of the first interconnect dielectric layer. The method also includes forming a plurality of conduits extending through the first interconnect dielectric layer and the second interconnect dielectric layer, and depositing copper in the plurality of conduits to form a copper interconnect layer of the copper interconnect structure. Further, the first interconnect dielectric layer, between neighboring conduits, contains cavities such that dielectric constant of the first interconnect dielectric layer is reduced. The second interconnect dielectric layer seals the top of the cavities, the substrate is the bottom of the cavities, and a width of the top of the cavities is less than a width of the bottom of the cavities. | 05-22-2014 |
20140138829 | INTERCONNECTION STRUCTURE AND METHOD FOR FABRICATING THE SAME - The present invention relates to an interconnection structure and a method for fabricating the same. According to the present invention, cavities are formed between the interconnection dielectric by using a sacrificial layer, carbon nanotubes are used as the interconnection material for local interconnection between via holes, graphene nanoribbons are used as the interconnection material for metal lines, and cavities are included in the interconnection dielectric. In addition, the conventional CMOS BEOL Cu interconnection technique is applied to the intermediate interconnection level and the global interconnection level. In this way, the high parasitic resistance and parasitic capacitance in the Cu interconnection technique, which may occur when the local interconnection is relatively small in size, can be effectively overcome. | 05-22-2014 |
20130002502 | MULTI-SYSTEM MULTI-BAND RFID ANTENNA - The present invention provides a multi-system multi-band RFID antenna, which comprises an on-chip antenna and at least one external antenna, wherein the on-chip antenna is arranged on RFID chip; the external antennas are arranged outside the RFID chip; and the RFID chip is provided with connection pads on the outer surface, wherein both the on-chip antenna and the external antennas are connected with the RFID chip through the connection pads. According to the multi-system multi-band RFID antenna of the present invention, the RFID chip can provide appropriate antennas for applications in different systems with different frequency bands, and can satisfactorily meet the need for RFID multi-system integration applications in the future. | 01-03-2013 |
20110039405 | METHOD FOR FABRICATING A SONOS MEMORY - The present invention provides a method for making SONOS memory, comprising the following steps: depositing silicon oxide layer and silicon oxynitride layer in sequence on underlayer; coating a layer of photoresist on the silicon oxynitride layer; removing part of the photoresist and form the logic area; removing silicon oxynitride layer in the logic area; removing the bottom oxide layer in the logic area; growing top oxide layer on the silicon oxynitride layer and logic area; removing the top oxide layer in the logic area; growing gate oxide layer; forming device structure of SONOS and logic area. The present invention can avoid the damage of top oxide layer and lateral etching in wet etching so as to improve the defect-free rate of devices. | 02-17-2011 |
20100311244 | DOUBLE-EXPOSURE METHOD - The present invention discloses a double-exposure method comprising a first lithography process and a second lithography process. Between the first and the second lithography process, coat Resolution Enhancement Lithography Assisted by Chemical Shrink (RELACS) material on the first photoresist pattern, promote thermal crosslinking reaction at the interface between the RELACS materials and the first photoresist pattern; afterwards, remove the RELACS material which does not crosslink with the first photoresist pattern. This method not only realizes higher lithography resolution, but also avoids the adverse effects of the second exposure on the first photoresist pattern in double-exposure technology. | 12-09-2010 |