SEAKR Engineering, Inc.
|SEAKR Engineering, Inc. Patent applications|
|Patent application number||Title||Published|
|20140281802||MULTI-DIMENSIONAL ERROR DETECTION AND CORRECTION MEMORY AND COMPUTING ARCHITECTURE - Error correction and detection may be performed across multiple dimensions of memory storage, such as across two or more complete memory devices, as well as within individual pages of memory within a single memory device. Error correction and detection performed across two or more complete memory devices may mitigate single event functional interrupts that affect a complete memory device. Error detection and correction performed within individual pages of memory may be used to mitigate single event upset induced single and multiple bit flips within a page of a memory device. A parallel or serial block code, such as a parallel or serial block Reed-Solomon code or any other type of error correcting code, may be used for error correction and detection performed across two or more complete memory devices or within individual pages of memory within a single memory device.||09-18-2014|
|20130297847||DISTRIBUTED MESH-BASED MEMORY AND COMPUTING ARCHITECTURE - Methods, systems, and devices for distributed computing are provided. Clusters of nodes are provided, each node have a communication link to a primary I/O switch as well as to two other nodes, thereby providing redundant alternative communication paths between different components of the system. Primary and redundant I/O switching modules may provide further redundancy for high availability and high reliability applications, such as applications that may be subjected to the environment as would be found in space, including radiation effects. Nodes in a cluster may provide data storage, processing, and/or input/output functions, as well as one or more alternate communications paths between system components. Multiple clusters of nodes may be coupled together to provide enhanced performance and/or reliability.||11-07-2013|