NEPES CORPORATION Patent applications |
Patent application number | Title | Published |
20130241042 | SEMICONDUCTOR CHIP PACKAGE, SEMICONDUCTOR MODULE, AND METHOD FOR MANUFACTURING SAME - In one embodiment, a semiconductor chip package includes an insulation frame having an opening part formed in a center thereof and a via hole formed around the opening part; a semiconductor chip disposed cm the opening part; a conductive part filling the via hole; an inner insulation layer formed on bottom surfaces of the semiconductor chip and the insulation frame so as to expose a bottom surface of the conductive part; and an inner signal pattern formed on the inner insulation layer and electrically connecting the semiconductor chip and the conductive part. Embodiments also relate to a semiconductor module including a vertical stack of a plurality of the semiconductor chip packages, and to a method for manufacturing the same. | 09-19-2013 |
20120286419 | SEMICONDUCTOR PACKAGE WITH INTERPOSER BLOCK THEREIN - A semiconductor package substrate is provided. The package substrate includes a mold base and an interposer block embedded in the mold base, said interposer block having a plurality of vertical conductive lines therein. A metallization layer is formed on the surface of the interposer block or the mold base, said metallization layer being electrically connected to at least one of the vertical conductive lines. A semiconductor chip may be mounted on or embedded in the mold base. | 11-15-2012 |
20120146216 | SEMICONDUCTOR PACKAGE AND FABRICATION METHOD THEREOF - A semiconductor package is provided. The package includes a package substrate with a first surface and a second surface on the opposite side, and a plurality of via sets connecting vertically the first surface with the second surface, said via sets having a plurality of micro vias and filled with conductive material. The micro vias are grouped together, and the distance between micro vias in the via set is smaller than the distance between neighboring via sets. | 06-14-2012 |
20110285015 | BUMP STRUCTURE AND FABRICATION METHOD THEREOF - There is provided a bump structure for a semiconductor device, comprising a metal post formed on and electrically connected to an electrode pad on a substrate, a solder post formed on the top surface of the metal post, said solder post having the same horizontal width as the metal post and the top surface of the solder post being substantially rounded, and an intermetallic compound layer disposed at the interface between the metal post and the solder post. An oxide layer formed on the solder post prevents solder post under reflow from being changed into a spherical shape. An intermetallic compound layer may be formed by an aging process at the interface between the metal post and the solder post. The bump structure can realize fine pitch semiconductor package without a short between neighboring bumps. | 11-24-2011 |
20110260336 | WAFER LEVEL SEMICONDUCTOR PACKAGE AND FABRICATION METHOD THEREOF - A wafer level semiconductor package is provided. A warpage control barrier line formed in every package of a single wafer prevents wafer from warping. The changed shape of the interface between a semiconductor chip and a molding layer at the edge of the package disperses stress applied to the outside of the package, and suppress the generation and propagation of crack. The size of the package is reduced to that of the semiconductor, and the thickness of the package is minimized. | 10-27-2011 |
20100032831 | BUMP STRUCTURE FOE SEMICONDUCTOR DEVICE - There is provided a bump structure for a semiconductor device, comprising a first metal layer, and a second metal layer electrically connected to the first metal layer so as to be integrally formed with the first metal layer, and electrically connected to electrode pads of the semi-conductor device, in which the second metal layer is composed of one or more metals or alloys having the melting point higher than the melting point of the first metal layer or the eutectic temperature of the first metal layer and another substance when the first metal layer makes a fusion reaction to the surface of the another substance. Preferably, the second metal layer may have a thickness greater than that of the first metal layer. The bump structure may further comprise a diffusion prevention layer between the first metal layer and the second metal layer. | 02-11-2010 |
20090283903 | BUMP WITH MULTIPLE VIAS FOR SEMICONDUCTOR PACKAGE AND FABRICATION METHOD THEREOF, AND SEMICONDUCTOR PACKAGE UTILIZING THE SAME - A bump for a semiconductor package forms a polymer layer having multiple vias on an electrode pad above a semiconductor chip to increase an electrical contact area between the electrode pad and a metal bump. Further, the bump forms a polymer layer having multiple vias on a redistribution electrode pad to increase a surface area of an electrode interconnection. The multiple vias increase electrical and mechanical contact areas, thereby preventing current crowding and improving joint reliability. The bump for a semiconductor package may further comprise a stress relaxation layer at the lower portion of the bump. | 11-19-2009 |
20090146281 | SYSTEM IN PACKAGE AND FABRICATION METHOD THEREOF - There is provided a system-in-package including: a substrate of a sawed base wafer on which a semiconductor circuit is formed; a conductive post formed on a top surface of the substrate; at least one semiconductor chip stacked on the top surface of the substrate; a buried layer formed on the top surface of the substrate so as to cover at least partially the conductive post and the semiconductor chip; and an external connection bump electrically connected to the conductive post. The system-in-package is fabricated by stacking a plurality of semiconductor chips on a top surface of a base wafer, forming a buried layer, realizing an electrical path by a conductive post, and polishing top and bottom surfaces of the package, thereby thinning the thickness of the package. Further, the system-in-package greatly improves electrical operation characteristics and increases productivity. | 06-11-2009 |
20090091001 | CRACK RESISTANT SEMICONDUCTOR PACKAGE AND METHOD OF FABRICATING THE SAME - There are provided a semiconductor package comprising: a semiconductor substrate including an integrated circuit unit, and a crack-propagation preventing unit at least partially formed around a peripheral of the integrated circuit unit of the semiconductor substrate and filled with a heterogeneous material different from a material of the semiconductor substrate, and a method of fabricating the semiconductor package, comprising: at least partially forming a trench around the peripheral of the integrated circuit unit of the semiconductor substrate, and filling the trench with a heterogeneous material different from that of the semiconductor substrate. In accordance with the present invention, the structural and mechanical strength and durability of the semiconductor package, specifically, the wafer level semiconductor package, are improved and the reliability of the product is significantly improved. Furthermore, a fail rate including crack/chipping during a subsequent mounting process lowers, to improve the yield and reduce the whole manufacturing cost. | 04-09-2009 |
20090032942 | SEMICONDUCTOR CHIP WITH SOLDER BUMP AND METHOD OF FABRICATING THE SAME - A semiconductor chip having a solder bump and a method of fabricating the same are provided. The semiconductor chip includes at least one under bump metal (UBM) layer formed on an electrode pad of the semiconductor chip, an adhesion enhance layer (AEL) formed on the UBM layer and having at least one concavo-convex portion on a top surface thereof, and the solder bump formed on the AEL. Thereby, adhesive solder bump is increased, and thereby the reliability of the semiconductor chip can be improved. Further, it is possible to prevent tin (Sn) in the solder bump from being diffused due to the AEL. | 02-05-2009 |
20090020871 | SEMICONDUCTOR CHIP WITH SOLDER BUMP SUPPRESSING GROWTH OF INTER-METALLIC COMPOUND AND METHOD OF FABRICATING THE SAME - A semiconductor chip having a solder bump and a method of fabricating the same are provided. Conventionally, an inter-metallic compound (IMC) unexpectedly grows at an interface of the solder bump by means of heat generated during operation of the semiconductor chip, thereby weakening mechanical property of the semiconductor chip. To solve this drawback, the semiconductor chip includes at least one metal adhesion layer formed on an electrode pad of the semiconductor chip, an interlayer isolation layer formed on the metal adhesion layer, at least one penetration layer formed on the interlayer isolation layer and penetrating into the solder bump, and the solder bump formed on the penetration layer. Thereby, materials of the penetration layer penetrate into the solder bump to change the solder bump into a multi-component solder bump, so that the growth of the IMC is suppressed, and the reliability of the semiconductor chip can be improved. | 01-22-2009 |
20090008762 | ULTRA SLIM SEMICONDUCTOR PACKAGE AND METHOD OF FABRICATING THE SAME - There is provided an ultra slim semiconductor package comprising: a multilayer thin film layer including at least one or more dielectric layers and at least one or more redistribution layers; at least one semiconductor chip electrically connected to the redistribution layer and mounted on the multilayer thin film layer; conductive structures electrically connected to the redistribution layer and each formed in a post shape at one side of the multilayer thin film layer; a molding part formed on the multilayer thin film layer and at least partially covering the conductive structures and the semiconductor chip; and bumps for external connection formed on the molding part and electrically connected to the conductive structures. The semiconductor package according to the present invention enables mass production at wafer level, is easily stacked between the packages, and has an excellent electrical characteristic. Further, since the package thickness is very thin, the semiconductor package contributes to the slimming of diverse electronic products. | 01-08-2009 |
20080290496 | WAFER LEVEL SYSTEM IN PACKAGE AND FABRICATION METHOD THEREOF - There is provided a system-in-package (SiP), which includes a substrate obtained by cutting a wafer for each unit system; one or more first electronic devices mounted on the substrate by a heat radiation plate; a plurality of interlayer dielectrics sequentially formed on the substrate; and one or more second electronic devices buried between or in the interlayer dielectrics on the substrate. A heat sink may be additionally attached to the bottom surface of the substrate. In this case, a thermal conduction path including heat pipes connecting the heat radiation plate on the substrate and the heat sink is formed. In the SiP, various types of devices are buried at a wafer level, so that a more integrated semiconductor device is implemented corresponding to demand for a fine pitch. Further, the heat radiation of a device required in high-speed operation and high heat generation is maximized due to the multi-stepped heat radiation structure, and thus the operation of the device is more stabilized. | 11-27-2008 |
20080203583 | SEMICONDUCTOR PACKAGE AND FABRICATION METHOD THEREOF - There is provided a semiconductor package comprising: a multilayer thin film structure including a plurality of dielectric layers and at least one or more redistribution layers; a semiconductor chip positioned at one side of the multilayer thin film structure and electrically connected to the redistribution layer; and a solder bump formed at the other side of the multilayer thin film structure. The multilayer thin film structure functions as the substrate for the semiconductor package and realizes the light, thin, short and small BGA package without any additional substrate. A plurality of the packages can be simultaneously formed at wafer level or carrier level, to simplify the process and to be favorable for mass production. After the semiconductor chips are formed at wafer level, only the semiconductor chips having the excellent operation characteristic through the test are selectively bonded to the multilayer thin film structure, to provide the high quality package products in which the fault rate is maximally reduced. The light, thin, short and small BGA package according to the present invention enables small and slim communication devices, displayers and other diverse electronic devices, to be contributed to the increase of the competitiveness of the products to which the BGA package is applied. | 08-28-2008 |