LAPIS Semiconductor Co., Ltd. Patent applications |
Patent application number | Title | Published |
20160118938 | SEMICONDUCTOR DEVICE AND MEASUREMENT DEVICE - A semiconductor device includes an electronic component that includes an oscillator and has terminals on one face. A semiconductor chip is electrically connected to the electronic component and also includes terminals on one face thereof. The electronic component and the semiconductor chip are mounted to a mounting base such that the terminals of the electronic component and the terminals of the semiconductor chip face in the same direction. First bonding wires are connected to the terminals of the semiconductor chip, and second bonding wires having an apex height smaller than that of the first bonding wires connect the terminals of the electronic component to the terminals of the semiconductor chip. A sealing member completely seals within at least the electronic component. | 04-28-2016 |
20160093389 | NONVOLATILE SEMICONDUCTOR MEMORY - A nonvolatile semiconductor memory can reduce variations in an amount of current during data writing operation. This allows for the writing of data to memory cells with high precision. The nonvolatile semiconductor memory includes a plurality of memory cells, word lines connected to the memory cells, and bit lines connected to each of the memory cells. At least two of the bit lines are selected, and a current is simultaneously supplied from a power supply line to those memory cells which are connected to the selected bit lines in order to write data thereto. The nonvolatile semiconductor memory also includes charge amount measurement units for measuring respective amounts of charge stored in the memory cells. The nonvolatile semiconductor memory also includes current path switching circuits connected to the respective bit lines. Those current path switching circuits which are connected to the selected bit lines supply a current from the power supply line to the memory cells or a predetermined terminal depending on a measured value of the amount of charge measured by the charge amount measurement section. | 03-31-2016 |
20160093245 | AMPLIFIER AND DISPLAY DRIVER INCLUDING AMPLIFIER - When an amplifier supplies to a drive line a driving signal based on an input voltage corresponding to a data value indicated by input data, and feeds to an output line a current corresponding to a voltage value on the drive line, the amplifier precharges the drive line at start of increase or decrease of the input voltage. Furthermore, the amplifier stops the precharge when the data value indicated by the input data is smaller than a reference value, or when a difference between a data value at present and a data value immediately therebefore in a series of data values indicated by the input data is smaller than a reference difference value. | 03-31-2016 |
20160086648 | FERROELECTRIC RANDOM ACCESS MEMORY - A ferroelectric random access memory which comprises a memory cell matrix constituted by a plurality of 1T1C type memory cells of j rows and k columns, and having j bit lines, k word lines, and k plate lines, each of the plurality of memory cells being connected to one of the j bit lines and one pair of the k word lines and the k plate lines, a plate line drive circuit which selectively applies one of a first potential and a second potential having a higher potential level than the first potential to one plate line of the k plate lines, and an equalizing circuit which performs an equalizing process in which the first potential is applied to each of the j bit lines. The plate line drive circuit applies a third potential having a potential level between the first and second potentials to the one plate line, before starting the equalizing process by the equalizing circuit. | 03-24-2016 |
20160079926 | AMPLIFYING CIRCUIT - An amplifying circuit includes a first differential amplifier (first differential pair) and a second differential amplifier (second differential pair) having an input capacitance smaller than the first differential amplifier. The amplifying circuit switches between the first differential amplifier (first differential pair) and the second differential amplifier (second differential pair) in response to an amplification mode setting signal to perform amplification processing of an input signal. | 03-17-2016 |
20160071479 | DRIVER CIRCUIT - A driver circuit driving a display device comprises: a gradation voltage generating circuit for generating m gradation voltages (m is an integer larger than or equal to 2) indicative of m stages of gradation levels; n decoder circuits each configured to select, out of the m gradation voltages, n drive voltages (n is an integer larger than or equal to 2) corresponding to n data pieces on the basis of n input gradation signals; m gradation voltage wirings each for transferring the m gradation voltages to the n decoder circuits, respectively; and a charge supplementing circuit for supplementing each of the m gradation voltage wirings with an amount of electric charge when a voltage drop occurs in the gradation voltage wirings. | 03-10-2016 |
20160071472 | DISPLAY DEVICE, DISPLAY PANEL DRIVER, AND IMAGE DATA SIGNAL TRANSMISSION METHOD - For each unit transmission block having a pixel data block including at least one pixel data piece, clock data is added contiguously to a head of the pixel data block. If no data transition has occurred at a boundary between the clock data and the pixel data block, logic inversion is performed on the pixel data piece. Thereafter, a transmission image data signal in which unit transmission blocks, each constituted by adding an inversion flag immediately before the clock data, are consecutively arranged is transmitted to a display panel driver. The driver generates a clock signal on the basis of the clock data included in the received signal and takes in the pixel data piece or the resultant obtained by inverting the logic level of this pixel data piece in accordance with the clock signal on the basis of the inversion flag. | 03-10-2016 |
20160071453 | DIFFERENTIAL AMPLIFIER AND DISPLAY DRIVER INCLUDING THE SAME - When the offsets of the first and second differential units have polarities different from each other, the first and second differential units are both set to a normal connection state, i.e., a state in which the input voltage is supplied to the first input terminal of each of the first and second differential units and the output voltage is supplied to the second input terminal of each of the first and second differential units. When the offsets of the first and second differential units have the same polarity, on the other hand, the first differential unit is set to the above normal connection state and the second differential unit is set to a chopping connection state in which the output voltage is supplied to the first input terminal and the input voltage is supplied to the second input terminal. | 03-10-2016 |
20160065135 | HIGH-FREQUENCY AMPLIFIER CIRCUIT - A high-frequency amplifier circuit comprising a first and a second amplification units connected in cascade structure and so on. The first amplification unit includes an FET of a first conductivity type having a source terminal supplied with a first potential, and a first inductor connected to an intermediate potential line, and the second amplification unit includes an FET of a second conductivity type having a source terminal supplied with a second potential, and a second inductor connected to the intermediate potential line. The intermediate potential line is supplied with an intermediate potential between the first and second potentials. The first and second amplification units are supplied with bias voltages by a first and a second bias units, respectively. An operating current for the second bias unit is controlled on the basis of the intermediate potential. | 03-03-2016 |
20160063957 | DISPLAY DRIVER - A display driver is provided which can prevent concentration of currents flowing into a display device and display a high-quality image without uneven luminance. A plurality of delayed clock signals used to apply a plurality of pixel driving voltages to data lines of the display device at respective different timings are generated by a DLL circuit including a variable delay circuit group constituted by variable delay circuits are connected in series, and a phase comparator that detects a phase difference of a delayed clock signal with respect to a reference clock signal and adjusts a delay amount of each of the variable delay circuits so that the phase difference converges to zero. | 03-03-2016 |
20160056163 | NON-VOLATILE MEMORY AND SEMICONDUCTOR DEVICE - There is provided a non-volatile memory including: plural zener zap devices, each including a cathode region and an anode region formed in a well; and a metal wiring line that is formed above the plural zener zap devices, that is commonly connected to each of the cathode regions, and that supplies a write voltage to each of the zener zap devices. | 02-25-2016 |
20160055795 | DISPLAY DRIVE CIRCUIT INCLUDING AN OUTPUT TERMINAL - A display drive circuit formed in a chip manufactured by a chip on glass implementation, which is connected to lead lines formed on a glass substrate, includes a rectangularly-shaped substrate, a power supply line formed on the substrate, the line being elongated along the longer side of the rectangular shaped substrate, a plurality of output terminals formed on the rectangular shaped substrate, the output terminal being disposed along the power supply line, a plurality of bump electrodes, each of which connects one of the output terminal to one of the lead lines, switches disposed along the power supply line, each of which is connected between the one of the output terminals and the power supply line, a single power supply terminal, which is disposed near the middle of the power supply line, being connected to the power supply line. | 02-25-2016 |
20160055785 | DISPLAY DEVICE AND TRANSMISSION PROCESSING METHOD FOR IMAGE DATA SIGNAL - A transmission image data signal including: a coded data block obtained by performing an error correction coding on a sequence of pixel data pieces in input image data; and a representative pixel data pieces group containing three pixel data pieces corresponding to red, green, and blue, respectively, in the sequence of the pixel data pieces is transmitted to a driver in a display panel. The driver converts the sequence of the pixel data pieces obtained by performing an error correction on the transmission image data signal to pixel driving voltages and applies these voltages to the display panel. If pixels for one horizontal scanning line have an identical color, the driver performs no error correction. Instead, the driver converts the representative pixel data pieces group to pixel driving voltages and applies these voltages to the display panel. | 02-25-2016 |
20160054924 | MEMORY CONTROL DEVICE AND MEMORY CONTROL METHOD - A memory device is operative to reset write-in status or read-out status information data in accordance with a reset signal. In response to the reset signal, a memory control device refers to a power-on reset check region in a RAM and determines whether or not the received reset signal is a power-on reset signal that is the reset signal generated firstly after power on. If the reset signal is determined to be the power-on reset signal, a memory check process is executed on respective target pages in each block in the memory. A refresh process is also performed on a block in which the number of error bits detected in the memory check process is more than a threshold value. The memory check process is performed on a different page whenever power is supplied. | 02-25-2016 |
20160049944 | SEMICONDUCTOR DEVICE, MEASUREMENT DEVICE, AND CORRECTION METHOD - A semiconductor device includes an oscillator that oscillates at a specific frequency, a semiconductor integrated circuit that integrates a temperature sensor that detects a peripheral temperature, and a controller that is electrically connected to the oscillator and that corrects temperature dependent error in the oscillation frequency of the oscillator based on the temperature detected by the temperature sensor and a sealing member that integrally seals the oscillator and the semiconductor integrated circuit. | 02-18-2016 |
20160049943 | SEMICONDUCTOR DEVICE AND METERING APPARATUS - A semiconductor device includes: an oscillator; a semiconductor chip that includes an oscillation circuit connected to the oscillator, a timer circuit that generates a timing signal of a frequency according to a oscillation frequency of the oscillation circuit, and a frequency correction section that corrects a frequency of the timing signal based on temperature data; and a discrete device that includes at least one of a temperature sensing device that detects a peripheral temperature, that supplies the detected temperature as temperature data to the frequency correction section, and that is provided as a separate body to the semiconductor chip, or a capacitor that is electrically connected to both the oscillator and the oscillation circuit and that is provided as a separate body to the semiconductor chip, wherein the oscillator, the semiconductor chip and the discrete device are contained within a single package. | 02-18-2016 |
20160048195 | ELECTRIC POWER SUPPLY SYSTEM - A master device supplies a power supply voltage through a power transmission line to a slave device that generates an operation signal indicating the contents of an operation received by an operation unit. The slave device includes an operation execution switch that is turned on to apply a reference voltage to the power transmission line, upon reception of the operation by the operation unit. The master device determines whether or not a current accompanying a pilot signal is flowing through the power transmission line, while intermittently sending the pilot signal to the power transmission line in the state of stopping the supplying of the power supply voltage to the slave device. If it is determined that the current is flowing, the master device supplies the power supply voltage to the slave device. | 02-18-2016 |
20160027400 | DISPLAY PANEL - A driver IC has a rectangular shape, and includes a first input terminal group in which first input terminals are disposed at intervals along a first long side, that is opposite a side that faces a display section, from a first short side. A second input terminal group is provided in which second input terminals are disposed at intervals along a second long side that faces the display section, from the first short side. An output terminal group is provided in which output terminals that output signals to the display section are disposed at intervals along the second long side from a position, which is spaced apart for a predetermined distance from where the second input terminals are disposed, to a second short side. A terminal group is not provided at positions that oppose the output terminal group at the first long side. | 01-28-2016 |
20160020185 | SEMICONDUCTOR DEVICE - A semiconductor device comprises: a pad group including a plurality of pads provided on a semiconductor substrate and arranged in a row to form a pad row as a whole. The pad group includes: at least one first pad provided with a first via-connection part electrically connected therewith and extended in a first direction perpendicular to a row direction of the pad row; and at least one second pad provided with a second via-connection part electrically connected therewith and extended in a second direction opposite to the first direction. The at least one second pad is formed at a position moved in the first direction from the row direction of the pad row passing through a center of the at least one first pad. | 01-21-2016 |
20150339989 | DISPLAY PANEL DRIVE DEVICE AND DISPLAY PANEL DRIVE METHOD - A plurality of video data pieces corresponding to one horizontal scan line of a display panel are classified into a first video data group and a second video data group different from the first video data group. Each piece of video data belonging to the first video data group is converted into a gradation voltage having an analog voltage value, and by interpolation based on each of the gradation voltages, a gradation voltage corresponding to each of the video data pieces belonging to said second video data group is obtained. | 11-26-2015 |
20150301653 | SEMICONDUCTOR DEVICE, DISPLAY SYSTEM, DETECTION METHOD, AND NON-TRANSITORY COMPUTER READABLE MEDIUM - The present invention provides a semiconductor device including: a detection section that acquires an output signal, which has an amplitude and is output from an analog-to-digital converter that converts a detection signal output from a capacitance type touch panel into a digital signal, that compares the output signal with a reference signal, and that, in a case in which a variation amount of the output signal with respect to the reference signal exceeds a first threshold value, detects whether a touching state of the touch panel is touched or not based on a time variation of the output signal. | 10-22-2015 |
20150287388 | SOURCE DRIVER IC CHIP - A source driver IC chip, designed to prevent flicker in images displayed on a display panel while suppressing power consumption and heat generation, includes: a reference gradation voltage generating part ( | 10-08-2015 |
20150255392 | RESISTANCE STRUCTURE, INTEGRATED CIRCUIT, AND METHOD OF FABRICATING RESISTANCE STRUCTURE - A resistance structure including: a conductive layer provided at a surface layer portion of a semiconductor substrate; a first resistance element having long sides and short sides provided over the conductive layer with an insulating film interposed; a second resistance element having long sides and short sides provided over the conductive layer with the insulating film interposed and disposed such that one long side thereof opposes one long side of the first resistance element; first wiring that is connected to one end of the first resistance element; second wiring that is connected to one end of the second resistance element; third wiring that connects the other end of the first resistance element with the other end of the second resistance element; and a connection portion that connects any of the first wiring, the second wiring and the third wiring with the conductive layer. | 09-10-2015 |
20150255035 | DRIVING DEVICE FOR DISPLAY DEVICE - A driving device for a display device wherein the display device and a source driver are connected by a plurality of external lines. A bias voltage generating part generates a bias voltage for controlling internal operating current of the plurality of amplifiers in the source driver to supply to each amplifier via a bias voltage supply line. The bias voltage supply line is laid out such that for the amplifier connected to the external line of a longer length, the length of the bias voltage supply line from the bias voltage generating part to the amplifier is shorter so as to raise a bias voltage supplied to the amplifier. | 09-10-2015 |
20150221276 | DISPLAY DEVICE DRIVER - A display device driver that can display images while preventing noise and suppressing display unevenness is provided. When pixel drive voltages corresponding to the luminance levels of respective pixels indicated by a video signal are applied to the data lines of the display device, the pixel drive voltages are applied to data lines that intersect the scanning lines of the display device at positions where the delay time is larger, at timing later than timing of applying the pixel drive voltages to the data lines that intersect the scanning lines at positions where the delay time is smaller, the delay time being a period of time between start of application of the scanning pulse by the scanning driver and actual arrival of the scanning pulse. | 08-06-2015 |
20150221274 | DISPLAY DRIVER - First to N-th latches capture N pieces of pixel data indicative of the luminance levels of respective pixels in synchronization with first to N-th capture clock signals each having different edge timing. Voltages corresponding to the pieces of pixel data output from the first to N-th latches are applied to each of the data lines of the display device. In this case, first to N-th flip-flops formed in an N-stage shift register capture a single pulse load signal which is synchronized with a horizontal synchronizing signal in a video signal while sequentially shifting the load signal to subsequent stages in synchronization with a reference timing signal supplied from the outside. Outputs of the first to N-th flip-flops in the N-stage shift register are supplied as first to N-th capture clock signals, to the first to N-th latches, respectively. | 08-06-2015 |
20150188429 | POWER-SUPPLY DEVICE, METHOD FOR CONTROLLING THE SAME, AND COMMUNICATION DEVICE INCLUDING THE SAME - Upon sending out a first power-supply voltage having a first value to first and second power supply lines in a first mode and sending out a second power-supply voltage having a second value lower than the first value to the second power supply line in a second mode, when switching a power-supply device from the first mode to the second mode, the value of the first power-supply voltage generated in a first power-supply circuit is changed to the second value first, the first and second power supply lines are temporarily connected together and then cut off from each other, and then the generating operation of the first power-supply voltage is stopped. | 07-02-2015 |
20150179417 | PLASMA MONITORING METHOD AND PLASMA MONITORING SYSTEM - A plasma monitoring method using a sensor, the sensor having a substrate; a first electrode, the first electrode being a conductive electrode and formed on the substrate while being isolated from the substrate; an insulating film formed on the first electrode; a contact hole formed in the insulating film and having a depth from a surface of the insulating film to the first electrode; and a second electrode, the second electrode being a conductive electrode, formed on the surface of the insulating film, and faced to plasma during a plasma process, the plasma monitoring method including measuring and monitoring potentials of the first electrode and the second electrode or a potential difference between the first electrode and the second electrode during the plasma process is disclosed. A plasma monitoring system carrying out the plasma monitoring method is also disclosed. | 06-25-2015 |
20150138261 | DRIVING DEVICE FOR DRIVING DISPLAY UNIT - A driving device for driving a display unit which can reduce power consumption regardless of the type of video data is provided which, based on the type of application software which is the provider of a video data signal, performs either one of a first power saving mode in which to stop power delivery to a data driver and a second power saving mode in which the data driver stops importing of the pixel data sequence signal when the 1-H line data's respectively corresponding to neighboring ones of horizontal scan lines of the display unit coincide with each other. | 05-21-2015 |
20150138259 | DRIVING DEVICE FOR DRIVING DISPLAY UNIT - A device and method for controlling a semiconductor memory capable of suppressing deterioration in reliability of read-out data are provided. A drive controller generates pixel data sequence signals which indicate luminance levels of respective pixels based on a video data signal. A data driver generates pixel drive voltages corresponding to the luminance levels of the respective pixels on the basis of the pixel data sequence signals, and supplies the pixel drive voltages to data lines of the display unit. When the video data signal of one frame matches or substantially coincides with the video data signal of another frame which is directly succeeding to the particular one frame in time sequence, supply of the pixel data sequence signals to the data driver is stopped. | 05-21-2015 |
20150138254 | DRIVING DEVICE FOR DRIVING A DISPLAY UNIT - Disclosed is a display unit driving device which has a reduced power consumption rate. The display unit displays an image in response to a video data signal which is constituted by a plurality of frames each including a data scanning period and a blanking period. The driving device stops power supply to a data driver for a predetermined power stop period within the blanking period. The data driver applies pixel drive voltages respectively corresponding to luminance levels of each pixel based on the video data signal to multiple data lines of the display device in each horizontal scanning cycle within the data scanning period. | 05-21-2015 |
20150130399 | CHARGING CONTROL SYSTEM AND DEVICE - A charging control system for charging a secondary battery from a solar battery, including a first path for transmitting power from the solar battery to the secondary battery, a second path for sensing the voltage of the secondary battery, and a comparison unit for comparing the solar battery voltage with the sensed voltage of the secondary battery. The first path includes a first interrupter, controlled by the comparison unit, which interrupts the first path to prevent discharge of the secondary battery through the solar battery when the solar battery voltage falls below the secondary battery voltage. The second path includes a second interrupter that interrupts the second path after the first path is interrupted, to prevent the secondary battery from discharging through the second path when not being charged through the first path. | 05-14-2015 |
20150108612 | METHOD FOR THINNING, METALIZING, AND DICING A SEMICONDUCTOR WAFER, AND SEMICONDUCTOR DEVICE MADE USING THE METHOD - There is provided a method of fabricating a semiconductor device, method including: a) forming semiconductor elements in plural element regions surrounded by assumed dicing lines on a first principal surface of a semiconductor wafer; b) grinding the second principal surface in such a way that an outer peripheral portion of a second principal surface on the opposite side of the first principal surface of the semiconductor wafer becomes thicker than an inner peripheral portion of the second principal surface; c) forming a metal film, in such a way as to avoid sections corresponding to the dicing lines, on the second principal surface that has been ground in the grinding step; and d) cutting the semiconductor wafer from the second principal surface side along portions where the metal film is not formed on the dicing lines. | 04-23-2015 |
20150106049 | MOTION DETECTION DEVICE, ELECTRONIC DEVICE, MOTION DETECTION METHOD, AND PROGRAM STORAGE MEDIUM - A motion detection device includes: an acceleration detection unit, a separating unit, a gravity axis determination unit, and a motion detection unit. The acceleration detection unit detects acceleration components of each axis of a three-dimensional rectangular coordinate system of acceleration acting on the acceleration detection unit and outputs sets of acceleration component data. The separating unit separates the outputted sets of acceleration component data into stationary components and motion components. The gravity axis determination unit determines an axis whose separated stationary component is the largest to be a gravity axis. The motion detection unit detects, if an axis corresponding to a largest motion component showing a largest value of the separated motion components is an axis other than the determined gravity axis, a motion axis of the acceleration detection unit on the basis of the largest motion component. | 04-16-2015 |
20150092492 | SEMICONDUCTOR DEVICE AND METHOD OF SEARCHING FOR ERASURE COUNT IN SEMICONDUCTOR MEMORY - In response to a search start instruction, a read address signal including address sequences for blocks is generated and the read address signal is provided to a block management memory to successively read sequences of erasure count data pieces corresponding to the blocks from the block management memory. Thereafter, when the erasure count data piece read from the block management memory represents an erasure count smaller than a minimum erasure count data piece, the erasure count data piece is imported and retained and outputted as the minimum erasure count data piece. Also, the read address signal is imported and retained and an address indicated by the read address signal is outputted as a minimum erasure count address. | 04-02-2015 |
20150091102 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - Disclosed is a semiconductor device manufacturing method comprising: forming an element isolation region in one principal face of a semiconductor substrate of one conductivity type; forming a gate electrode extending from an element region to the element isolation region at both sides of the element region in a first direction, both end portions of the gate electrode in the first direction being on the element isolation region and respectively including a concave portion and protruding portions at both sides of the concave portion; carrying out ion implantation of impurities of the one conductivity type from a direction tilted from a direction perpendicular to the one principal face toward the first direction so that first and second impurity implantation regions of the one conductivity type are formed in the one principal face in two end regions of the element region in the first direction. | 04-02-2015 |
20150085913 | DATA RECEIVING CIRCUIT AND SEMICONDUCTOR DEVICE - A data receiving circuit that can accurately obtain a data signal corresponding to information data from a high speed high density transmitted signal, and a semiconductor device including the data receiving circuit. The amplitude of a first differential signal corresponding to a level difference between a pair of received differential signals, generated in a first differential stage, is amplified and binalized to obtain a received data signal. A second differential signal corresponding to the level difference between the received differential signals, and a third differential signal which is a phase-inverted signal of the second differential signal are generated in a second differential stage provided separately, and a current corresponding to the second differential signal and a current corresponding to the third differential signal are discharged into the respective ones of the pair of transmission lines, thereby suppressing the amplitudes of the received differential signals. | 03-26-2015 |
20150070083 | BOOSTING CIRCUIT OF CHARGE PUMP TYPE AND BOOSTING METHOD - A boosting circuit of charge pump type includes: charging portion for applying an input voltage to a first capacitor; double boosting portion for applying the input voltage to a second capacitor and applying a sum of the input voltage and a voltage across the first capacitor to an output capacitor in a first predetermined period after start of a boosting operation; and triple boosting portion for repeating in order, after end of the first predetermined period, a step of applying the sum of the input voltage and the voltage across the first capacitor to the second capacitor and a step of applying a sum of the voltage across the first capacitor and a voltage across the second capacitor to the output capacitor. | 03-12-2015 |
20150022794 | SEMICONDUCTOR DEVICE MANUFACTURING METHOD AND SEMICONDUCTOR DEVICE MANUFACTURING APPARATUS - A method of manufacturing a semiconductor device includes: preparing a wafer member, the wafer member including a wafer, a conductive layer formed on a surface of the wafer and a negative photoresist formed on the conductive layer; applying a light blocking material so as to cover at least a part of an outer edge of the wafer member from an upper surface of the negative photoresist to a side surface of the negative photoresist; exposing the negative photoresist to exposure light; removing the light blocking material; and developing the negative photoresist. | 01-22-2015 |
20150008985 | OSCILLATOR AND PHASE-LOCKED LOOP CIRCUIT - An oscillator comprising: an oscillator circuit element having a substrate terminal group and a capacitance section provided on an element substrate, the substrate terminal group comprising at least three substrate terminals including a first substrate terminal and a second substrate terminal, the capacitance section being connected between the first and second substrate terminals; a mount part including an external terminal group comprised of at least one external terminal and mounting thereon the oscillator circuit element; a plurality of inductance lines which are formed among the at least three substrate terminals by conductor wirings which connect between the at least three substrate terminals of the substrate terminal group and the at least one external terminal; and a switch circuit provided on the element substrate to control a connection state of the plurality of inductance lines. | 01-08-2015 |
20140368226 | SEMICONDUCTOR DEVICE AND TEST METHOD - A test voltage having a first voltage or a second voltage is applied to an output terminal of a complementary fuse that includes a first fuse to one end of which the first voltage is applied and the other end of which serves as the output terminal and a second fuse to one end of which the second voltage is applied and the other end of which is connected to the output terminal. The test voltage then stops being applied. In such a state, whether output data from the output terminal of the complementary fuse coincides with an expected value is determined. The result of determination is output as a test result. | 12-18-2014 |
20140328440 | FILTER CIRCUIT AND RECEIVING APPARATUS - A receiving apparatus that includes a first and second filter circuit. The first filter performs filtering on a frequency signal with a band-pass characteristic such that a frequency band of a desired channel is included in a passband, thereby obtaining a pass frequency signal. The second filter performs filtering on the pass frequency signal with a filter characteristic such that a frequency band of a channel adjoining the desired channel is included in an attenuation band. | 11-06-2014 |
20140312870 | BOOST-TYPE SWITCHING REGULATOR AND SEMICONDUCTOR DEVICE FOR BOOST-TYPE SWITCHING REGULATOR - A boost-type switching regulator includes an inductor; a rectifying element; a capacitor; a switching element; an output terminal; a detection voltage generating unit; an output voltage controlling unit; and a detection voltage level shifting unit. The detection voltage generating unit generates a detection voltage according to an output voltage. The output voltage controlling unit turns on and off the switching element to increase the output voltage when the detection voltage is smaller than a specific value, and to turn off the switching element to decrease the output voltage when the detection voltage is greater than the specific value. The detection voltage level shifting unit shifts the detection voltage so that the detection voltage during a voltage increasing period becomes greater than the detection voltage during a voltage decreasing period. | 10-23-2014 |
20140306321 | SEMICONDUCTOR DEVICE FABRICATION METHOD AND SEMICONDUCTOR DEVICE - There is provided a method of fabricating a semiconductor device, the method including: forming a semiconductor component portion at a first surface of a substrate; applying a grinding treatment to a second surface of the substrate that is opposite from the first surface to form a fracture surface; applying a fracture surface removal treatment to predetermined positions of the fracture surface of the second surface; and forming an electrode at the second surface. | 10-16-2014 |
20140286472 | SEMICONDUCTOR DEVICE AND MEASUREMENT METHOD - The present invention provides a semiconductor device and a measurement method that enables high precision measurement of temperature or humidity or the like over a wide range. A semiconductor device of the present invention determines which is faster out of a reference oscillation and a thermistor oscillation, and using the faster oscillation as a reference, measures a count value based on the other oscillation. Moreover, the count based on the faster oscillation is employed as a reference value, and a count value based on the other oscillation when the reference value is taken as a measurement value. A frequency ratio is computed based on the reference value and the measurement value, and based on the computed frequency ratio, a table expressing correspondence relationships between frequency ratio and temperature is referred to and a temperature acquired. | 09-25-2014 |
20140232321 | CHARGING CONTROL SYSTEM AND DEVICE - A charging control system for charging a secondary battery from a solar battery, including a first path for transmitting power from the solar battery to the secondary battery, a second path for sensing the voltage of the secondary battery, and a comparison unit for comparing the solar battery voltage with the sensed voltage of the secondary battery. The first path includes a first interrupter, controlled by the comparison unit, which interrupts the first path to prevent discharge of the secondary battery through the solar battery when the solar battery voltage falls below the secondary battery voltage. The second path includes a second interrupter that interrupts the second path after the first path is interrupted, to prevent the secondary battery from discharging through the second path when not being charged through the first path. | 08-21-2014 |
20140231947 | SEMICONDUCTOR MODULE - A semiconductor module including a semiconductor chip having a light receiving device formed at a front thereof and light permeable cover having a front, a back, and a side. The light permeable cover is disposed opposite to the front of the semiconductor chip such that the front of the semiconductor chip is covered by the back of the light permeable cover. The permeable cover is provided at the outer circumferential region of the front thereof and at the side thereof with a light shielding layer. It is possible to prevent the incidence of unnecessary light from the side of the light permeable cover of a CSP and to easily adjust the distance between a lens and the front of the semiconductor chip within tolerance. | 08-21-2014 |
20140205865 | BATTERY MONITORING SYSTEM, SEMICONDUCTOR DEVICE, BATTERY ASSEMBLY SYSTEM, BATTERY MONITORING IC - Provides a battery monitoring system including a battery cell number setting section that sets each LSI with the respectively individual number of battery cells C to which they are connected. When a command to sequentially measure the battery voltage of the battery cells is input, a cell selection control section compares the setting value with the commanded measurement start battery cell number. When the setting value is equal to or greater, performs measurement in sequence starting from the battery cell corresponding to the measurement start battery cell number. When the setting value is less, measurement is performed in sequence starting from the battery cell corresponding to the setting value. In a boost control section, during when the battery voltages with 3 higher potential battery cells is measured, a power source voltage is boosted by a charge pump and is supplied to first and second buffer amplifier. | 07-24-2014 |
20140191765 | BATTERY MONITORING SYSTEM AND BATTERY MONITORING DEVICE - A battery monitoring system includes: plural battery monitoring devices that are serially connected to each other; and a control circuit connected to one battery monitoring device and that transmits a first activation signal to the one battery monitoring device, wherein each particular one of the plural battery monitoring devices includes: a constant voltage generation circuit that generates and outputs a constant voltage; a first activation circuit that outputs a second activation signal if the first activation circuit receives the first activation signal; and a second activation circuit that outputs a third activation signal in response to recognizing the constant voltage generated by the constant voltage generation of another of the battery monitoring devices that is connected to the particular battery monitoring device, and wherein the constant voltage generation circuit generates the constant voltage if the constant voltage generation circuit receives the second activation signal or the third activation signal. | 07-10-2014 |
20140189033 | COMMUNICATION SYSTEM, SEMICONDUCTOR DEVICE, AND DATA COMMUNICATION METHOD - System and method of data communication and a semiconductor device capable of transmitting information data through a communication interface with a specified response duration without degradation in efficiency of operation. In a first information processing unit, when a first controller issues request signals of predetermined data processing, a first communication interface sends a pseudo response to the first controller in response to one of the request signals and transmits the request signal to a second information processing unit which in turn performs predetermined information processing indicated by the request signal and sends back response data. The first communication interface stores the received response data in memory and reads the response data from memory in response to a request signal issued for the second time onward from the first controller after complete storing of the response data, and then supplies the data to the first controller. | 07-03-2014 |
20140188381 | SEMICONDUCTOR DEVICE, ELECTRICAL DEVICE, AND METHOD OF CONTROLLING POWER SOURCE - A semiconductor device includes an atmospheric pressure value obtaining unit configured to obtain an atmospheric pressure value from an atmospheric pressure sensor; and a control unit configured to detect a variance state of the atmospheric pressure value obtained with the atmospheric pressure value obtaining unit. The control unit is further configured to control an on state and an off state of a power source of a GPS (Global Positioning System) device according to a determination whether the variance state satisfies a specific condition. The GPS device is configured to detect a position thereof based on a GPS signal received therewith and output positional information. | 07-03-2014 |
20140185694 | SIGNAL RECEIVING DEVICE, SEMICONDUCTOR DEVICE, AND SIGNAL RECEIVING METHOD - A signal receiving device obtains information data based on a plurality of signals received at a plurality of antennas. The signal receiving device is divided into a first receiving unit and a second receiving unit. The first receiving unit carries out certain part of an entire receiving process, and the second receiving unit carries out the remaining part of the receiving process. The first receiving unit demodulates and synthesizes the received signals and decodes the synthesized signal to recover received information data. The first receiving unit modulates the received information data to obtain a modulation signal and transmits the modulation signal to the second receiving unit via a transmission cable. The second receiving unit recovers the received information data by demodulating the modulation signal received via the transmission cable, and obtains the information data by decoding the recovered information data. | 07-03-2014 |
20140176522 | DISPLAY DRIVE CIRCUIT - A display drive circuit formed in a chip manufactured by a chip on glass implementation, which is connected to lead lines formed on a glass substrate, includes a rectangularly-shaped substrate, a power supply line formed on the substrate, the line being elongated along the longer side of the rectangular shaped substrate, a plurality of output terminals formed on the rectangular shaped substrate, the output terminal being disposed along the power supply line, a plurality of bump electrodes, each of which connects one of the output terminal to one of the lead lines, switches disposed along the power supply line, each of which is connected between the one of the output terminals and the power supply line, a single power supply terminal, which is disposed near the middle of the power supply line, being connected to the power supply line. | 06-26-2014 |
20140175620 | SEMICONDUCTOR DEVICE FABRICATION METHOD AND SEMICONDUCTOR DEVICE - There is provided a method of fabricating a semiconductor device, the method including: forming a first semiconductor region at a front surface of a substrate, the first semiconductor region including an active element that regulates current flowing in a thickness direction of the substrate; grinding a rear surface of the substrate; after the grinding, performing a first etching that etches the rear surface of the substrate with a chemical solution including phosphorus; after the first etching, performing a second etching that etches the rear surface with an etching method with a lower etching rate than the first etching; and after the second etching, forming a second semiconductor region through which the current is to flow, by implanting impurities from the rear surface of the substrate. | 06-26-2014 |
20140167277 | SEMICONDUCTOR WIRING PATTERNS - A semiconductor device includes a rectangular semiconductor element mounted on a substrate formed with an external input terminal, an external output terminal, and a plurality of wiring patterns connected to each of the external input terminal and the external output terminal. The semiconductor element includes, a plurality of first electrodes formed along a first edge of a surface thereof, a plurality of second electrodes formed along an edge opposite to the first edge of the surface, a plurality of third electrodes formed in the neighborhood of a functional block, and an internal wiring for connecting the first electrodes and the third electrodes. The substrate includes, a first wiring pattern for connecting the external input terminal and the first electrodes, a second wiring pattern for connecting the external output terminal and the second electrodes, and a third wiring pattern for connecting the first electrodes and the third electrodes. | 06-19-2014 |
20140146617 | NONVOLATILE SEMICONDUCTOR MEMORY - A nonvolatile semiconductor memory can reduce variations in an amount of current during data writing operation. This allows for the writing of data to memory cells with high precision. The nonvolatile semiconductor memory includes a plurality of memory cells, word lines connected to the memory cells, and bit lines connected to each of the memory cells. At least two of the bit lines are selected, and a current is simultaneously supplied from a power supply line to those memory cells which are connected to the selected bit lines in order to write data thereto. The nonvolatile semiconductor memory also includes charge amount measurement units for measuring respective amounts of charge stored in the memory cells. The nonvolatile semiconductor memory also includes current path switching circuits connected to the respective bit lines. Those current path switching circuits which are connected to the selected bit lines supply a current from the power supply line to the memory cells or a predetermined terminal depending on a measured value of the amount of charge measured by the charge amount measurement section. | 05-29-2014 |
20140131891 | SEMICONDUCTOR DEVICE AND PROCESS FOR FABRICATING THE SAME - A thin stacked semiconductor device has a plurality of circuits that are laminated and formed sequentially in a specified pattern to form a multilayer wiring part. At the stage for forming the multilayer wiring part, a filling electrode is formed on the semiconductor substrate such that the surface is covered with an insulating film, a post electrode is formed on specified wiring at the multilayer wiring part, a first insulating layer is formed on one surface of the semiconductor substrate, the surface of the first insulating layer is removed by a specified thickness to expose the post electrode, and the other surface of the semiconductor substrate is ground to expose the filling electrode and to form a through-type electrode. A second insulating layer if formed on one surface of the semiconductor substrate while exposing the forward end of the through-type electrode, and bump electrodes are formed on both electrodes. | 05-15-2014 |
20140118418 | DISPLAY PANEL DRIVER AND DRIVING METHOD THEREOF - A display panel driver that can take in pixel data without wasteful electric power consumption even if the number of output terminals of the display panel driver is greater than the number of source lines of the display panel, and a driving method thereof. The display panel driver has latches individually, respectively hold pixel data pieces, each of which is for a pixel, based on an input video signal according to information stored in a setting register and applies drive pulses corresponding to the pixel data pieces held in the latches to the source lines of the display panel. | 05-01-2014 |
20140118371 | DISPLAY PANEL DRIVER SETTING METHOD, DISPLAY PANEL DRIVER, AND DISPLAY APPARATUS INCLUDING THE SAME - When a plurality of display panel drivers is set to a state in conformity to given specifications, setting data indicative of details of the setting is stored in a memory. One of the display panel drivers supplies a first signal indicating that the setting data is in a readout condition to the memory and other display panel drivers. In response to the first signal, the memory reads and provides the setting data on the first line. The one display panel driver fetches the setting data on the first line to perform the setting based on the setting data. The other display panel drivers fetch the setting data from the first line in response to the first signal to perform the setting based on the setting data. | 05-01-2014 |
20140118040 | SYNCHRONIZING CIRCUIT AND CLOCK DATA RECOVERY CIRCUIT INCLUDING THE SAME - A synchronizing circuit that is capable of generating a reproduced clock signal synchronized with a reference clock signal without causing a false lock and a clock data recovery circuit including the same are provided. To generate a clock signal synchronized with a reference clock signal associated with a data transition point that appears every predetermined period in an input data signal, the following false-lock avoidance processing is performed. That is, precharging of a first line is started when a phase control voltage applied to the first line by a charge pump falls below a lower-limit reference voltage, and the precharging of the first line is continued until the phase control voltage exceeds an upper-limit reference voltage. | 05-01-2014 |
20140111182 | REFERENCE VOLTAGE GENERATION CIRCUIT - A reference voltage generation circuit includes a standard electrical current path including at least a pair of NMOS and PMOS, and a constant electrical current supplying circuit for supplying a constant electrical current to the standard electrical current path. The pair of NMOS and PMOS is configured to share a gate potential and a source-drain electrical current. Accordingly, the reference voltage generation circuit is configured to generate a reference voltage as a potential difference between two positions sandwiching the NMOS and PMOS. The reference voltage generation circuit further includes a timing compensation circuit. The timing compensation circuit includes a compensation DMOS for forming a detour electrical current path for bypassing the NMOS according to an on signal. | 04-24-2014 |
20140110807 | CAMERA MODULE - A camera module has a sensor chip including a sensor unit formed on a main surface around which sides are disposed. A lens chip is fixed to the sensor chip with a spacer unit and includes a lens unit corresponding to the sensor unit. A light shieldable layer covers a first side of the sensor chip and a side of the spacer unit. A first cutting surface includes a second side of the sensor chip and a side of the light shieldable layer on a same plane. | 04-24-2014 |
20140097872 | VOLTAGE CHANGE DETECTION DEVICE - A voltage change detection device, which reduces a deviation of a detection potential and detects a voltage change within a predetermined detection potential even when the threshold voltage of a field effect transistor is deviated. The voltage change detection device includes a first field effect transistor, a second field effect transistor, and a detection signal generator. The first field effect transistor has a drain connected to a power supply potential, a source connected to a first constant current source or a first resistor at a first node, and a gate connected to a fixed voltage. The second field effect transistor has a drain and a gate connected to the power supply potential and a source connected to a second constant current source or a second resistor at a second node. The detection signal generator generates a detection signal indicating that the power supply potential has crossed a predetermined detection potential. | 04-10-2014 |
20140091779 | SEMICONDUCTOR DEVICE - A semiconductor device includes a reference voltage generation circuit to which a power source voltage is applied; an output terminal for outputting an output voltage; a determining circuit connected to the reference voltage generation circuit and the output terminal for generating the output voltage according to a determination target voltage; and a constant electric current source connected to the determining circuit and a ground potential for generating a constant electrical current. | 04-03-2014 |
20140085349 | SOURCE DRIVER IC CHIP - A source driver IC chip, designed to prevent flicker in images displayed on a display panel while suppressing power consumption and heat generation, includes: a reference gradation voltage generating part ( | 03-27-2014 |
20140082952 | DETERMINATION DEVICE, ELECTRICAL DEVICE, AND METHOD OF DETERMINING MOVING STATE - A determination device includes a geomagnetism value obtaining unit for obtaining a geomagnetism value detected with a geomagnetism sensor; and a geomagnetism value determining unit for determining whether a user having the geomagnetism sensor is in a moving state in an automobile or on a train according to a magnitude of a change in the geomagnetism value obtained with the geomagnetism value obtaining unit. | 03-27-2014 |
20140077888 | SEMICONDUCTOR DEVICE AND METERING APPARATUS - A semiconductor device. The semiconductor device includes: an oscillator; a semiconductor chip that includes an oscillation circuit connected to the oscillator, a timer circuit that generates a timing signal of a frequency according to a oscillation frequency of the oscillation circuit, and a frequency correction section that corrects a frequency of the timing signal based on temperature data; and a discrete device that includes at least one of a temperature sensing device that detects a peripheral temperature, that supplies the detected temperature as temperature data to the frequency correction section, and that is provided as a separate body to the semiconductor chip, or a capacitor that is electrically connected to both the oscillator and the oscillation circuit and that is provided as a separate body to the semiconductor chip, wherein the oscillator, the semiconductor chip and the discrete device are contained within a single package. | 03-20-2014 |
20140073129 | SEMICONDUCTOR DEVICE INCLUDING BOTTOM SURFACE WIRING AND MANUFACTURING METHOD OF THE SEMICONDUCTOR DEVICE - Disclosed herein is a semiconductor device including a semiconductor substrate, a wiring layer formed above the semiconductor substrate, a through-hole electrode extending from the bottom surface of the semiconductor substrate to the wiring layer, a bottom surface wiring provided, at the bottom surface of the semiconductor substrate such that the bottom surface wiring is connected to the through-hole electrode, and an external terminal connected to the bottom surface wiring. The bottom surface wiring has a greater film thickness than a film thickness of the through-hole electrode at least a portion of the bottom surface wiring including a connection part between the bottom surface wiring and the external terminal. | 03-13-2014 |
20140070374 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING SEMICONDUCTOR DEVICE - There is provided a method of fabricating a semiconductor device, method including: a) forming semiconductor elements in plural element regions surrounded by assumed dicing lines on a first principal surface of a semiconductor wafer; b) grinding the second principal surface in such a way that an outer peripheral portion of a second principal surface on the opposite side of the first principal surface of the semiconductor wafer becomes thicker than an inner peripheral portion of the second principal surface; c) forming a metal film, in such a way as to avoid sections corresponding to the dicing lines, on the second principal surface that has been ground in the grinding step; and d) cutting the semiconductor wafer from the second principal surface side along portions where the metal film is not formed on the dicing lines. | 03-13-2014 |
20140068108 | ELECTRICAL DEVICE AND METHOD OF SETTING ADDRESS - An electrical device includes a plurality of apparatus connected with a daisy chain connection through a communication line so that the apparatus communicate with each other through the communication line; and a control unit connected to one of the apparatus at an end stage thereof so that the control unit is configured to communicate with the one of the apparatus. The apparatus includes an address setting unit for setting a specific number to an address of the apparatus according to an address setting command when the apparatus receives address setting data including an address addition instruction as the address setting command for adding the specific number to the address of the apparatus. The apparatus further includes an address setting data transmission control unit for outputting the address setting data to a later stage apparatus when the address setting unit sets the specific value to the address of the apparatus. | 03-06-2014 |
20140061804 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - Provided is a semiconductor device including active regions formed in a semiconductor substrate and arranged in a first direction parallel to a surface of the semiconductor substrate; a first element isolating region formed in the semiconductor substrate and electrically isolating adjacent active regions from each other; and gate electrodes extending over the active regions respectively and arranged in the first direction. The first element isolating region includes a first region extending in a second direction orthogonal to the first direction and a second region extending in a direction intersecting the first region, one gate electrode of adjacent gate electrodes has a first edge side which includes a first overlap part placed on the second region, and another gate electrode of the adjacent gate electrodes has a second edge side which faces the first edge side and includes a second overlap part placed on the second region. | 03-06-2014 |
20140055185 | INTEGRATED CIRCUIT HAVING LATCH CIRCUITS AND USING DELAY CIRCUITS TO FETCH DATA BITS IN SYNCHRONIZATION WITH CLOCK SIGNALS - A semiconductor integrated circuit includes a delay circuit connected between a source of data bits and a data input terminal of a latch circuit. The delay circuit includes a first delay section formed by connecting logic devices in series corresponding to a number of logic devices included in a clock signal path between a clock signal source and the latch circuit data input. The delay circuit also includes a second delay section having a delay time equal to an interconnect delay time corresponding to a wiring length of the clock signal path. | 02-27-2014 |
20140054746 | RESISTANCE STRUCTURE, INTEGRATED CIRCUIT, AND METHOD OF FABRICATING RESISTANCE STRUCTURE - A resistance structure including: a conductive layer provided at a surface layer portion of a semiconductor substrate; a first resistance element having long sides and short sides provided over the conductive layer with an insulating film interposed; a second resistance element having long sides and short sides provided over the conductive layer with the insulating film interposed and disposed such that one long side thereof opposes one long side of the first resistance element; first wiring that is connected to one end of the first resistance element; second wiring that is connected to one end of the second resistance element; third wiring that connects the other end of the first resistance element with the other end of the second resistance element; and a connection portion that connects any of the first wiring, the second wiring and the third wiring with the conductive layer. | 02-27-2014 |
20140050285 | DATA RECEIVING CIRCUIT AND SEMICONDUCTOR DEVICE - A data receiving circuit that can accurately obtain a data signal corresponding to information data from a high speed high density transmitted signal, and a semiconductor device including the data receiving circuit. The amplitude of a first differential signal corresponding to a level difference between a pair of received differential signals, generated in a first differential stage, is amplified and binalized to obtain a received data signal. A second differential signal corresponding to the level difference between the received differential signals, and a third differential signal which is a phase-inverted signal of the second differential signal are generated in a second differential stage provided separately, and a current corresponding to the second differential signal and a current corresponding to the third differential signal are discharged into the respective ones of the pair of transmission lines, thereby suppressing the amplitudes of the received differential signals. | 02-20-2014 |
20140043221 | DEVICE CIRCUIT AND DISPLAY APPARATUS HAVING OPERATIONAL AMPLIFIERS WITH PARASITIC DIODES - A driving circuit includes a pair of operational amplifiers, one producing an analog voltage output of positive polarity, the other producing an analog voltage output of negative polarity. An output switching circuit interchanges these outputs between a pair of data lines. One or both of the operational amplifiers includes a parasitic diode having one terminal connected to the output terminal of the operational amplifier and another terminal normally connected to a power supply voltage of the operational amplifier. When the output of the operational amplifier is switched, a protective switching circuit temporarily disconnects the parasitic diode from the power supply of the operational amplifier and instead connects it to a power supply line carrying a voltage high enough, or low enough, to ensure that the parasitic diode is not forward biased by the existing voltage on the data line to which the output is switched. | 02-13-2014 |
20140043073 | CLOCK SYNCHRONIZATION CIRCUIT AND SEMICONDUCTOR DEVICE - A clock synchronization circuit is configured to capture an input data bit according to an input clock signal, and to synchronize and output the input data bit. The clock synchronization circuit includes a clock buffer for generating an internal clock signal according to the input clock signal and transmitting the internal clock signal to a clock line. The clock synchronization circuit further includes a D flip-flop for capturing and outputting the input data bit at an edge timing of the internal clock signal. The clock buffer includes an inverter core portion and an electric current suppressing portion. The inverter core portion is configured to generate the internal clock signal through alternately supplying an electric current to the clock line and drawing the electric current from the clock line according to the input clock signal. The electric current suppressing portion is configured to suppress an amount of the electric current. | 02-13-2014 |
20140042942 | SEMICONDUCTOR DEVICE, ELECTRICAL DEVICE AND CONTROL SIGNAL, GENERATION METHOD - The present invention provides a semiconductor device, an electrical device, and a control signal generation method that enable easy generation of a given control signal even by a comparatively low cost and low processing power microcontroller. Namely, a microcontroller of a motor control system includes a PWM device equipped with a PWM setting register. The PWM setting register includes a duty update cycle register, a duty update value register and a duty update-times number register. A PWM generator generates and outputs a PWM signal according to values set in each register of the PWM setting register. The PWM device is capable of generating and outputting a PWM signal automatically with the PWM generator according to setting values set in the PWM setting register, even without an interruption by the software (CPU). | 02-13-2014 |
20140042635 | SEMICONDUCTOR DEVICE - One wiring width of upper and lower wiring paths formed facing each other sandwiching an interlayer insulating film is large, and another wiring width is small; and the wiring widths of mutually adjacent wiring paths are formed to be large and small in alternating fashion on the same wiring layer. | 02-13-2014 |
20140028386 | OUTPUT BUFFER AND SEMICONDUCTOR DEVICE - An output buffer has a first transistor and a voltage mitigation second transistor. The first transistor is configured to generate a voltage value corresponding to the power-supply voltage in response to an input signal. The second transistor is provided between an output line and the first transistor. A gate terminal of the second transistor is applied with a power-supply bias voltage which turns the second transistor on and makes a voltage between gate and source terminals of the second transistor constant in accordance with a power-supply voltage. | 01-30-2014 |
20130313688 | SEMICONDUCTOR DEVICE AND METHOD OF PRODUCING SEMICONDUCTOR DEVICE - A method of producing a semiconductor device includes the step of forming a through hole in a semiconductor substrate. The semiconductor substrate has a first main surface and a second main surface opposite to the first main surface, and includes a first conductive layer formed on the second main surface. The through hole penetrates through the semiconductor substrate from the first main surface to the second main surface, so that the first conductive layer formed on the second main surface is exposed at a bottom portion of the through hole. The method further includes the steps of forming a seed layer on a side surface of the through hole from the bottom portion of the through hole to the first main surface; forming a second conductive layer on the seed layer through a first plating process; and forming a third conductive layer selectively on the second conductive layer. | 11-28-2013 |
20130285640 | SEMICONDUCTOR DEVICE, MEASUREMENT DEVICE, AND CORRECTION METHOD - A semiconductor device includes an oscillator that oscillates at a specific frequency, a semiconductor integrated circuit that integrates a temperature sensor that detects a peripheral temperature, and a controller that is electrically connected to the oscillator and that corrects temperature dependent error in the oscillation frequency of the oscillator based on the temperature detected by the temperature sensor and a sealing member that integrally seals the oscillator and the semiconductor integrated circuit. | 10-31-2013 |
20130285225 | SEMICONDUCTOR DEVICE AND MEASUREMENT DEVICE - A semiconductor device includes: an oscillator including external terminals disposed on a first face with a specific distance along a first direction; an integrated circuit including a first region formed with first electrode pads along one side, and a second region formed with second electrode pads on two opposing sides of the first region; a lead frame that includes terminals at a peripheral portion, and on which the oscillator and the integrated circuit are mounted such that the external terminals, the first and second electrode pads face in a substantially same direction and such that one side of the integrated circuit is substantially parallel to the first direction; a first bonding wire that connects one external terminal to one first electrode pad; a second bonding wire that connects one terminal of one lead frame to one second electrode pad; and a sealing member that seals all of the components. | 10-31-2013 |
20130285224 | SEMICONDUCTOR DEVICE AND MEASUREMENT DEVICE - A semiconductor device includes a lead frame, an oscillator, an integrated circuit and first bonding wires. The oscillator includes plural terminals separated from each other by a predetermined distance, and that is mounted to an oscillator mounting region formed on a first face of the lead frame. The oscillator mounting region has a narrower width than the distance between the plural terminals. The integrated circuit is mounted to a second face of the lead frame, which is on an opposite side to the first face. The first bonding wires connect the plural terminals of the oscillator to terminals of the integrated circuit. | 10-31-2013 |
20130278166 | SEMICONDUCTOR CIRCUIT AND SEMICONDUCTOR APPARATUS - A semiconductor circuit includes an operational amplifier, a voltage drop circuit, and a switch. The operational amplifier has an output terminal connected to an active element that produces a load drive current. A reference voltage is input to the non-inverting input of the operational amplifier. The voltage drop circuit drops a voltage outputted from the operational amplifier. The switch applies a voltage corresponding to a predetermined current flowing when the active element is on to the inverting input of the operational amplifier in a first interval in which the active element is on in response to a predetermined voltage from the operational amplifier. The switch allows the voltage dropped by the voltage drop circuit to be input to the inverting input in a second interval in which the active element is off, thereby shortening a time period until the load drive current starts to flow. | 10-24-2013 |
20130276147 | SEMICONDUCTOR DEVICE, CONFIDENTIAL DATA CONTROL SYSTEM, CONFIDENTIAL DATA CONTROL METHOD - A semiconductor device, confidential data control system and confidential data control method are provided capable of safeguarding confidential data even in cases of unauthorized access to a single storage medium. Capacities of each of confidential data segments, necessary when reading each of confidential data segments from an external memory and an internal memory, are acquired as control data from a register. Then each of the confidential data segments is read based on the acquired control data. It is accordingly rendered difficult to determine data related to the capacity of the confidential data even in cases of unauthorized access (hacking). Moreover, reading of the full confidential data does not occur even if unauthorized access to a single storage medium occurs (either the external memory or the internal memory). Consequently, unauthorized access can be suppressed. | 10-17-2013 |
20130275831 | SEMICONDUCTOR DEVICE, CONFIDENTIAL DATA CONTROL SYSTEM, CONFIDENTIAL DATA CONTROL METHOD - A semiconductor device, a confidential data control system and a confidential data control method are provided capable of safeguarding confidential data even in cases of unauthorized access. Control is performed to alternately store confidential data segments of divided confidential data and respective corresponding segment parity data in a memory. When reading the confidential data, errors in the confidential data segment are checked for with the segment parity data, corrected when an error has occurred, and read. The confidential data is not stored altogether in the memory, and so the confidential data is rendered difficult to discern even in cases in which unauthorized access (hacking) has occurred to the confidential data control system. | 10-17-2013 |
20130275702 | SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR READING OUT DATA - Unique output control is carried out in allowing or prohibiting an output unit to deliver data to outside from a memory unit, when the data at a designated address is read out of the memory unit in response to an address signal designating that address. The memory unit has an output enable/disable flag stored at a predetermined address. This flag is indicative of whether to permit the data to be delivered to outside. After power is turned on, the output unit prohibits the delivery of the data to outside until the output enable/disable flag indicates permission for data delivery to outside and the address signal designating the predetermined address is continuously supplied over N times the clock period of a clock signal. N is an integer equal to or greater than two. | 10-17-2013 |
20130272051 | NON-VOLATILE MEMORY AND SEMICONDUCTOR DEVICE - There is provided a non-volatile memory including: plural zener zap devices, each including a cathode region and an anode region formed in a well; and a metal wiring line that is formed above the plural zener zap devices, that is commonly connected to each of the cathode regions, and that supplies a write voltage to each of the zener zap devices. | 10-17-2013 |
20130272050 | NON-VOLATILE MEMORY, SEMICONDUCTOR DEVICE AND READING METHOD - There is provided a non-volatile memory circuit including: plural storage element sections each including a zener zap device and a switch section that connects an anode of the zener zap device to an output terminal during data reading; and wherein cathodes of respective zener zap devices of the plural storage element sections are commonly connected so as to be connected to a power supply employed in the writing or to a power supply employed in the reading, wherein the output terminals of the plural storage element sections are commonly connected to an input terminal of a detector, an anode of each of the storage element sections being connected to a ground voltage during data writing, and wherein the switch section is switched ON during data reading so as to connect the anode of the storage element section through the output terminal to the input terminal of the detector. | 10-17-2013 |
20130268792 | SEMICONDUCTOR DEVICE AND ELECTRICAL TERMINAL - A semiconductor device includes a moving state determining unit for obtaining first sensor data from a first sensor for detecting a moving state of a user who possesses an electrical terminal so that the moving state determining unit performs a determination process of the moving state of the electrical terminal; a reliability information determining unit for determining reliability information indicating reliability of a determination result of the determination process; and a transmission processing unit for transmitting the determination result and the reliability information to a main control unit that controls the electrical terminal. | 10-10-2013 |
20130257830 | OUTPUT DRIVER, ELECTRICAL DEVICE HAVING THE OUTPUT DRIVER, AND METHOD OF EVALUATING THE OUTPUT DRIVER - An output driver includes a data processing unit configured to perform a data processing on an input signal to generate processing result data; a D/A (Digital-to-Analog) conversion unit configured to apply D/A conversion on the processing result data to generate an analog signal; an output amplifier configured to amplify the analog signal to obtain an amplified analog signal as an output signal; a comparing unit configured to compare the processing result data with expected value data to obtain and output comparison result data; and an output control unit configured to select the comparison result data as the output signal instead of the amplified analog signal according to a comparison output selection signal. | 10-03-2013 |
20130257441 | BATTERY MONITORING SYSTEM AND SEMICONDUCTOR DEVICE - A battery monitoring system including: plural battery cell sets; and semiconductor devices, wherein: each of the semiconductor devices includes a measuring section, a high side communication section that is supplied with a drive voltage in a first voltage range, and, when a semiconductor device is present at a higher position that operates at a higher operating voltage than the operating voltage of the semiconductor device itself when measuring a battery cell set on the high side of the battery cell set measured by the semiconductor device itself, can perform communication with the high side semiconductor device, a low side communication section, and a communication level converter; the semiconductor device at the highest stage further includes a signal level determination section; and the first voltage range of the highest stage is set to a specific voltage range narrower than the first voltage range of another of the semiconductor devices. | 10-03-2013 |
20130251077 | DATA RECEIVING CIRCUIT AND DATA RECEIVING METHOD - A data receiving circuit an a data receiving method accurately acquire a data signal corresponding to information data from a high speed high density transmitted signal. An increase or a decrease of the level of one of a amplified data signal and a level converted data signal that is transmitted from one, referred to as one processing stage, of an amplification processing stage and a level converting processing stage, is fed back to a stage preceding the one processing stage. The amplification processing stage supplies, to a first line, an amplified data signal obtained by performing an amplification processing on a received data signal, and the level converting processing stage transmits, via a second line, a level converted data signal obtained by performing a level converting processing on the amplified data signal. | 09-26-2013 |
20130241566 | SEMICONDUCTOR CIRCUIT, BATTERY MONITORING SYSTEM, AND DIAGNOSIS METHOD - A semiconductor circuit, battery monitoring system, diagnostic program and diagnosis method are provided enabling appropriate self-diagnosis of a measurement unit. An output value (A-B) output through respective power supply lines V (Vn, Vn−1), a cell selector switch, and a level shift circuit from an AD converter and an output value (B) of a directly input reference voltage B output from the AD converter are summed together. Diagnosis is made that no abnormality such as a defect has occurred when the summed value is substantially the same as a reference voltage A. | 09-19-2013 |
20130234251 | SEMICONDUCTOR INTEGRATED DEVICE - A semiconductor integrated device in which electrostatic discharge damage can be reliably prevented, includes a semiconductor substrate in which an electrostatic protection circuit including a second diffusion region surrounding a first diffusion region as a local region is formed in a main surface; a metal pad opposed to the main surface; and a conductive bump formed so as to face a top surface of the metal pad, wherein in a surface opposed to the metal pad of the conductive bump, a projection which is in contact with the metal pad is provided in a range opposed to the first diffusion region. | 09-12-2013 |
20130229295 | AD (ANALOG-TO-DIGITAL) CONVERSION CIRCUIT, MICRO-CONTROLLER, AND METHOD OF ADJUSTING SAMPLING TIME - An AD (analog-to-digital) conversion circuit includes a capacitor array formed of a plurality of capacitors; a sample hold circuit configured to apply an analog input voltage input through an input terminal to the capacitor array so that the analog input voltage is accumulated in the capacitor array until a sampling time set is elapsed; a comparator circuit configured to sequentially retrieve the analog input voltage accumulated in each of the capacitors of the capacitor array, and to compare the analog input voltage with a reference voltage defined in advance to generate a digital signal; and a sampling time adjusting circuit configured to measure a period of time when a voltage on an input side of the sample hold circuit reaches a threshold value defined in advance relative to the reference voltage, and to set a time determined according to the period of time as the sampling time. | 09-05-2013 |
20130222074 | OSCILLATION FREQUENCY REGULATING CIRCUIT, SEMICONDUCTOR DEVICE, ELECTRONIC DEVICE AND OSCILLATION FREQUENCY REGULATION METHOD - There is provided an oscillation frequency regulating circuit including: a measuring section that performs measurement based on an oscillation frequency of an oscillation circuit; a comparator section that compares a measurement value measured by the measuring section against a set comparison value over a set comparison duration; a setting section that sets a comparison value selected from a plurality of comparison values of different magnitudes and that sets in the comparator section the comparison duration according to the magnitude of the selected comparison value; and a regulation section that, based on the comparison result of the comparator section, regulates the oscillation frequency of the oscillation circuit such that the oscillation frequency that is measured by the measuring section becomes a target oscillation frequency. | 08-29-2013 |
20130222068 | OSCILLATION CIRCUIT, INTEGRATED CIRCUIT, AND ABNORMALITY DETECTION METHOD - There is provided an oscillation circuit including: a main oscillation circuit that outputs a specific main clock to an internal circuit; a sub oscillation circuit that outputs a sub clock having a different frequency to the frequency of the main oscillation circuit; a first abnormality detection section that detects an abnormality according to a number of main clock cycles output from the main oscillation circuit within a predetermined period corresponding to sub clock outputs from the sub oscillation circuit; and a second abnormality detection section that detects an abnormality according to a frequency divided clock of the main clock output from the main oscillation circuit that has been frequency-divided and the sub clock output from the sub oscillation circuit. | 08-29-2013 |
20130186198 | GRAVITY AXIS DETERMINATION APPARATUS AND MOBILE TERMINAL APPARATUS USING THE SAME - A gravity axis determination apparatus which can determine the gravity direction in a short time. The apparatus is low in cost and has a simple construction. Data values of acceleration data trains in a same time zone are mutually compared and one of the three axes is determined as a gravity axis. | 07-25-2013 |
20130176058 | VOLTAGE COMPARISON CIRCUIT - There is provided a voltage comparison circuit including: a voltage adjustment section connected between a first potential supply line and a first node; a first constant current source connected between the first node and a fixed potential supply line; a switch element connected between a second potential supply line and a second node, and including a control terminal connected to the first node, the switch element operating in accordance with a voltage of the first node; and a second constant current source connected between the second node and the fixed potential supply line. | 07-11-2013 |
20130175994 | BATTERY RESIDUAL AMOUNT MEASUREMENT SYSTEM, COMPUTER-READABLE MEDIUM STORING BATTERY RESIDUAL AMOUNT MEASUREMENT PROGRAM, AND BATTERY RESIDUAL AMOUNT MEASUREMENT METHOD - The present invention provides a battery residual amount measurement system including: a current detection section that defects a current value of current discharged from a battery that is an object of measurement: a first storage section that stores reference undischargeable amounts that are determined in advance in accordance with ambient temperatures of the battery and current values of current discharged from the battery; and a calculating section that when a discharging operation is carried out at the battery, acquires, from the first storage section, the reference undischargeable amount that corresponds to an ambient temperature of the battery and the current value detected by the current detection section, and calculates a battery residual amount on the basis of a undischargeable amount that is calculated and computed on the basis of the acquired reference undischargeable amount and a nominal battery capacity of the battery. | 07-11-2013 |
20130169352 | BOOSTING CIRCUIT OF CHARGE PUMP TYPE AND BOOSTING METHOD - A boosting circuit includes an input terminal to which a power voltage is applied, a first capacitor connected to the input terminal, second and third capacitors, a first circuit including a first switch through which one end of the first capacitor is connected to one end of the second capacitor, and a second switch through which another end of the first capacitor is connected to another end of the second capacitor, a second circuit including a third switch through which the one end of the first capacitor is connected to the other end of the second capacitor, and a fourth switch through which the one end of the second capacitor is connected to one end of the third capacitor, the other end of the first capacitor being connected to another end of the third capacitor, and a fifth switch through which the one end of the first capacitor is connected to the one end of the third capacitor. | 07-04-2013 |
20130148762 | CIRCUIT AND METHOD FOR REMOVING FREQUENCY OFFSET, AND COMMUNICATION APPARATUS - A circuit and a method for removing a frequency offset and a communication apparatus including the circuit, capable of removing the frequency offset by tracking rapidly and accurately in a payload section. A sequence of sample levels is obtained by sampling a frequency level of the baseband signal at every 0.5 symbol interval. Absolute values of differences between the frequency levels adjacent to each other at every 1 symbol are calculated as first difference absolute values. Absolute values of differences between the frequency levels adjacent to each other at every 1 symbol are calculated as second difference absolute values. When the first difference absolute values are greater than a predetermined first determination value or the second difference absolute values are less than a predetermined second determination value, the average value calculated is set as the frequency offset. | 06-13-2013 |
20130147271 | POWER SUPPLY DEVICE, METHOD FOR CONTROLLING THE POWER SUPPLY DEVICE, AND ELECTRONIC APPARATUS - Provided are a power supply device capable of producing a highly-accurate supply voltage at low power consumption, a method for controlling the power supply device, and an electronic apparatus in which the power supply device is incorporated. The power supply device includes a first power supplying part and a second power supplying part which has less output current capacity than the first power supplying part does. The power supply device is configured to control the voltage value of the second voltage produced in the second power supplying part in order to make the first voltage produced in the first power supplying part equal to the second voltage produced in the second power supplying part. | 06-13-2013 |
20130145198 | TIME MEASUREMENT DEVICE, MICRO-CONTROLLER AND METHOD OF MEASURING TIME - A time measurement device includes a first measurement unit configured to measure a clock number of a first reference clock signal within a specific cycle of a second reference clock signal; a calculation unit configured to calculate a physical amount indicating a variance amount of the clock number relative to a reference clock number; a compensation unit configured to compensate an expected measurement value indicating the clock number of the first reference clock signal corresponding to a time as a measurement target according to the physical amount calculated with the calculation unit; and an output unit configured to output time information indicating that the clock number of the first reference clock signal reaches the expected measurement value when the clock number of the first reference clock signal measured with the first measurement unit reaches the expected measurement value compensated with the compensation unit. | 06-06-2013 |
20130141164 | VOLTAGE OUTPUT DEVICE HAVING AN OPERATIONAL AMPLIFIER - A voltage output device capable of preventing an increase in circuit scale includes an offset compensation function and is suitably applicable to a drive circuit for display devices. The voltage output device includes an operational amplifier having an inverting input terminal and a non-inverting input terminal. Resistance values of a load resistor on the inverting input side and a load resistor on the non-inverting input side are maintained when the output voltage of the amplifier has changed while sequentially varying either one or both of the resistance values of the load resistor on the inverting input side and the load resistor on the non-inverting input side in a state that the inverting input terminal and the non-inverting input terminal are connected. The voltage output device is configured to output the output voltage of the amplifier with the inverting input terminal not connected to the non-inverting input terminal. | 06-06-2013 |
20130121377 | TEMPERATURE DETECTION CIRCUIT AND METHOD OF ADJUSTING THE SAME - A temperature detection circuit that can detect temperature with high accuracy regardless of manufacturing variations, and a method of adjusting the same. The circuit includes: first and second diodes having respective independent p-n junctions; a first current path including a first variable voltage dividing resistor series connected to the first diode; a second current path including a second variable voltage dividing resistor series connected to the second diode; a reference voltage generation part that feeds back a differential voltage to each of the first and second current paths and outputs as a reference voltage the differential voltage indicating a difference between a first divided voltage of the first variable voltage dividing resistor and a potential on the second current path; and a temperature detection signal generation part generating a temperature detection signal based on a second divided voltage of the second variable voltage dividing resistor. | 05-16-2013 |
20130104004 | RAM MEMORY DEVICE - A RAM memory device includes a selection unit that supplies the access reaching one of two interfaces to a RAM in one cycle of a clock signal in response to a control signal. The RAM memory device also includes a storage unit that stores another access that has reached the other of the two interfaces at least till the next cycle following the above-mentioned one cycle in response to the control signal. The selection unit supplies the above-mentioned another access from the storage unit to the RAM in or after the above-mentioned next cycle. | 04-25-2013 |
20130099841 | NOISE REDUCTION DEVICE AND SEMICONDUCTOR DEVICE HAVING THE SAME - A semiconductor device includes a first terminal for receiving a first signal; a second terminal for receiving a second signal having more restriction than the first signal with respect to a delay upon transmitting to an internal circuit; a first noise reduction circuit; and a second noise reduction circuit. The first noise reduction circuit includes a first Schmitt circuit for receiving the first signal from the first terminal; and an output signal adjusting unit for adjusting an output signal of the first Schmitt circuit when the output signal is maintained for a specific period of time after the output signal is varied. The second noise reduction circuit includes a second Schmitt circuit for receiving the second signal from the second terminal; and an input signal adjusting unit for adjusting the second signal input to the second Schmitt circuit according to a fluctuation of a power source voltage. | 04-25-2013 |
20130086379 | COMMUNICATION APPARATUS, RECEPTION CONTROL METHOD, AND TRANSMISSION CONTROL METHOD - Lookaside-type communication apparatus and reception and transmission control methods make high-rate communication of a packet including encrypted data. Receive data including encrypted data are supplied to an encryption data processing part, and supplied to a security part through a second bus when the packet is received. The encrypted data becomes plain-text data in the security part, and supplied to the control part through the system bus. Transmit data including a data body including a plain-text data to be encrypted are supplied to the security part when the packet is transmitted. The plain-text data become the encrypted data in the security part, and the transmit data having the data body including the encrypted data are supplied to the encryption data processing part through the second bus. The transmit data are transmitted in the form of the packet in the transmission and reception part. | 04-04-2013 |
20130077398 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND PROGRAMMING METHOD - A nonvolatile semiconductor memory device of the charge trap type is initialized by reading the memory cells in the device to determine which charge traps hold less than a predetermined minimum charge and injecting charge into these charge traps until all of the charge traps in the device hold at least the predetermined minimum charge. The charge traps are then programmed selectively with data. The initialization procedure shortens the programming procedure by narrowing the initial distribution of charge in the charge traps, and leads to more reliable reading of the programmed data. | 03-28-2013 |
20130069597 | SEMICONDUCTOR CIRCUIT, BATTERY MONITORING SYSTEM, AND CONTROL METHOD - A semiconductor circuit is provided. The semiconductor circuit includes: a drive component that includes first switching elements connected to discharge switching elements and resistive elements; and a drawing component. The first switching elements interconnect, in accordance with a drive time of the discharge switching elements, drive current sources that supply charge to control signal lines and the control signal lines. The drawing component draws charge with draw current sources in accordance with a draw time in which the drawing component draws the charge supplied from the drive component. | 03-21-2013 |
20130069156 | SEMICONDUCTOR DEVICE - A semiconductor device formed on a silicon-on-insulator substrate includes a gate electrode, a gate insulation film, a drain diffusion region, a drift region, a body region, a plurality of source diffusion regions, and a plurality of charge collection diffusion regions. The source diffusion regions and charge collection diffusion regions are of mutually opposite conductivity types, and alternate with one another in the direction paralleling the width of the gate electrode. The half-width of each source diffusion region is equal to or less than the length of the gate electrode plus the half-length of the drift region. | 03-21-2013 |
20130058207 | SEMICONDUCTOR INTEGRATED CIRCUIT - Disclosed is a semiconductor integrated circuit capable of efficiently performing debugging. The semiconductor integrated circuit includes a distributing part distributing received packets according to destinations of the packets, a plurality of accumulating parts sequentially accumulating the packets distributed thereto, respectively, a plurality of relaying parts supplying the packets accumulated in one of the accumulating parts to corresponding one of the processing parts, respectively, and an output controlling part assigning the relay permission command to one relaying part designated by a relay permission packet from among the relaying parts when a packet distributed thereto from the distributing part is determined as the relay permission packet. | 03-07-2013 |
20130043537 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - There is provided a semiconductor device and a method for manufacturing a semiconductor device. Within the N-type semiconductor layer formed from a high resistance N-type substrate, the P-type well diffusion layer and P-type extraction layer are formed and are fixed to ground potential. Due thereto, a depletion layer spreading on the P-type well diffusion layer side does not reach the interlayer boundary between the P-type well diffusion layer and the buried oxide film. Hence, the potential around the surface of the P-type well diffusion layer is kept at a ground potential. Accordingly, when the voltages are applied to the backside of the N-type semiconductor layer and a cathode electrode, a channel region at the MOS-type semiconductor formed as a P-type semiconductor layer is not activated. Due thereto, leakage current that may occur independently of a control due to the gate electrode of a transistor can be suppressed. | 02-21-2013 |
20130033251 | SEMICONDUCTOR INTEGRATED CIRCUIT - A semiconductor integrated circuit includes constant current circuit, starter circuit and power supply start-up circuit. In the constant current circuit, first current mirror circuit includes first and second transistors, and second current mirror circuit includes third and fourth transistors that are connected to first and second nodes. In the starter circuit, a potential of first node controls sixth transistor, seventh transistor is connected to third node, gate electrode of the seventh transistor is at ground potential, a capacitance element is connected to fourth node, and a potential of fourth node controls fifth transistor, which supplies start-up current to the constant current circuit via second node. In the power supply start-up circuit, source electrode of eighth transistor is fixed at power supply voltage, gate electrode is at ground potential, and drain electrode supplies power to the other circuits. | 02-07-2013 |
20130033108 | POWER SUPPLY CONTROL SYSTEM AND SEMICONDUCTOR INTEGRATED CIRCUIT - The present invention provides a power supply control system and a semiconductor integrated circuit that may prevent reverse current flow from a solar battery to a primary battery. Namely, in a first switching circuit, a first voltage that is the primary battery output voltage dropped by a first voltage level and a second voltage that is the load side voltage dropped by a second voltage level are compared by a comparator. Electrical connection between the primary battery and the load is disconnected when the second voltage is equal to or greater than the first voltage. In a second switching circuit for a solar battery and the load, the switching circuit is similarly switched OFF before the load side voltage exceeds the output voltage of the primary battery or the solar battery, preventing damage to the battery due to reverse flow of current. | 02-07-2013 |
20130023117 | SEMICONDUCTOR DEVICE MANUFACTURING METHOD AND SEMICONDUCTOR DEVICE MANUFACTURING APPARATUS - A method of manufacturing a semiconductor device includes: preparing a wafer member, the wafer member including a wafer, a conductive layer formed on a surface of the wafer and a negative photoresist formed on the conductive layer; applying a light blocking material so as to cover at least a part of an outer edge of the wafer member from an upper surface of the negative photoresist to a side surface of the negative photoresist; exposing the negative photoresist to exposure light; removing the light blocking material; and developing the negative photoresist. | 01-24-2013 |
20130016762 | DATA COMMUNICATION SYSTEM, METHOD OF OPTIMIZING PREAMBLE LENGTH, AND COMMUNICATION APPARATUSAANM Tanaka; HitoshiAACI KanagawaAACO JPAAGP Tanaka; Hitoshi Kanagawa JP - A frame is effectively transmitted and received by setting an optimal preamble length according to transmission environments between communication apparatuses. A data communication system includes a synchronization detection part to detect bit synchronization based on the preamble of the frame received to the second communication apparatus from the first communication apparatus, a synchronization position information generating part to generate synchronization position information of a position of the bit synchronization, which is in the frame received in the second communication apparatus, detected by the synchronization detection part, a preamble length calculating part to calculate an optimal value of a length of the preamble based on the synchronization position information, and a transmit command issuing part to issue a transmit command of transmission of the frame including the preamble having the length based on the optimal value from the first communication apparatus to the second communication apparatus. | 01-17-2013 |
20120319793 | OSCILLATION CIRCUIT - There is provided an oscillation circuit including: a band-gap circuit that outputs an output voltage adjusted for temperature dependency so as to give a constant output voltage independent of temperature; a voltage-current conversion circuit including a first variable resistor, the voltage-current conversion circuit converting an output voltage output from the band-gap circuit into an output current corresponding to the resistance of the first variable resistor and outputting a bias current based on the converted output current; and a CR oscillation circuit including a second variable resistor, a capacitor and a comparator section, the CR oscillation circuit oscillating with an oscillation frequency based on the resistance of the second variable resistor and the capacitance value of the capacitor, and the CR oscillation circuit operating according to the amperage of the bias current the comparator section has input from the voltage-current conversion circuit. | 12-20-2012 |
20120315857 | WIRELESS COMMUNICATION METHOD AND APPARATUS - A wireless communication method and apparatus that produce only a small amount of transmission delay even when carrier sensing is performed. Intensity indication data indicating the radio wave intensity of a received wireless signal is generated. The intensity indication data is intermittently captured and retained. An average of the retained intensity indication data is calculated. If the average is less than or equal to a threshold, a wireless transmission operation is enabled. The average is calculated with a frequency according to the frequency of capturing of the intensity indication data. The average and the threshold are compared at a frequency corresponding to the frequency of calculation of the average. | 12-13-2012 |
20120314717 | FRAME TRANSMITTING APPARATUS, FRAME RECEIVING APPARATUS, AND FRAME TRANSMISSION/RECEPTION SYSTEM AND METHOD - To enable more precise synchronization of distributed clocks, before a high-level frame is converted to a low-level frame for transmission over a communication network, if the high-level frame includes a certain type of message, it is flagged. The flag is detected during the conversion process, and the time of detection is stored as a transmission timestamp. When a low-level frame is received from the network, it is immediately timestamped with the time of reception. The timestamped frame is then converted to a high-level frame, and if the high-level frame includes the certain type of message, the timestamp is stored as a reception timestamp. | 12-13-2012 |
20120306571 | VOLTAGE OUTPUT DEVICE HAVING AN OPERATIONAL AMPLIFIER - A voltage output device capable of preventing an increase in circuit scale includes an offset compensation function and is suitably applicable to a drive circuit for display devices. The voltage output device includes an operational amplifier having an inverting input terminal and a non-inverting input terminal. Resistance values of a load resistor on the inverting input side and a load resistor on the non-inverting input side are maintained when the output voltage of the amplifier has changed while sequentially varying either one or both of the resistance values of the load resistor on the inverting input side and the load resistor on the non-inverting input side in a state that the inverting input terminal and the non-inverting input terminal are connected. The voltage output device is configured to output the output voltage of the amplifier with the inverting input terminal not connected to the non-inverting input terminal. | 12-06-2012 |
20120306549 | SEMICONDUCTOR INTEGRATED CIRCUIT - A semiconductor integrated circuit includes a constant current circuit and a start-up circuit. The constant current circuit includes a first current mirror circuit including a first and second transistors; and a second current mirror circuit including a third transistor connected to a first node and a fourth transistor connected to a second node. The start-up circuit includes a fifth transistor that supplies start-up current to the constant current circuit via the second node; a sixth transistor that uses a potential of the first node as a control voltage; a seventh transistor that is connected to a third node into which current from the sixth transistor flows and that has a diode-connected configuration; a capacitor connected to a fourth node into which current from the seventh transistor flows; and a latch circuit that controls the fifth based on a potential of the fourth node. | 12-06-2012 |
20120306068 | SEMICONDUCTOR DEVICE FABRICATION METHOD AND SEMICONDUCTOR DEVICE - A semiconductor device is manufactured by forming a first dielectric film on a substrate, forming an aperture in the first dielectric film, mounting a semiconductor chip in the aperture, forming a second dielectric film on the first dielectric film and the semiconductor chip, and forming an interconnection wiring structure on the second dielectric film. The second dielectric film secures the semiconductor chip without the need to etch the substrate or use an adhesive die attachment film. | 12-06-2012 |
20120297263 | SEMICONDUCTOR CHIP AND TEST METHOD - A semiconductor chip having a functional block that performs a communication function includes an input circuit that supplies an oscillating test signal to the functional block, and a test circuit that detects the strength of an oscillating signal which the functional block outputs in response. A strength signal indicating the detected strength is output from the test circuit through an external terminal of the semiconductor chip to a test device. The test device evaluates the strength signal to decide whether an operating characteristic of the functional block is within a specified range. The strength information indicated by the strength signal is not affected by impedance on the signal transmission line between the semiconductor chip and the test device, so the test is not affected by impedance loss. | 11-22-2012 |
20120293125 | COMPARATOR CIRCUIT, SEMICONDUCTOR DEVICE, BATTERY MONITORING SYSTEM, CHARGING ROHIBITION METHOD, AND COMPUTER-READABLE MEDIUM - A comparator circuit includes: a switching element that is disposed between a positive electrode of a battery cell and a fixed potential supply source, that has a control terminal connected to a negative electrode of the battery cell, and that operates in response to a voltage applied from the battery cell to the control terminal; a voltage regulating unit that is disposed between the battery cell and the switching element and that regulates the voltage applied from the battery cell to the switching element; and an output signal line that outputs a potential between the switching element and the fixed potential supply source. | 11-22-2012 |
20120288045 | SIGNAL RECEIVING APPARATUS AND METHOD OF CONTROLLING FILTERS IN SIGNAL RECEIVING APPARATUS - A signal receiving device receives an incoming signal to obtain a frequency signal. The signal receiving device has a multi-filter device. The frequency signal is subjected to frequency selection processing by using the multi-filter device. The multi-filter device has a plurality of filters whose frequency characteristics are different from each other. The filters are connected in series. If the received signal intensity is higher than prescribed threshold intensity, the center frequency of at least one of the filters in the multi-filter device is biased. | 11-15-2012 |
20120286385 | SEMICONDUCTOR DEVICE, CAMERA MODULE, AND SEMICONDUCTOR DEVICE MANUFACTURING METHOD - A semiconductor device is provided which has a semiconductor element having an element forming surface at which a sensor element is formed, a back surface on the opposite side of the element forming surface, and a light transmissive protective member laminated over the element forming surface via an adhering portion. The semiconductor device includes a region exposed from the protective member at the outer peripheral end portion of the semiconductor element, when viewed from the protecting member in a laminating direction. | 11-15-2012 |
20120269022 | INTERNAL POWER SOURCE VOLTAGE GENERATING CIRCUIT OF SEMICONDUCTOR MEMORY AND METHOD FOR GENERATING INTERNAL POWER SOURCE VOLTAGE - An internal power source voltage generating circuit of a semiconductor memory and a corresponding method shorten an access delay upon transition of a data reading operation in an address period shorter than a prescribed minimum period to an operation in the prescribed minimum period. While a boosted voltage of an external power source voltage is supplied to the semiconductor memory as the internal power source voltage via an output line connected to one end of a condenser. A reference low potential is applied to the other end of the condenser and the external power source voltage is applied to the output line, thereby charging the condenser. If the internal power source voltage is lower than a threshold voltage, the internal power source voltage on the output line is boosted by applying the external power source voltage to the other end of the condenser. | 10-25-2012 |
20120268208 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - There is provided a semiconductor integrated circuit device including: a differential amplification circuit having a non-inverting input terminal that receives a reference voltage and an inverting input terminal connected to an output load; and an output circuit including a first MOS transistor having a gate connected to an output terminal of the differential amplification circuit, a source, and a drain connected to the inverting input terminal of the differential amplification circuit such that the first MOS transistor is ON/OFF in an operation state/a non-operation state, and a second MOS transistor connected in series between a power source and the source of the first MOS transistor, with a gate width/gate length ratio of the second MOS transistor smaller than a gate width/gate length ratio of the first MOS transistor, such that the second MOS transistor is ON in the operation state and OFF in the non-operation state. | 10-25-2012 |
20120253759 | PROCESSING SUPPORT DEVICE, METHOD AND COMPUTER READABLE STORAGE MEDIUM, AND SEMICONDUCTOR FABRICATION SUPPORT DEVICE AND METHOD - Using an equipment-classified processing results database, an intercept satisfying a second predetermined condition is derived from intercepts of straight lines that pass through a reference co-ordinate point, which satisfies a first predetermined condition, and respective co-ordinate points in a region bounded by: a line that passes through the reference co-ordinate point and is parallel to an x-axis representing wafer counts X; a y-axis representing processing durations Y; and a line passing through the reference co-ordinate point and the origin. Of co-ordinate points represented by an equipment and recipe-classified processing results database, a gradient satisfying a third predetermined condition is derived from gradients of lines that pass through the derived intercept and each of all co-ordinate points with wafer counts X at or above a predetermined number. A processing duration is derived using a regression equation into which the derived intercept and the derived gradient are substituted. | 10-04-2012 |
20120249884 | RECEIVER, SHUTTER GLASSES, AND COMMUNICATION SYSTEM - A receiver allows controlling a device to be controlled such as a display device based on reference timing acquired from reception data without delay and with low power consumption, and includes: a communication device receiving data incoming intermittently; a first control circuit analyzing the data received by the communication device to identify the presence of a predetermined reference timing signal pattern in the data; and a timer for counting a clock from an initial value, generating a control signal for the device to be controlled according to a resulting count value, and if the count value reaches a predetermined interval value, resuming counting the clock at the initial value. The timer changes the initial value to reduce a count of the clock between the initial value and the interval value if the first control circuit identifies the predetermined reference timing signal pattern to be present. | 10-04-2012 |
20120249760 | COMMUNICATION DEVICE, CONTROL SIGNAL GENERATION METHOD, SHUTTER GLASSES, AND COMMUNICATION SYSTEM - A communication device allows control of a device to be controlled such as a display device based on reference timing acquired from reception data without delay and with low power consumption. A method for generating a control signal for controlling the device to be controlled, shutter glasses, and a communication system having the corresponding features are also disclosed. The communication device includes a timing signal identifying part which identifies whether or not a predetermined reference signal pattern exist in data incoming intermittently, and a control signal generating part which generates a control signal for the device to be controlled when the existence of the predetermined signal pattern is identified by the timing signal identification part, and a controller which performs the control of the communication device. | 10-04-2012 |
20120249608 | DRIVER CIRCUIT FOR A DISPLAY DEVICE, AND DRIVER CELL - A driver circuit for driving a display panel is formed on a substrate and is organized into two families of sections. Each section includes a logic circuit, a level shifter, a decoder, an operational amplifier, and an output pad. In the first family, each section is laid out in the stated sequence (logic circuit, level shifter, decoder, operational amplifier, output pad). In the second family, each section is laid out in a different sequence: output pad, operational amplifier, logic circuit, level shifter, decoder. The output pads in the two families of sections are located on opposite sides of the substrate, and every output pad is adjacent to the operational amplifier to which it is connected. This arrangement reduces signal-to-signal variations in the output characteristics of the driver circuit and improves the slew rate of the output signals. | 10-04-2012 |
20120249607 | OUTPUT CIRCUIT FOR REDUCING OFFSET FOR USE IN SOURCE DRIVER ADAPTED TO DRIVE LIQUID CRYSTAL DEVICE - An offset-reducing output circuit of a source driver adapted to drive a liquid crystal device. The output circuit includes an operational amplifier having a non-inverting input to receive a reference voltage. The output circuit also includes input and output capacitors. One terminal of the input capacitor and one terminal of the output capacitor are connected to a node extending to an inverting input of the operational amplifier in at least a normal output operation mode. The output circuit also includes a switching circuit to short both terminals of the input capacitor and both terminals of the output capacitor in a reset operation so that the reference voltage is applied to the terminals of the input and output capacitors respectively. The switching device applies a gray scale voltage to an opposite terminal of the input capacitor in a normal operation mode. | 10-04-2012 |
20120249208 | CLAMP CIRCUIT, SEMICONDUCTOR DEVICE, SIGNAL PROCESSING SYSTEM, AND SIGNAL CLAMPING METHOD - The present invention provides a clamp circuit including, a switching section including first and second switching elements connected parallel between a current supply source and a clamp capacitor; a first control section that controls the first switching element to connect the current supply source and the clamp capacitor, when the voltage of an input signal input through the clamp capacitor is lower than a first reference voltage; and a second control section that stores voltage information based on the input signal when the voltage of the input signal is lower than a second reference voltage, and that controls the second switching element to connect the current supply source and the clamp capacitor for a period predetermined based on the voltage information, when the input signal is equal to or higher than the first reference voltage. | 10-04-2012 |
20120230157 | CLOCK DISPLAY DEVICE - There is provided a clock display device including: a central processing unit; a liquid crystal display section; a clock information generating section; a converting section that converts the clock information into character data for display at the liquid crystal display section; a direct memory access section that fetches the character data for display without going through the central processing unit, and transfers the fetched character data for display without going through the central processing unit; a display register that stores the character data for display; a programmable display allocating section that allocates correspondences between respective bits of the character data for display that is within the display register, and respective display segments of the liquid crystal display section; and a display control section that, on the basis of results of the allocation, visibly displays the clock information at the liquid crystal display section. | 09-13-2012 |
20120230133 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND DATA WRITING METHOD - A nonvolatile semiconductor memory quickly and precisely accumulates a desired amount of charges corresponding to data-to-be-written in a charge accumulating part of a memory cell. When charges are injected into the charge accumulating part of the memory cell by applying a writing voltage corresponding to the data-to-be-written to the drain or source region of the memory cell, the writing voltage is reduced on the basis of an increase in the amount of charges accumulated in the charge accumulating part. | 09-13-2012 |
20120220250 | SIGNAL RECEIVING DEVICE AND SIGNAL RECEIVING METHOD - A signal receiving device and signal receiving method to pass a desired frequency component of an intermediate frequency signal by using an IF filter without increasing a chip area. The signal receiving device comprises: a mixer to mix a received frequency signal with a local oscillation frequency signal to generate an intermediate frequency signal; an IF filter to pass a predetermined frequency component of the intermediate frequency signal; a controlling part which adjusts, according to a frequency band of the intermediate frequency signal, the frequency band of the IF filter, and adjust, according to a center frequency set in the IF filter that fluctuates with the adjustment, a center frequency of the intermediate frequency signal to be inputted in the IF filter; and a demodulating part to demodulate a frequency component of the intermediate frequency signal outputted after passing through the IF filter. | 08-30-2012 |
20120212290 | FSK DEMODULATOR - An FSK demodulator and a method for detecting an inflection point extract a greater amount of effective inflection points of a frequency detection signal while reducing erroneous detection of the inflection points. The inflection point detector includes an inflection point extraction part to extract the inflection point corresponding to variation of a sample value of an amplitude value of the frequency detection signal, an amplitude determination part to determine if a size between peak values of sample values in front and rear of the inflection point exists in a first predetermined range, a preamble determination part to determine if a difference between initial and final sample values of at least one of a symbol having the extracted inflection point and a right before symbol exists in a second predetermined range, and an AND operation part to determine a normal inflection point. | 08-23-2012 |
20120206846 | OVERVOLTAGE PROTECTION CIRCUIT AND SEMICONDUCTOR INTEGRATED CIRCUIT - Disclosed is an overvoltage protection circuit which includes a first terminal through which a first voltage is supplied to an internal circuit; a second terminal through which a second voltage is supplied; a rectifier having an input end connected to the first terminal and having an output end; and first-stage to n-th-stage switching elements which are connected in parallel to one another. The first-stage to n-th-stage switching elements have first to n-th controlling ends, respectively. Each of the switching elements has first and second controlled ends connected to the first terminal and the second terminal, respectively. The rectifier is configured to output a control voltage from the output end thereby to cause the first-stage to n-th-stage switching elements to be turned on, in response to receipt of an overvoltage from the first terminal. | 08-16-2012 |
20120206204 | VARIABLE GAIN AMPLIFIER CIRCUIT - A variable gain amplifier circuit with a small-sized configuration can accurately adjust the gain without causing a transmission loss of an input signal. A plurality of amplification portions are connected with each other between an amplification coupling line and a grounding line in parallel. The amplification portion includes a switching device and an amplification transistor, which induces a current corresponding to an input signal to flow between the amplification coupling line and the grounding line via the switching device when the switching device is in the on state. The amplitude gain is varied by, according to a gain control signal, separately switching on and off the switching devices of the respective amplification portions. | 08-16-2012 |
20120200330 | SEMICONDUCTOR INTEGRATED CIRCUIT, SEMICONDUCTOR CHIP AND METHOD OF DESIGNING SEMICONDUCTOR INTEGRATED CIRCUIT - A semiconductor integrated circuit includes a delay circuit connected between a source of data bits and a data input terminal of a latch circuit. The delay circuit includes a first delay section formed by connecting logic devices in series corresponding to a number of logic devices included in a clock signal path between a clock signal source and the latch circuit data input. The delay circuit also includes a second delay section having a delay time equal to an interconnect delay time corresponding to a wiring length of the clock signal path. | 08-09-2012 |
20120193813 | WIRING STRUCTURE OF SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE WIRING STRUCTURE - A wiring structure of a semiconductor device, includes: an insulating layer formed on a base member; a first metal layer covered with the insulating layer; a second metal layer having a plurality of electrode parts which are arranged on the insulating layer to be spaced from each other and which have a thickness larger than the first metal layer, the insulating layer having a plurality of via holes which connect the first metal layer and the plurality of electrode parts; and a plurality of through wiring lines which are located within the plurality of via holes and which electrically connect the plurality of electrode parts to the first metal layer. | 08-02-2012 |
20120193714 | SOI SUBSTRATE, METHOD OF MANUFACTURING THE SOI SUBSTRATE, SEMICONDUCTOR DEVICE, AND METHOD OF MANUFACTURING THE SEMICONDUCTOR DEVICE - Disclosed is an SOI substrate which includes a semiconductor base; a semiconductor layer formed over the semiconductor base; and a buried insulating film which is disposed between the semiconductor base and the semiconductor layer, so as to electrically isolate the semiconductor layer from the semiconductor base, where the buried insulating film contains a nitride film. | 08-02-2012 |
20120181994 | BOOSTING SYSTEM, DIAGNOSING METHOD, AND COMPUTER READABLE MEDIUM STORING DIAGNOSING PROGRAM - The present invention provides a boosting system, a diagnosing method and a diagnosing program, that may diagnose a boosting section while suppressing consumption of electric power and current, and without being carrying out by a CPU. Namely, during an initializing operation, difference between power supply voltage and own threshold voltage charges capacitor C | 07-19-2012 |
20120179411 | SEMICONDUCTOR CIRCUIT, SEMICONDUCTOR DEVICE, LINE BREAK DETECTION METHOD, AND COMPUTER READABLE MEDIUM STORING LINE BREAK DETECTION PROGRAM - When line break detection of signal line Ln is carried out, potential smaller than signal line Ln−1 having lower potential than signal line Ln is supplied to signal line Ln, and potentials of signal line Ln and signal line Ln−1 are compared. If potential of signal line Lc>signal line Li, it is detected no line break, and if signal line Lcsignal line Li, it is detected that a line break exists. | 07-12-2012 |
20120176160 | SEMICONDUCTOR CIRCUIT, BATTERY CELL MONITORING SYSTEM, COMPUTER READABLE MEDIUM STORING DIAGNOSTIC PROGRAM AND DIAGNOSTIC METHOD - The present invention provides a semiconductor circuit including: a comparator section that compares discharge sections, each including a first signal line connected to a high potential side of each of a plurality of battery cells that are connected in series, a second signal line connected to a low potential side of each of the plurality of battery cells, a resistance element provided between the first signal line and the second signal line, and a discharge switching element connected in series to the resistance element, wherein the comparator section compares a threshold voltage, set according to a potential difference between a potential of the first signal line and a potential of the second signal line, with a voltage according to a potential between the resistance element and the discharge switching element. | 07-12-2012 |
20120164815 | METHOD OF FORMING ELEMENT ISOLATION LAYER - There is provided a method of forming an element isolation layer, the method including: forming a pad oxide layer and a nitride layer in succession on a front face of a semiconductor substrate; forming a trench so as to penetrate through the pad oxide layer and the nitride layer and into the semiconductor substrate; forming an in-fill oxide layer so as to fill the trench and cover the nitride layer; polishing the in-fill oxide layer using a first polishing agent so as to leave in-fill oxide layer remaining over the nitride layer; and polishing the in-fill oxide layer using a second polishing agent having a polishing selectivity ratio of the in-fill oxide layer to the nitride layer greater than that of the first polishing agent, so as to expose the nitride layer and flatten the exposed faces of the nitride layer and the in-fill oxide layer. | 06-28-2012 |
20120163105 | SEMICONDUCTOR STORAGE DEVICE - A semiconductor storage device has a great number of logic circuits and fuse blocks with its space-saving design. In the semiconductor storage device, a plurality of fuse blocks is arranged in a line or row in the vicinity of a gate array. Each fuse block includes a plurality of fuse pieces arranged in a juxtaposed manner and exposed to the exterior through a fuse window. A power-supply wire and a ground wire extend along the juxtaposed direction of the fuse pieces. Spacing in the vicinity of the gate array is used for arrangement of the fuse blocks. | 06-28-2012 |
20120163089 | METHOD FOR WRITING DATA IN SEMICONDUCTOR STORAGE DEVICE AND SEMICONDUCTOR STORAGE DEVICE - A method for writing data in a semiconductor storage device and a semiconductor storage device are provided, that can reduce variations in readout current from a sub storage region which serves as a reference cell for the memory cells of the semiconductor storage device, thereby preventing an improper determination from being made when determining the readout current from a memory cell. In the method, data is written on a memory cell in two data write steps by applying voltages to the first and second impurity regions of the memory cell, the voltages being different in magnitude from each other. | 06-28-2012 |
20120163075 | NON-VOLATILE STORAGE DEVICE - There is provided a non-volatile storage device including: a bit line that is connected to a non-volatile storage element and is applied with a voltage of magnitude corresponding to the logic value stored in the storage element; a charging section that charges the bit line to a voltage of equivalent magnitude to the reference voltage; a voltage generation section that is connected between the reference voltage line and the bit line, comprises a capacitance load for generating coupling charge when charging by the charging section has been performed, and employs the capacitance load to generate a voltage according to a difference between the magnitude of the voltage of the reference voltage line and the magnitude of the voltage of the bit line as a voltage expressing the comparison result; and a charge absorbing section for absorbing the coupling charge generated by the capacitance load. | 06-28-2012 |
20120162618 | SUBSTRATE PROCESSING DEVICE AND METHOD - A semiconductor processing device sprays a liquid chemical agent onto a film on a spinning semiconductor substrate. The spray nozzle is moved horizontally from a first upper position comparatively distant from the substrate to a second upper position closer to the substrate, then vertically downward to a lower position. All of these positions are higher than the substrate and none of them overlie the substrate. The spray nozzle is then moved horizontally to a spray position over the substrate and spraying begins. Any residual liquid chemical agent remaining at the outlet of the spray nozzle from the processing of a previous substrate drops off harmlessly at the end of the downward vertical motion instead of dropping onto the film on the substrate. | 06-28-2012 |
20120142283 | WIRELESS COMMUNICATION APPARATUS - A wireless communication apparatus using a frequency signal produced by a frequency synthesizer operates at a reduced power consumption and includes a reception portion comprising a first mixer mixing a signal based on the received wireless signal and the frequency signal, a second mixer mixing the first mixer output signal and a local signal, and a demodulation stage demodulating the second mixer output signal. The frequency synthesizer comprises a Voltage Controlled Oscillator (VCO) generating a frequency signal responsive to a variation of a control input voltage, and a feed back circuit receiving as a control input voltage a voltage corresponding to a phase difference between a signal obtained by frequency dividing the output frequency signal of the VCO and a reference clock signal. The VCO is operable at a high frequency that increases with an increase of a bias current. | 06-07-2012 |
20120139523 | REFERENCE CURRENT OUTPUT DEVICE AND REFERENCE CURRENT OUTPUT METHOD - A reference current output device and reference current output method that may adjust a reference current while maintaining a temperature gradient. In the reference current output device and reference current output method of the present invention, a reference current is outputted by a reference voltage and current output circuit, a reference voltage outputted from the reference voltage and current output circuit is converted to an adjustment current and outputted by a conversion and output circuit, the adjustment current is superimposed with the reference current and a superimposed current is outputted by a superimposition and output section. | 06-07-2012 |
20120135610 | SYSTEM AND METHOD FOR PROCESSING SUBSTRATE - A substrate processing system including a cleaning equipment; a resist coating equipment forming a resist layer on a surface of a substrate; an edge exposure equipment that exposes to light an edge portion of the resist layer formed on a peripheral edge of the substrate; a substrate transport mechanism; and a system controller. The system controller includes a waiting time monitor and a process controller. The waiting time monitor monitors a waiting time that is a time interval between the formation of the resist layer and start of the exposure of the edge portion of the resist layer. The process controller causes the substrate transport mechanism to transport the substrate into the cleaning equipment when the monitored waiting time exceeds a prescribed limit, removing the resist layer from the substrate. The process controller then causes the substrate transport mechanism to transport the substrate into the resist coating equipment. | 05-31-2012 |
20120135572 | SEMICONDUCTOR DEVICE MANUFACTURING METHOD - A gate electrode is formed on a surface of a semiconductor substrate. A resist mask is formed that covers both end faces of the gate electrode in a gate width direction intersecting a gate length direction. Impurity ions are implanted into the semiconductor substrate in an implantation direction having a gate length direction component and a gate width direction component, to form a low-concentration impurity layer overlapping with the gate electrode at both sides of the gate electrode in the surface of the semiconductor substrate. A sidewall is formed that covers a side surface of the gate electrode. Impurity ions are implanted using the gate electrode and the sidewall as a mask, to form a high-concentration impurity layer apart from the gate electrode at both sides of the gate electrode on the surface of the semiconductor substrate. | 05-31-2012 |
20120133684 | DISPLAY DEVICE WITH GRAY SCALE PROCESSING CIRCUIT, AND METHOD OF GRAY SCALE PROCESSING - A display device includes a gray scale controller which adjusts the number of pieces of image data successively displayed at the same brightness level to a predefined value or less when a desired brightness level represented by input image data is equal to or less than a predetermined level. Alternatively the display device may include a gray scale controller which may make the frequencies of selection of an immediately lower display brightness level than a desired level and an immediately higher display brightness level closer to each other when the brightness level represented by the input image data is equal to or less than the predetermined level and other than a plurality of display brightness levels. This frequency control is done to prevent a selected display brightness level from continuing at the same level over a period greater than a predetermined cycle. | 05-31-2012 |
20120119748 | BATTERY VOLTAGE MEASUREMENT SYSTEM AND BATTERY VOLTAGE MEASUREMENT METHOD - The present invention provides a battery voltage measurement system and battery voltage measurement method that may reduce the size of the battery voltage measurement system. A regulator generates a constant voltage based on a battery voltage, and inputs the constant voltage to an analog input terminal of an AID converter. The battery voltage is directly inputted to a reference voltage terminal of the AID converter via a terminal (a pad). The A/D converter uses the battery voltage as a reference voltage, determines the level of the input voltage which is the constant voltage, in respect to the reference voltage, and outputs a conversion result. The conversion results increase with a decrease in the battery voltage. Accordingly, the battery voltage is measured and monitored by a processing section on the basis of the conversion results. | 05-17-2012 |
20120119371 | METHOD OF FABRICATING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE - There is provided a method of fabricating a semiconductor device including: forming an insulating film on a semiconductor substrate; forming a pad electrode on the insulating film; forming a protective film on the pad electrode; forming, on the protective film, a resist equipped with an open portion in a first region corresponding to part of the pad electrode; by using the resist as a mask, etching the protective film and etching the first region of part of the pad electrode to a predetermined depth; etching the protective film on a second region that surrounds the first region of the pad electrode; and removing the resist. | 05-17-2012 |
20120117925 | APPARATUS AND METHOD FOR PACKAGING CHIP COMPONENTS - A chip component packaging arrangement prevents occurrence of defective loading of chip components during a taping process that is carried out to the package chip components. This arrangement has a small size. A cover tape is prepared having a base tape and a plurality of cover film pieces sequentially attached to the base tape. Each cover film piece has an adhesive part. The cover tape extends in a direction intersecting a longitudinal direction of a carrier tape. The carrier tape has a plurality of component receiving parts sequentially formed in its longitudinal direction. The cover tape is pressed to the carrier tape so that one of the cover film pieces is adhered to the carrier tape to seal the corresponding component receiving part. | 05-17-2012 |
20120116710 | MOTION DETECTION DEVICE, ELECTRONIC DEVICE, MOTION DETECTION METHOD, AND PROGRAM STORAGE MEDIUM - A motion detection device includes: an acceleration detection unit, a separating unit, a gravity axis determination unit, and a motion detection unit. The acceleration detection unit detects acceleration components of each axis of a three-dimensional rectangular coordinate system of acceleration acting on the acceleration detection unit and outputs sets of acceleration component data. The separating unit separates the outputted sets of acceleration component data into stationary components and motion components. The gravity axis determination unit determines an axis whose separated stationary component is the largest to be a gravity axis. The motion detection unit detects, if an axis corresponding to a largest motion component showing a largest value of the separated motion components is an axis other than the determined gravity axis, a motion axis of the acceleration detection unit on the basis of the largest motion component. | 05-10-2012 |
20120106808 | FINGERPRINT AUTHENTICATION DEVICE AND COMPUTER READABLE MEDIUM - A fingerprint authentication device includes: a fingerprint acquisition section that acquires fingerprint image data; a fingerprint image correction processing section that corrects a pixel value by using a correction coefficient for making a first pixel value of the brightest pixel in a group of pixels at which an integrated value of a number of pixels at a dark portion side in a histogram becomes a predetermined proportion with respect to an integrated value of a number of all pixels, be a brighter second pixel value; a spectral data generation section that generates a spectral data matrix including directions of ridges of a fingerprint and a frequency of the fingerprint; a registered spectral data matrix archive section that archives a registered spectral data matrix; a fingerprint verification section that verifies the spectral data matrix and the registered spectral data matrix; and an authentication results output section that outputs results of authentication. | 05-03-2012 |
20120099384 | SEMICONDUCTOR DEVICE - A semiconductor memory has main bit lines paralleled by fixed potential lines in an alternating arrangement. Each main bit line is switchably connected to two sub-bit lines. The memory cells connected to one of the two sub-bit lines are placed below the main bit line. The memory cells connected to the other one of the two sub-bit lines are placed below an adjacent fixed potential line. The fixed potential lines prevent parasitic capacitive coupling between the main bit lines and thereby speed up read access to the memory cells without taking up extra layout space. | 04-26-2012 |
20120098547 | SEMICONDUCTOR CIRCUIT, SEMICONDUCTOR DEVICE, METHOD OF DIAGNOSING ABNORMALITY OF WIRE, AND COMPUTER READABLE STORAGE MEDIUM - There is provided a semiconductor circuit including: a selection circuit, to which are connected batteries in series, and which selects any one of the batteries; a difference detecting circuit, to which voltage of a high potential side of the selected battery inputted, and to which voltage of a low potential side of the selected battery is inputted, and which outputs a difference between the voltage at the high-potential side and the voltage at the low-potential side; and a voltage applying unit that applies diagnostic voltage to a wire that is for inputting the high potential voltage to the difference detecting circuit when diagnosing an abnormality of a wire associated with the selected battery if the selected battery is a battery of a highest position in the series or a battery of a lowest position in the series. | 04-26-2012 |
20120092038 | INSPECTION DEVICE AND INSPECTION METHOD - The present invention provides semiconductor integrated circuit, inspection device and inspection method for inspecting whether inspection target is functioning normally regardless to start-up period of a power supply voltage. The inspection device includes a reset control circuit and a tester. When a reset signal is inputted from a power-on reset circuit to a first terminal, the reset control circuit starts output of a reset execution signal having the same level as the reset signal. When a trigger signal is inputted from a control device to the second input terminal, the reset control circuit finishes the output of the reset execution signal and starts output of a release execution signal that has the same level as a reset release signal from the output terminal. The tester determines whether the power-on reset circuit is functioning normally by determining whether signals outputted from the reset control circuit are at predetermined levels. | 04-19-2012 |