Kilopass Technology, Inc. Patent applications |
Patent application number | Title | Published |
20140217484 | ONE-TIME PROGRAMMABLE MEMORY AND METHOD FOR MAKING THE SAME - A one time programmable nonvolatile memory formed from metal-insulator-semiconductor cells. The cells are at the crosspoints of conductive gate lines and intersecting doped semiconductor lines formed in a semiconductor substrate. | 08-07-2014 |
20130161761 | ONE-TIME PROGRAMMABLE MEMORY AND METHOD FOR MAKING THE SAME - A one time programmable nonvolatile memory formed from metal-insulator-semiconductor cells. The cells are at the crosspoints of conductive gate lines and intersecting doped semiconductor lines formed in a semiconductor substrate. | 06-27-2013 |
20110216572 | ELECTRICALLY PROGRAMMABLE FUSE BIT - One-time programmable (OTP) nonvolatile fuse memory cells are disclosed that do not require decoding or addressing for reading their data content. Each fuse memory cell has its content latched at its output and available at all times and can be used, for example, for code storage memories, serial configuration memories, and as individual fuse bits for ID (identification), trimming, and other post-fabrication System-on-Chip (SoC) customization needs. Means are also provided for temporary data storage for design testing, etc. In alternative embodiments, using two differentially programmed fuses in a single memory cell, the selection and programming circuitry are merged. | 09-08-2011 |
20090085127 | NON-VOLATILE SEMICONDUCTOR MEMORY BASED ON ENHANCED GATE OXIDE BREAKDOWN - A semiconductor memory structure based on gate oxide break down is constructed in a deep N-well. Thus, the electrical field over the programmable element during the transient procedure of gate oxide break down can be controlled to achieve the best memory programming results. The conductivity of the programmed memory cell is increased greatly and conductivity variation between the memory cells is reduced. This is achieved by adding a body bias during the programming process. The body here refers to a P-well formed within the deep N-Well. Furthermore, the read voltage offset is reduced greatly with this new memory configuration. These improved programming results will allow faster read speed and lower read voltage. This new structure also reduces current leakage from a memory array during programming. | 04-02-2009 |