INTEGRATED DEVICE TECHNOLOGY, INC. Patent applications |
Patent application number | Title | Published |
20150215006 | APPARATUSES AND RELATED METHODS FOR COMMUNICATION WITH A WIRELESS POWER RECEIVER - A wireless power enabled apparatus may comprise a wireless power receiver that includes a receive coil configured to generate an AC power signal responsive to a wireless power signal, a rectifier including a plurality of switches configured to receive the AC power signal and generate a DC rectified power signal, a regulator operably coupled with the regulator to receive the DC rectified power signal and generate an output power signal, and control logic configured to generate a communication signal responsive to adjusting an input impedance of the regulator. A method of operating a wireless power receiver includes generating a rectified voltage responsive to receiving a wireless power signal, generating an output voltage from the rectified voltage with a voltage regulator, and controlling the voltage regulator during a communication mode of wireless power receiver to modulate a characteristic of the voltage regulator with data for transmission to a wireless power transmitter. | 07-30-2015 |
20150156284 | METHODS AND APPARATUSES FOR A UNIFIED COMPRESSION FRAMEWORK OF BASEBAND SIGNALS - A method and apparatus provides a parameter estimation processor configured to estimate parameters used to compress data for transmission over a serial data link. The parameter estimation processor includes a processor. The processor includes user programmable inputs. The user programmable inputs set an input data packet length, a target compression ratio, and a resampling factor and allow filter parameters to be set. Input data information is received from an input data buffer of a data sample compressor. The processor performs a function that: (a) adjusting a target compression ratio by a first compression ratio to determine a remaining compression ratio when the resampling operation is enabled; (b) estimating a set of compression parameters that are used to achieve the remaining compression ratio, the set of compression parameters includes an attenuation value, filter order, a type of encoding; and (c) sends the set of compression parameters to the data sample compressor. The data sample compressor applies the compression parameters to a packet of input data and outputs a plurality of compressed data words. | 06-04-2015 |
20150035372 | MULTIMODE WIRELESS POWER RECEIVERS AND RELATED METHODS - A wireless power receiver comprises a resonant tank configured to generate an AC power signal responsive to an electromagnetic field, a rectifier configured to receive the AC power signal and generate a DC output power signal, and control logic configured to control the resonant tank to reconfigure and adjust its resonant frequency responsive to a determined transmitter type of a wireless power transmitter. The control logic may operate the wireless power receiver as a multimode receiver having a first mode for a first transmitter type and a second mode for a second transmitter type. The resonant tank may exhibit a different resonant frequency for each of the first mode and the second mode. A method comprises determining a transmitter type for a wireless power transmitter desired to establish a mutual inductance relationship, and adjusting a resonant frequency of a resonant tank of a wireless power receiver. | 02-05-2015 |
20140266449 | METHODS AND APPARATUSES FOR SLEW RATE ENHANCEMENT OF AMPLIFIERS - A circuit is disclosed to enhance slew rate of an amplifier. An amplifier includes an output, a first input, and a second input in a differential pair configuration. A slew rate enhancer includes a first slew rate enhancer and a second slew rate enhancer. The first slew direction enhancer is configured to detect a first slew rate condition in a first direction responsive to the first input and the second input and provide additional current for a first side of the differential pair of the amplifier during the first slew rate condition. The second slew direction enhancer is configured to detect a second slew rate condition in a second direction responsive to the first input and the second input and provide additional current for a second side of the differential pair of the amplifier during the second slew rate condition. | 09-18-2014 |
20140266015 | APPARATUSES AND METHODS FOR OVER-TEMPERATURE PROTECTION OF ENERGY STORAGE DEVICES - A charging system includes a temperature sensor to generate a temperature signal responsive to a temperature of an energy storage device. A circuit temperature sensor generates a circuit temperature signal responsive to a temperature of a semiconductor device. A charge adjuster generates a desired current signal responsive to the temperature signal and the circuit temperature signal. A comparator compares a charge-current level signal to the desired current signal to generate a charge adjustment signal. A charge controller on the semiconductor device generates and adjusts a current of a charging signal for charging the energy storage device responsive to the charge adjustment signal. The charge adjuster may generate a reduction signal when the temperature signal is above a throttle threshold, reduce a digital desired current signal responsive to the reduction signal, and convert the digital desired current signal to the desired current signal as an analog signal. | 09-18-2014 |
20140266010 | APPARATUSES AND RELATED METHODS FOR CHARGING CONTROL OF A SWITCHING VOLTAGE REGULATOR - Charging systems and related methods are disclosed for switching voltage regulators. A charging controller may be configured to generate a control signal indicating a first level of an output current generated by a switching voltage regulator for charging an energy storage device, determine that an output voltage exceeded a predetermined threshold, and generate the control signal indicating a new level of the output current that is reduced from the first level. A method of controlling charging of an energy storage device may comprise monitoring an output voltage charging an energy storage device, comparing a reference signal and a current sense signal to generate a PWM control signal that determines an output current for a switching voltage regulator generating the output voltage, and decrementing the reference signal in response to the output voltage exceeding a predetermined level for a maximum charging voltage for the energy storage device. | 09-18-2014 |
20140265610 | APPARATUSES AND RELATED METHODS FOR MODULATING POWER OF A WIRELESS POWER RECEIVER - A wireless power enabled apparatus may comprise a wireless power receiver that includes a receive coil configured to generate an AC signal responsive an electromagnetic field, a rectifier including a plurality of switches configured to receive the AC signal and generate an output power signal, and control logic configured to control the plurality of switches to cause the rectifier to modulate the output power signal. The control logic may be configured to control the plurality of switches within the rectifier to have an overlap delay that modulates at least one parameter of the wireless power receiver. A method of operating a receiver side of a wireless power transfer system comprises generating an output power signal including a rectified voltage and a rectified current responsive to receiving a wireless power signal, and controlling a rectifier according to at least one mode including a power modulation mode modulating the output power signal. | 09-18-2014 |
20140253256 | MONOLITHIC CLOCK GENERATOR AND TIMING/FREQUENCY REFERENCE - A periodic signal generator includes a resonant LC tank circuit that generates a periodic reference signal at a first frequency at a differential output thereof. A temperature-responsive frequency compensation module is electrically coupled to the differential output of the resonant LC tank circuit. This module includes a temperature dependent voltage control module that generates a temperature dependent control voltage and an array of switchable capacitive modules that is electrically coupled to a first node of the differential output of the resonant LC tank circuit and responsive to the temperature dependent control voltage and a plurality of switching coefficients. The array of switchable capacitive modules includes a fixed capacitor having a first terminal electrically coupled to the first node and a voltage-controlled variable capacitor having a first terminal electrically coupled to the first node. | 09-11-2014 |
20140079037 | TRANSMISSION OF MULTIPROTOCOL DATA IN A DISTRIBUTED ANTENNA SYSTEM - In a distributed antenna system (DAS) and a local area network (LAN), a common communication infrastructure distributes data from radio-based and Internet-based sources. A radio equipment (RE) of the DAS interfaces to a LAN segment. For the downlink, a gateway maps radio signal data from a radio equipment controller (REC) and data packets from a switch to mixed-data frames using a radio data interface protocol for transmission in the DAS. At the RE, the signal data and data packets are retrieved from the mixed-data frames and provided to the air interface and LAN segment, respectively. For the uplink from the RE, the radio signal data from the air interface and the data packets from the LAN segment are mapped to mixed-data frames and transmitted to the gateway. The gateway retrieves the signal samples and data packets from the mixed-data frames for transfer to the REC and switch, respectively. | 03-20-2014 |
20140027890 | Low Stress Package For an Integrated Circuit - A package that electrically connects an integrated circuit to a printed circuit board includes a frame and a package body that encases a portion of the frame and the integrated circuit. The frame includes a mounting region that is connected to the printed circuit board, and a cantilevering region that cantilevers away from the mounting region. The cantilevering region retains the integrated circuit in a flexible fashion. | 01-30-2014 |
20130278234 | APPARATUSES AND SYSTEM AND METHOD FOR AUTO-CONFIGURATION OF A POWER CONTROL SYSTEM - Power control systems and power control devices may include a power control chip having a power control module configured to generate a power stage control signal, and an external power stage having a timing control module. The timing control module may be configured to receive the power stage control signal and generate a timing control signal controlling at least one switch to regulate an output voltage of the external power stage. The power control device further includes an auto-configuration module configured to communicate with the external power stage and request auto-configuration information from the external power stage. A related method of auto-configuring a power control system includes communicating auto-configuration information between at least one external power stage of a power control system and a power control chip, and configuring a setting of the at least one external power stage of the power control system based on the auto-configuration information. | 10-24-2013 |
20130265022 | APPARATUSES AND SYSTEM HAVING SEPARATE POWER CONTROL AND TIMING CONTROL OF A POWER CONTROL SYSTEM AND RELATED METHOD - Power control systems and power control devices may include a power control chip having a power control module configured to generate a power stage control signal, and at least one power stage having a timing control module that is physically separate from the power control module. The timing control module may be configured to receive the power stage control signal and generate a timing control signal controlling at least one switch to regulate an output voltage of the at least one power stage. A related method may include generating power stage control information indicating an offset between an output voltage and a desired regulated output voltage, transmitting the power stage control information between modules that are physically separate, and timing signals for controlling a switching converter to regulate the output voltage. A related method of auto-configuring a power control system is also disclosed. | 10-10-2013 |
20130260676 | APPARATUS, SYSTEM, AND METHOD FOR BACK-CHANNEL COMMUNICATION IN AN INDUCTIVE WIRELESS POWER TRANSFER SYSTEM - An inductive wireless power transfer device comprises a transmitter that comprises a transmit coil configured to generate a wireless power signal to a coupling region in response to an input voltage, and a modulator configured to modulate the wireless power signal and encode data with the wireless power signal to establish a back-channel communication link from the transmitter to a receiver. An inductive wireless power receiving device comprises a receiver that comprises a receive coil configured to generate a time varying signal in response to receiving a modulated wireless power signal from a transmitter in a coupling region, and a demodulator configured to demodulate the modulated wireless power signal from an established back-channel communication link from the transmitter to a receiver. Related inductive wireless power transfer systems and methods for back-channel communication from the transmitter to the receiver of an inductive wireless power transfer system are disclosed. | 10-03-2013 |
20130257402 | APPARATUSES AND METHODS RESPONSIVE TO OUTPUT VARIATIONS IN VOLTAGE REGULATORS - A voltage regulator includes an amplifier to generate a difference voltage responsive to a comparison of a reference voltage and a feedback voltage. An output driver is coupled to the amplifier and drives a regulated output voltage responsive to the difference voltage. An impedance circuit is coupled between the output driver and a low power source and establishes the feedback voltage responsive to a current through the impedance circuit. A variation detector is operably coupled between the regulated output voltage and the difference voltage and is configured to modify the difference voltage. In some embodiments, the difference voltage is modified responsive to a rapid change of the regulated output voltage capacitively coupled to the variation detector. In other embodiments, the difference voltage is modified responsive to a rapid change of the feedback voltage capacitively coupled to the variation detector. | 10-03-2013 |
20130257360 | APPARATUSES HAVING DIFFERENT MODES OF OPERATION FOR INDUCTIVE WIRELESS POWER TRANSFER AND RELATED METHOD - An inductive wireless power enabled device may comprise a transceiver including a plurality of switches coupled with a resonant tank, and control logic configured to drive the plurality of switches to operate the resonant tank in one of a transmit mode and a receive mode. Another inductive wireless power enabled device may comprises a transceiver including a plurality of switches coupled with a resonant tank. The transceiver may be configured to both transmit a wireless power signal through the resonant tank and generate power from an incoming wireless power signal through the resonant tank depending on a current operational mode. A related method for operating a wireless power enabled device according to either a transmit mode or a receive mode is also disclosed. | 10-03-2013 |
20130257168 | APPARATUS, SYSTEM, AND METHOD FOR DETECTING A FOREIGN OBJECT IN AN INDUCTIVE WIRELESS POWER TRANSFER SYSTEM BASED ON INPUT POWER - An inductive wireless power transfer system comprises a transmitter configured to generate an electromagnetic field to a coupling region for providing energy transfer to a wireless power receiving apparatus. The transmitter includes control logic configured to determine a power component of the transmitter, and determine a presence of a foreign object within the coupling region in response to a comparison of the power component and a desired threshold for the power component. Related inductive methods for detecting a foreign object in an inductive wireless power transfer coupling region of an inductive wireless power transfer system and operating a sleep mode of a wireless power transmitter are disclosed. | 10-03-2013 |
20130257167 | APPARATUSES, SYSTEMS, AND METHODS FOR POWER TRANSFER ADJUSTMENT IN WIRELESS POWER TRANSFER SYSTEMS - A wireless power-transfer system includes a power-transmitting device and a power-receiving device. The power-transmitting device includes, a frequency generator for generating a power-transmit frequency and a transmit coil for generating a near-field electromagnetic radiation responsive to the power-transmit frequency. The power-receiving device, includes a receive resonance circuit that generates a receive resonance frequency and includes a receive coil for receiving the near-field electromagnetic radiation when within a coupling region of the transmit coil and a receive capacitor in combination with the receive coil. The rectifier converts the receive resonance signal to a rectified signal. The signal sensor senses at least one of a voltage or a current on the rectified signal to generate a power indicator signal. The receive impedance adjuster modifies a resonant frequency of the receive resonance circuit responsive to the power indicator signal by selectively modifying an impedance of the receive impedance adjuster. | 10-03-2013 |
20130257165 | APPARATUS, SYSTEM, AND METHOD FOR DETECTING A FOREIGN OBJECT IN AN INDUCTIVE WIRELESS POWER TRANSFER SYSTEM VIA COUPLING COEFFICIENT MEASUREMENT - An inductive wireless power device comprises a transmitter configured to generate an electromagnetic field to a coupling region for wireless power transfer to a receiver, and control logic configured to determine a coupling coefficient of the wireless power transfer when the receiver is within the coupling region. The control logic also determines a presence of a foreign object within the coupling region responsive to a comparison of the determined coupling coefficient and an expected coupling coefficient for the wireless power transfer. An inductive wireless power device comprises a receiver configured to couple with an electromagnetic field in a coupling region for inductive wireless power transfer from a transmitter. The receiver is configured to alter a wireless power transfer characteristic of the transmitter for a determination of a presence of a foreign object within the coupling region responsive to a determination of a coupling coefficient of the wireless power transfer. | 10-03-2013 |
20130241643 | SYSTEMS AND METHODS FOR ADAPTIVE EQUALIZATION CONTROL FOR HIGH-SPEED WIRELINE COMMUNICATIONS - Methods and systems for conditioning wireline communications to remove intersymbol interference are provided that used adaptive equalization. The method and systems include using a digital finite state machine to control two feedback loops that adjust the gain and power of the input signal relative to a supplied reference. The eye height of the input signal is conditioned by a gain feedback loop so that signal equalization can be performed in a known state. The digital finite state machine allows the loops to be flexibly run in sequence or concurrently. The adaptation functions can be shut off when adequate signal equalization has been achieve, thus saving power. | 09-19-2013 |
20130221756 | APPARATUSES, SYSTEMS, AND METHODS FOR A MONOTONIC TRANSFER FUNCTION IN WIRELESS POWER TRANSFER SYSTEMS - A wireless power-transfer system includes a power-transmitting device and a power-receiving device. A frequency generator generates a power-transmit frequency to stimulate transmit coil and transmit resonance adjuster, which generate a near-field electromagnetic radiation at an adjustable coupling frequency. The power-receiving device includes a receive coil and a receive resonance adjuster for receiving the near-field electromagnetic radiation when the receive coil is within a coupling region of the transmit coil. The receive resonance frequency may be modified by the receive resonance adjuster. In the wireless power-transfer system, one or both of the transmit resonance adjuster and the receive resonance adjuster is configured to adjust its corresponding frequency to be sufficiently less than the power-transmit frequency such that a monotonic transfer function is developed between the power-transmit frequency and the receive resonance frequency. | 08-29-2013 |
20130201031 | SYSTEMS AND METHODS FOR COMMUNICATION WITH A SMART POWER METER OVER OPTICAL FIBER - A system and method for facilitating smart power meter monitoring are provided. The system for facilitating smart power meter monitoring includes a standards-based frame detector, a CDR, at least one | 08-08-2013 |
20130094598 | APPARATUS, SYSTEM, AND METHOD FOR DETECTING A FOREIGN OBJECT IN AN INDUCTIVE WIRELESS POWER TRANSFER SYSTEM - An inductive wireless power transfer system comprises a transmitter configured to generate an electromagnetic field to a coupling region in response to an input signal. The inductive wireless power transfer control logic is configured to determine an input power of the input signal. The control logic is configured to determine a presence of a foreign object within the coupling region in response to a comparison of the input power and an output power of an output signal of a receiver within the coupling region. Related inductive wireless power transfer systems and methods for detecting a foreign object in an inductive wireless power transfer coupling region of an inductive wireless power transfer system are disclosed. | 04-18-2013 |
20130076301 | APPARATUS AND METHOD FOR A SWITCHING POWER CONVERTER - A charging converter includes a plurality of switches configured to switchably operate to either step up an input voltage or step down the input voltage and generate a charging voltage on a second terminal to charge to a rechargeable storage unit, and control logic configured to operate the plurality of switches in one of a step up mode and a step down mode based on a determination of a voltage level of the input voltage relative to the desired charging voltage. A method includes determining a desired charging voltage to charge a rechargeable storage unit, switchably controlling a charging converter to step up the input voltage if an input voltage is lower than the desired charging voltage to generate a charging voltage, and switchably controlling the charging converter to step down the input voltage if the input voltage is higher than the desired charging voltage to generate the charging voltage. | 03-28-2013 |
20120302194 | Method and Apparatus for An Equalized On-Die Termination (ODT) Circuit - A method and apparatus for an equalized On-Die Termination (ODT) circuit uses timed switching to reduce receiver power consumption. | 11-29-2012 |
20120299617 | Method and Apparatus for A Low Power AC On-Die-Termination (ODT) Circuit - A method and apparatus for A Low Power AC On-Die-Termination (ODT) Circuit using active components reduces receiver power consumption. | 11-29-2012 |
20120250740 | OFDM SIGNAL PROCESSING IN A BASE TRANSCEIVER SYSTEM - A method and apparatus provides OFDM signal compression for transfer over serial data links in a base transceiver system (BTS) of a wireless communication network. For the uplink, an RF unit of the BTS applies OFDM cyclic prefix removal and OFDM frequency transformation of the baseband signal samples followed by frequency domain compression of the baseband signal samples, resulting from analog to digital conversion of received analog signals followed by digital downconversion, forming compressed coefficients. After transfer over the serial data link, the baseband processor applies frequency domain decompression to the compressed coefficients prior to further signal processing. For the downlink, the RF unit performs frequency domain decompression of the compressed coefficients and applies OFDM inverse frequency transformation of the decompressed coefficients and OFDM cyclic prefix insertion prior to digital upconversion and digital to analog conversion, generating the analog signal for transmission over the antenna. | 10-04-2012 |
20120242309 | Autonomous Controlled Headroom Low Dropout Regulator For Single Inductor Multiple Output Power Supply - A controlled headroom low dropout regulator (CHLDO) having an LDO with an input voltage provided by a capacitor. An incremental voltage is added to an output voltage of the LDO to create a reference voltage. The reference voltage is compared to the input voltage to determine when to couple/de-couple the capacitor with a current source. If the capacitor is coupled to the current source, the capacitor will charge only if the voltage driven by the current source exceeds the input voltage provided by the capacitor. When the input voltage developed on the capacitor exceeds the reference voltage, the capacitor is automatically de-coupled from the current source. Multiple CHLDOs can be charged from a single current source, wherein charging automatically proceeds from the lowest voltage CHLDO to the highest voltage CHLDO. | 09-27-2012 |
20120235846 | APPARATUSES AND METHODS FOR REDUCING ERRORS IN ANALOG TO DIGITAL CONVERTERS - Successive approximation Analog-to-digital converters (ADCs) and related methods are disclosed. A successive approximation ADC includes a comparator with a comparator output and inputs coupled to a common model signal and a compare input. Control logic generates one or more control signals responsive to the comparator output. A capacitor array includes first sides of capacitors operably coupled to an array output. The capacitor arrays selectively couples each of second sides of the capacitors to an analog input signal and one or more input reference signals responsive to the one or more control signals. A voltage limiter is operably coupled between the array output and the compare input of the comparator and limits a voltage on the compare input to within a predefined range relative to the array output. The successive approximation ADC may also be configured differentially with a second comparator and a second voltage limiter. | 09-20-2012 |
20120223647 | APPARATUSES AND METHODS FOR REDUCING POWER IN DRIVING DISPLAY PANELS - Energy sharing circuits and related methods are disclosed herein. A high voltage can be selectively coupled to a first source line and a low voltage can be selectively coupled to a second source line during a first time period. During a subsequent time period, a first coupling switch is activated to inductively couple the first source line to the second source line and diode block the second source line from the first source line. During a subsequent time period, the low voltage is selectively coupled to the first source line and the high voltage is selectively coupled to the second source line. During a subsequent time period, a second coupling switch is activated to inductively couple the second source line to the first source line and diode block the first source line from the second source line. | 09-06-2012 |
20120176966 | FREQUENCY DOMAIN COMPRESSION IN A BASE TRANSCEIVER SYSTEM - A method and apparatus provide signal compression for transfer over serial data links in a base transceiver system (BTS) of a wireless communication network. For the uplink, an RF unit of the BTS applies frequency domain compression of baseband signal samples, resulting from analog to digital conversion of received analog signals followed by digital downconversion, forming compressed coefficients. After transfer over the serial data link, the baseband processor then applies frequency domain decompression to the compressed coefficients prior to normal signal processing. For the downlink, the baseband processor applies frequency domain compression of baseband signal samples and transfers the compressed coefficients to the RF unit. The RF unit applies frequency domain decompression to the compressed coefficients prior to digital upconversion and digital to analog conversion, generating the analog signal for transmission over the antenna. This abstract does not limit the scope of the invention as described in the claims. | 07-12-2012 |
20120176827 | CONTROLLER FOR SECONDARY SIDE CONTROL OF A SWITCH, POWER CONVERTER, AND RELATED SYNCHRONOUS RECTIFICATION CONTROL METHOD - A controller, power converter, and a related method for secondary side control of a switch are disclosed herein. An embodiment of the present invention includes a controller. The controller comprises a drain to source voltage (V | 07-12-2012 |
20120146688 | VOLTAGE LEVEL SHIFTING APPARATUSES AND METHODS - Level shifting circuits and related methods are disclosed herein. The level shifting circuit includes a cross-coupled pull-up circuit coupled to a higher supply voltage, an output signal, and an inverted output signal. An input signal transitions between a ground and a lower supply voltage and an inverted input signal transitions in a direction opposite from the input signal between the ground and the lower supply voltage. A first n-channel transistor has a gate coupled to the lower supply voltage, a drain coupled to the output signal, and a source coupled to the inverted input signal. A second n-channel transistor has a gate coupled to the lower supply voltage, a drain coupled to the inverted output signal, and a source coupled to the input signal. The level shifting circuit may be included in an IC with core logic in a first voltage domain and input/output logic in a second voltage domain. | 06-14-2012 |
20120133634 | APPARATUS, SYSTEM, AND METHOD FOR GENERATING A LOW POWER SIGNAL WITH AN OPERATIONAL AMPLIFIER - An amplifier, electronic display system, and a related method for generating a low power signal with an operational amplifier are disclosed herein. An embodiment of the present invention includes an amplifier, comprising an operational amplifier and a voltage converter. The operational amplifier includes an inverting input, a non-inverting input, an output, a first power supply input and a second power supply input, and is configured to generate an output signal in response to an input signal. The voltage is operably coupled with the first power supply input of the operating amplifier, and is configured to receive a first supply voltage and generate a second supply voltage to the first power supply input of the operational amplifier. The voltage of the second supply voltage is relatively closer to the expected operating voltage range of the output signal than is the first supply voltage. | 05-31-2012 |
20120038398 | METHODS AND APPARATUSES FOR CLOCK DOMAIN CROSSING - Clock-domain-crossing systems and methods include an integrator that accumulates input samples over multiple clock cycles in a first clock domain to generate an accumulation result. Clock-domain-crossing circuitry samples the accumulation result in the first clock domain after each of a repeating accumulation count to generate a first domain accumulation. The first domain accumulation is sampled in a second clock domain after a time delay to generate a second domain accumulation. The time delay ensures proper setup and hold time parameters for the second clock domain relative to the first clock domain. A differentiator generates output information in the second clock domain by delaying the second domain accumulation and subtracting the delayed second domain accumulation from the second domain accumulation. The systems and methods preserve temporal characteristics of the input information in the first clock domain when it is transferred to the second clock domain as the output information. | 02-16-2012 |
20120001672 | Apparatuses and methods for a voltage level shifting - Level shifting circuits and a related method are disclosed herein. An embodiment of the present invention includes a voltage level shifter, comprising a first pull up transistor coupled to a high voltage signal and a first pull down transistor coupled between the first pull up transistor and a low voltage signal and controlled by an input signal. The voltage level shifter further includes a first bias transistor serially coupled between the first pull up transistor and the first bias transistor. A gate of the first bias transistor is coupled with a bias voltage signal. The voltage level shifter further includes a first additional pull up path coupled with the high voltage signal and a first node between the first pull up transistor and the first pull down transistor, and an output signal associated with the first node. The output signal is a level shifted voltage responsive to the input signal. | 01-05-2012 |
20110231463 | METHODS AND APPARATUSES FOR FLEXIBLE AND HIGH PERFORMANCE DIGITAL SIGNAL PROCESSING - A Signal Processing Engine (SPE) includes circuitry for generating a selectable forward tap and a selectable reverse tap from a forward delay chain and a reverse delay chain, respectively. An add/subtract unit arithmetically combines the selectable forward tap and the selectable reverse tap to generate an intermediate output. A multiplier combines the intermediate output and a coefficient output from a circular coefficient buffer to generate a multiply result. Another adder/subtractor combines the multiply result with a second term including a processed input or an accumulator feedback by bypassing, adding, or subtracting the second term with the multiply result to generate an accumulator output. The accumulator output may be delayed a programmable number of clock cycles to generate a processed output. In some embodiments, the SPE is coupled to programmable logic blocks forming a programmable logic array through a programmable SPE routing block. | 09-22-2011 |
20110225222 | METHODS AND APPARATUSES FOR CORDIC PROCESSING - A CORDIC engine includes an N-stage CORDIC processor for performing N micro-iterations of a CORDIC algorithm and generating a 3-vector CORDIC output responsive to a 3-vector CORDIC input. A counter counts a number of M macro-iterations for the CORDIC algorithm and indicates a start of the cycle iterations. A multiplexer selects an input to the N-stage CORDIC processor as the 3-vector CORDIC input at the start of the cycle iterations or the 3-vector CORDIC output at other times. The CORDIC algorithm is complete after N*M clock cycles by generating N micro-iterations for each of the M macro-iterations. In some embodiments, the CORDIC engine is coupled to programmable logic blocks as part of a programmable logic array. | 09-15-2011 |
20110210879 | APPARATUSES AND METHODS FOR PHYSICAL LAYOUTS OF ANALOG-TO-DIGITAL CONVERTERS - Physical layouts of integrated circuits are provided, which may include an analog-to-digital converter including a plurality of comparators. Individual transistors of each comparator of the plurality are arranged in a one-dimensional row in a first direction. Neighboring comparators of the plurality of comparators are positioned relative each other in an abutting configuration in a second direction orthogonal to the first direction. The plurality of comparators may include multiple, inter-coupled, outputs. Such an ADC may be called a Benorion Analog-to-Digital Converter. A method for fabricating an integrated circuit is also provided. The method comprises arranging transistors of a first comparator in a one-dimensional row in a first direction, arranging transistors of at least one additional comparator in the one-dimensional row in the first direction, and arranging transistors of the first comparator and the at least one additional comparator relative to each other in a second direction orthogonal to the first direction. | 09-01-2011 |
20110210878 | APPARATUSES AND METHODS FOR MULTIPLE-OUTPUT COMPARATORS AND ANALOG-TO-DIGITAL CONVERTERS - An analog-to-digital converter with comparators with multiple, inter-coupled, outputs is provided, which may be also called a Benorion Analog-to-Digital Converter (ADC) or a Benorion Converter. The analog-to-digital converter includes a plurality of comparators operably coupled for receiving an analog input signal and configured for comparing the analog input signal with a plurality of voltage reference signals. Each comparator of the plurality is configured for generating a plurality of comparator outputs comprising a primary comparator output, and at least one additional comparator output selected from the group consisting of positive comparator outputs and negative comparator. The analog-to-digital converter further includes a plurality of composite outputs, each composite output of the plurality comprising a combination of the primary comparator output from a corresponding comparator of the plurality and at least one additional comparator output from at least one additional comparator of the plurality of comparators. Other comparators and methods are provided. | 09-01-2011 |
20110198931 | SYSTEMS, DEVICES, AND METHODS FOR PROVIDING BACKUP POWER TO A LOAD - Systems, devices, and methods for providing backup power to a load are disclosed. A power converter may comprise a capacitor array comprising a plurality of capacitors and configured to store a charge from an input during a charge mode of operation and provide a charge to an output during a discharge mode of operation. Further, the power converter may comprise a controller configured to selectively couple the capacitor array to the input during a portion of the charge mode of operation and selectively couple the capacitor array to the output during a portion of the discharge mode of operation. | 08-18-2011 |
20110170619 | High Speed Switch With Data Converter Physical Ports And Processing Unit - An integrated circuit chip implements a high-speed switch that includes: a switch fabric; control logic that controls the transmission of digital signals through the switch fabric; a transceiver block comprising one or more transceivers, each transmitting digital signals between the control logic and a corresponding external device; a data converter physical interface comprising one or more data converters, each performing a conversion between analog and digital signals, wherein digital signals associated with the one or more data converters are routed through the switch fabric; and a signal processing engine coupled to the control logic, wherein the signal processing engine performs on-chip processing of digital signals received from the transceiver block and the data converter physical interface. | 07-14-2011 |
20110170577 | High Speed Switch With Data Converter Physical Ports - A high-speed switch that includes a switch fabric, and both high-speed serial ports and data converter physical ports. A first set of data converter physical ports may perform analog-to-digital conversions, such that an external analog signal may be converted to a digital input signal on the switch. The converted digital input signal may then be routed through the switch fabric in accordance with a serial data protocol. A second set of data converter physical ports may perform digital-to-analog conversions, such that an internal digital signal received from the switch fabric may be converted to an analog output signal on the switch. The converted analog output signal may then be transmitted to an external destination in accordance with a serial data protocol. | 07-14-2011 |
20110169585 | Monolithic Clock Generator and Timing/Frequency Reference - In various embodiments, the invention provides a clock generator and/or a timing and frequency reference, with multiple operating modes, such power conservation, clock, reference, and pulsed modes. The various apparatus embodiments include a resonator adapted to provide a first signal having a resonant frequency; an amplifier; a temperature compensator adapted to modify the resonant frequency in response to temperature; and a process variation compensator adapted to modify the resonant frequency in response to fabrication process variation. In addition, the various embodiments may also include a frequency divider adapted to divide the first signal having the resonant frequency into a plurality of second signals having a corresponding plurality of frequencies substantially equal to or lower than the resonant frequency; and a frequency selector adapted to provide an output signal from the plurality of second signals. The output signal may be provided in any of various forms, such as differential or single-ended, and substantially square-wave or sinusoidal. | 07-14-2011 |
20110148675 | Analog/Digital Or Digital/Analog Conversion System Having Improved Linearity - A digital-to-analog converter (DAC) circuit includes a least significant bit (LSB) set of capacitors, each commonly coupled to an LSB node, and a most significant bit (MSB) set of capacitors, each coupled to an MSB node. A section-coupling capacitor couples the LSB and MSB nodes. The LSB node exhibits a parasitic capacitance, which tends to introduce a jump error voltage. Digital input signals are applied to the LSB and MSB capacitors, and in response, an analog output signal is developed on the MSB node. A compensation capacitor coupled to the MSB node has a compensation capacitance selected to offset the jump error voltage introduced by the parasitic capacitance. The compensation capacitor is enabled when all of the LSB capacitors are coupled to digital input signals having a logic ‘0’ state. Otherwise, the compensation capacitor is disabled (e.g., left in a floating state). | 06-23-2011 |
20110115541 | APPARATUSES AND METHODS FOR A LEVEL SHIFTER WITH REDUCED SHOOT-THROUGH CURRENT - A level shifting circuit with reduced shoot-through current includes an output circuit comprising high-voltage devices with a pull up circuit configured for pulling up a voltage on an output signal to a high voltage responsive to a high-side control signal. The output circuit may also include a pull down circuit configured for pulling down the voltage on the output signal to a low voltage in responsive to a low-side control signal. The level shifting circuit can also include a high-side inverting buffer operably coupled between an edge-controlled signal and the high-side control signal, and a low-side buffer configured for driving the low-side control signal responsive to an input signal. The level shifting circuit may also include an edge-control buffer operably coupled between the input signal and the high-side inverting buffer and configured to generate the edge-controlled signal with a slow rise time relative to a fall time. | 05-19-2011 |
20110098977 | HIGH SPEED CHIP SCREENING METHOD USING DELAY LOCKED LOOP - A voltage controlled delay line (VCDL) for measuring the maximum speed of a chip includes a first input configured to receive a reference clock signal, a first output configured to output an output clock signal, and a second input configured to receive a phase error signal representing a phase delay between the reference and output clock signals. A register stores a delay code applied by the VCDL to the reference clock signal to delay the reference clock signal to generate the output clock signal. The delay code is adjusted according to the phase error signal until the phase delay is equal to a predetermined value. A second output is coupled to an interface that reads the delay code from the register and outputs the delay code to automated testing equipment when the phase delay is equal to the predetermined value. The outputted delay code corresponds to the maximum chip speed. | 04-28-2011 |
20110078525 | Method and Apparatus of ATE IC Scan Test Using FPGA-Based System - An apparatus and a method for enhancing the use of automated test equipment (ATE), are presented. The apparatus comprises a test load board that mounts a plurality of devices to be tested (DUTs), and a daughter card communicating with the test board and the ATE, testing each of the plurality of devices, and providing test results to the ATE. The method comprises mounting a plurality of devices to be tested on the test load board, using the daughter card to communicate with the test board and the ATE, and using the daughter card for testing each of the plurality of DUTs, providing test results to the ATE. Also provided is a system to perform automated tests of integrated chips, comprising an ATE scan test unit, an off-load tester resource coupled to the ATE scan test unit, a processor executing commands to control the ATE unit and the off-load tester resource. | 03-31-2011 |
20110063764 | APPARATUSES AND METHODS FOR A SCR-BASED CLAMPED ELECTROSTATIC DISCHARGE PROTECTION DEVICE - A SCR-based based electrostatic discharge protection device with a shunt path is provided. The shunt path operates at a low resistance when an enabling signal of the shunt path is asserted and a high resistance when the enabling signal is negated. The shunt path connects the cathode and the gate of the silicon-controlled rectifier, and provides a conductive path for displacement current from a parasitic capacitance when the shunt path is enabled, such as when power is provided to the device, and further allows the SCR to enter a low-resistance state when the shunt path is not enabled, such as when power is not provided to the device. A threshold trigger circuit is operably coupled between the anode and the cathode of the silicon-controlled rectifier and is configured to provide a current path when the anode voltage reaches a predetermined value lower than a breakdown voltage of the silicon-controlled rectifier. | 03-17-2011 |
20110012574 | INTERLEAVED/ALL-PHASE MODE SWITCHED PWM SYSTEM - A multi-phase power switching converter having first and second states includes a pulse width modulator having an output, a converter output providing an output signal, and a plurality of drivers, each having an output electrically coupled to the converter output and an input. When the converter is in the first state where a duty cycle of the converter is less than or equal to 100 divided by the number of drivers, each of the driver inputs is configured to be sequentially electrically coupled to the pulse width modulator output. When the converter is in the second state where the duty cycle of the converter is greater than 100 divided by the number of drivers, each of the driver inputs is simultaneously electrically coupled to the pulse width modulator output. | 01-20-2011 |
20100327981 | Charge Pump Linearization Technique For Delta-Sigma Fractional-N Synthesizers - A delta-sigma fractional-N frequency synthesizer having a charge pump with error canceling circuitry eliminates a non-linear term from the charge pump transfer function. The charge pump includes a matched pair of charging current sources, each supplying a first current I | 12-30-2010 |
20100321074 | METHODS AND APPARATUSES FOR INCREMENTAL BANDWIDTH CHANGES RESPONSIVE TO FREQUENCY CHANGES OF A PHASE-LOCKED LOOP - In a phase-locked loop, a desired change in frequency is indicated. The phase-locked loop locks to the new frequency and a loop bandwidth of the phase-locked loop is changed. In changing the loop bandwidth, a frequency adjustment signal to a voltage-controlled oscillator may include a voltage spike. The voltage spike is reduced by detecting a lock when the reference clock and a feedback clock reach a same frequency, then waiting for a time delay after the detecting the lock, and adjusting a current level of a charge pump pulse by an incremental amount to achieve a fractional portion of a new loop bandwidth. The charge pump pulse is filtered to generate the frequency adjustment signal and the frequency spike reduction process is repeated until the new loop bandwidth is achieved. | 12-23-2010 |
20100296615 | DYNAMIC PHASE TRACKING USING EDGE DETECTION - Methods and apparatus of phase tracking are described. Decisions regarding phase location of an oversampled portion of a data signal are based on the content of the data signal. In one example, a phase decision threshold is dynamically variable based on whether a predetermined number of edges is detected in the data signal. | 11-25-2010 |
20100271854 | Ternary Content Addressable Memory Having Reduced Leakage Effects - A column of ternary content addressable memory (TCAM) cells includes a bit line pair that is twisted at a location at or near the center of the column. Data is written to (and read from) TCAM cells located above the twist location with a first bit line polarity. Data is written to (and read from) TCAM cells located below the twist location with a second bit line polarity, opposite the first bit line polarity. As a result, read leakage currents introduced by TCAM cells storing ‘Don't Care’ values are reduced. | 10-28-2010 |
20100232195 | Content Addressable Memory (CAM) Array Capable Of Implementing Read Or Write Operations During Search Operations - A read operation and a search operation are performed during the same cycle within a CAM system including a CAM array by: (1) forcing a non-matching condition to exist in the row of the CAM array selected for the read operation, (2) comparing the read data value with the search data value outside of the CAM array to determine whether a match exists, and (3) prioritizing the results of the search operation performed within the CAM array and the results of the comparison performed outside of the CAM array to provide a final search result. | 09-16-2010 |
20100232194 | Content Addressable Memory Having Bidirectional Lines That Support Passing Read/Write Data And Search Data - A CAM column structure includes an interface that drives search data to a plurality of CAM cells via a search line pair. The CAM cells are divided into sections, each section including: a set of CAM cells, a bit line pair coupled to the set of CAM cells, a sense amplifier coupled to the bit line pair, a tri-state read buffer configured to drive read data from the sense amplifier to the search line pair, and a pair of tri-state write buffers configured to drive write data from the search line pair to the bit line pair. In one embodiment, the pair of tri-state write buffers is replaced by a pair of switches that couple the search line pair to the sense amplifier. The search line pair may be segmented by tri-state buffers, which are controlled to drive the search, read and write data along the search line pair. | 09-16-2010 |
20100046265 | Separate CAM Core Power Supply For Power Saving - A CAM system includes an integrated circuit chip having: logic & control circuitry, a CAM cell array, read/write access circuitry that performs read and write accesses to the CAM cell array, comparison access circuitry that performs comparison operations to the CAM cell array, a first voltage supply pad coupled to the read/write access circuitry; and a second voltage supply pad coupled to the comparison access circuitry. A first voltage supply, external to the integrated circuit chip, provides a first supply voltage to the first voltage supply pad, wherein the logic & control circuitry is powered by the first supply voltage. A second voltage supply, external to the integrated circuit chip, provides a second supply voltage to the second voltage supply pad, wherein at least a portion of the comparison access circuitry is powered by the second supply voltage, wherein the second supply voltage is less than the first supply voltage. | 02-25-2010 |
20100007373 | IMPEDANCE MATCHING LOGIC - An impedance matching logic generates code values that define pull-up and pull-down transistors to be enabled with output buffers. The output buffers store the code values using a two-stage latch configuration, such that updated code values are always stored within the output buffer, even if the output buffer is driving an output signal when the updated code values are received. The impedance matching logic uses previously determined code values to shorten the time required to calculate updated code values. The impedance matching logic may be operated in response to a clock signal having a frequency lower than the frequency of the output clock signal used to control the output buffers. The impedance matching logic may adjust the code values by certain percentages using a multiplication function, thereby allowing for design fine tuning (e.g., due to layout mismatch). | 01-14-2010 |
20090321905 | Multi-Package Ball Grid Array - A multi-package module that includes a multi-layer interconnect structure, a housing structure attached to the multi-layer interconnect structure, and a plurality of integrated circuit packages inserted into slots in the housing structure, and placed into contact with the multi-layer interconnect structure. The integrated circuit packages can be removed from the slots in the housing structure, thereby enabling testing and/or replacement of the integrated circuit packages. | 12-31-2009 |
20090256600 | INPUT CLOCK DETECTION CIRCUIT FOR POWERING DOWN A PLL-BASED SYSTEM - An apparatus is provided for detecting the loss of an input clock signal for a phase-locked loop (PLL). The apparatus includes a time delay circuit, a first frequency divider and a digital logic circuit. The time delay circuit receives the input clock signal and outputs a first time-delayed clock signal. The first frequency divider receives an input signal from an internal clock of the PLL and outputs a clock signal having the same frequency or a lower frequency than that of the time-delayed clock signal. The digital logic circuit that receives the first frequency divider output signal and the first time-delayed clock signal and outputs a signal indicating the loss of the input clock signal if there is no first time-delayed clock signal for a cycle of the first frequency divider output signal. | 10-15-2009 |
20090238184 | CONTENT DRIVEN PACKET SWITCH - A packet switch routes data packets based on both packet headers and data payloads in the data packets. The packet switch receives data packets, identifies a destination port of the packet switch for each data packet based on a packet header of the data packet, and routes the data packet to the destination port. Additionally, the packet switch selects data packets among the data packets received by the packet switch based on the data payloads of the received data packets, identifies a trace port of the packet switch for each selected data packet, and routes the selected data packet to the trace port. | 09-24-2009 |
20090109583 | ESD PROTECTION CIRCUIT FOR INSIDE A POWER PAD OR INPUT/OUTPUT PAD - An electrostatic discharge (ESD) protection circuit configured completely inside one of a power pad and an I/O pad of an electronic circuit, the ESD protection circuit comprising an electrostatic discharge (ESD) circuit that, when activated, discharges an ESD from a first voltage bus to a second voltage bus. The second voltage bus is at a lower electrical potential than the first voltage bus. An ESD discharge control circuit in electrical connection with the ESD discharge circuit that controls the activation of the ESD discharge circuit and including an NMOS transistor and an electrical node. The NMOS transistor regulating a rate of voltage decay of the electrical node from a predetermined high voltage level to a lower voltage level, the regulation of the rate of voltage decay of the electrical node is non-linear. The activation of the ESD discharge circuit determined by the rate of voltage decay of the electrical node. | 04-30-2009 |
20090102513 | Low Power Output Driver - A low power output driver includes one of a regulated reduced voltage source that receives a supply voltage and outputs a regulated reduced voltage that is a lower voltage than the supply voltage. The driver also includes a first driver input that receives a first logic signal, a second driver input that receives a second logic signal, a first driver output that outputs a first output signal and a second driver output that outputs a second output signal. The driver includes first, second, third and fourth n-type metal oxide semiconductor (NMOS) that are cross-connected between the reduced voltage and the first and second driver outputs or a constant voltage internal ground. When the second input is high, the second NMOS and the third NMOS are gated on, the second driver output is raised to the reduced voltage and the first driver output is pulled down to the constant voltage ground. | 04-23-2009 |
20090089538 | Synchronous Address And Data Multiplexed Mode For SRAM - A synchronous memory system configurable in a multiplexed or non-multiplexed mode. In the multiplexed mode, address and data are provided on a shared bus, and accesses to the memory system are qualified by memory access control signals, including an address strobe signal, a counter enable signal and a counter repeat signal. A read/write control signal is maintained for one cycle after the last valid access command to avoid bus turn-around problems. In the multiplexed mode, chip enable and output enable signals may be constantly activated, thereby simplifying associated printed circuit board design. Different ports of the synchronous memory system can be independently configured to operate in either the multiplexed or non-multiplexed mode. | 04-02-2009 |
20090089532 | Serial Buffer Supporting Virtual Queue To Physical Memory Mapping - A serial buffer having a plurality of virtual queues, which can be allocated to include various combinations of on-chip dual-port memory blocks, on-chip internal memory blocks and/or off-chip external memory blocks. The virtual queues are allocated and accessed in response to configuration bits and size bits stored on the serial buffer. Relatively large external memory blocks can be allocated to virtual queues used for data intensive operations, while relatively small and fast dual-port memory blocks can advantageously be allocated to virtual queues used for passing command and status information. The serial buffer provides an efficient and flexible manner for utilizing available memory, which not only minimizes the access latency but also provides a large amount of buffer space to meet different application needs. | 04-02-2009 |
20090086751 | Adaptive Interrupt On Serial Rapid Input/Output (SRIO) Endpoint - A serial buffer is configured to transmit a plurality of received data packets through a data packet transfer path to a host processor. A doorbell controller of the serial buffer monitors the number of data packets transmitted to the host processor through the data packet transfer path, and estimates the number of data packets actually received by the host processor. The doorbell controller generates a doorbell command each time that the estimated number of data packets corresponds with a fixed number of data packets in a frame. The doorbell commands are transmitted to the host processor on a doorbell command path, which is faster than the data packet transfer path. The doorbell controller may estimate the number of data packets actually received by the host processor in response to a first delay value, which represents how much faster the doorbell command path is than the data packet transfer path. | 04-02-2009 |
20090086750 | Non-Random Access Rapid I/O Endpoint In A Multi-Processor System - A system and method for using a doorbell command to allow sRIO devices to operate as bus masters to retrieve data packets stored in a serial buffer, without requiring the SRIO devices to specify the sizes of the data packets. The serial buffer includes a plurality of queues that store data packets. A doorbell frame request packet identifies the queue to be accessed within the serial buffer, but does not specify the size of the data packet(s) to be retrieved. Upon detecting a doorbell frame request packet, the serial buffer operates as a bus master to transfer the requested data packets out of the selected queue. The selected queue can be configured to operate in a flush mode or a non-flush mode. The serial buffer may also indicate that a received doorbell frame request has attempted to access an empty queue. | 04-02-2009 |
20090086748 | Multi-Function Queue To Support Data Offload, Protocol Translation And Pass-Through FIFO - A multi-port serial buffer having a plurality of queues is configured to include a first set of queues assigned to store write data associated with a first port, and a second set of queues assigned to store write data associated with a second port. The available queues are user-assignable to either the first set or the second set. Write operations to the first set of queues can be performed in parallel with write operations to the second programmable set of queues. In addition, a first predetermined set of queues is assigned to the first port for read operations, and a second predetermined set of queues is assigned to the second port for read operations. Data can be read from the first predetermined set of queues to the first port at the same time that data is read from the second predetermined set of queues to the second port. | 04-02-2009 |
20080238556 | Simple Technique For Reduction Of Gain In A Voltage Controlled Oscillator - A ring oscillator circuit having an odd plurality of inverter stages (i.e., 2N+1 stages). In accordance with one embodiment of the present invention, only one of the inverter stages is operated in response to a variable input voltage, while the remaining inverter stages are operated in response to a highly filtered constant input voltage. The inverter stages that operate in response to the constant input voltage oscillate at a base frequency. The inverter stage that operates in response to the variable input voltage causes the frequency of the output signal to deviate from the base frequency by an amount determined by the variable input voltage. In this manner, the variable voltage inverter stage implements frequency control for the ring oscillator. The gain of the ring oscillator circuit is reduced by a factor of (2N+1) with respect to the gain of a conventional ring oscillator. | 10-02-2008 |
20080238508 | Input Clock Detection Circuit for Powering Down a PLL-Based System - An apparatus is provided for detecting the loss of an input clock signal for a phase-locked loop (PLL). The apparatus includes a time delay circuit, a first frequency divider and a digital logic circuit. The time delay circuit receives the input clock signal and outputs a first time-delayed clock signal. The first frequency divider receives an input signal from an internal clock of the PLL and outputs a clock signal having the same frequency or a lower frequency than that of the time-delayed clock signal. The digital logic circuit that receives the first frequency divider output signal and the first time-delayed clock signal and outputs a signal indicating the loss of the input clock signal if there is no first time-delayed clock signal for a cycle of the first frequency divider output signal. | 10-02-2008 |
20080218274 | PHASE LOCKED LOOP AND DELAY LOCKED LOOP WITH CHOPPER STABILIZED PHASE OFFSET - A control circuit includes a phase frequency detector that receives a reference phase Φ | 09-11-2008 |
20080212581 | Switching Circuit Implementing Variable String Matching - A content matching engine (CME) uses a content addressable memory (CAM) array that stores a plurality of strings in separate entries. The strings define one or more rules to be matched. The strings of each rule are linked, thereby providing a required order. The strings of each rule can be linked by per-entry counters associated with each string, or by a state machine. The strings in the CAM array are compared with a packet, which is shifted one symbol at a time (because the strings can start on any boundary). When the CAM detects a match, the CAM skips over the string that resulted in the match, thereby preventing erroneous matches. The CAM allows parallel matching to be performed for multiple rules. If the contents of a packet match all of the strings of a rule, in order, then the CME asserts a match/index signal that identifies the matched rule. | 09-04-2008 |
20080209139 | Rapid Input/Output Doorbell Coalescing To minimize CPU Utilization And Reduce System Interrupt Latency - Status/error reporting is implemented using a doorbell system. A plurality of flag registers are included on a system device, such as a serial buffer. Each flag register has a corresponding address, and stores a plurality of flags. A flag scan controller accesses the flag registers in a predetermined priority order, using the flag register addresses. Upon detecting that one or more of the flags of a flag register are activated, the flag scan controller causes a doorbell command to be generated. The doorbell command includes the flag register address and the corresponding flags. A system processor receives the doorbell command and services the activated flags. Once the activated flags are serviced, the system processor performs one or more software write operations to clear the flags within the system device. The system processor can simultaneously service multiple flags. The system processor can also simultaneously clear multiple flags. | 08-28-2008 |
20080209089 | Packet-Based Parallel Interface Protocol For A Serial Buffer Having A Parallel Processor Port - A serial buffer is provided having a parallel port configured to couple the serial buffer to a first system via a parallel interface protocol. The serial buffer also includes a serial port configured to couple the serial buffer to a second system via a serial interface protocol and control logic that enables data to be transferred between the parallel port and the serial port in an efficient manner. In one embodiment, the parallel interface protocol is substantially identical to a quad-data rate burst of two (QDRII-B2) interface protocol. | 08-28-2008 |
20080209084 | Hardware-Based Concurrent Direct Memory Access (DMA) Engines On Serial Rapid Input/Output SRIO Interface - A serial buffer includes queues configured to store data packets received from a host. A direct memory access (DMA) engine receives data packets from the highest priority queue having a water level that reaches a corresponding watermark. The DMA engine is configured in response to a DMA register set, which is selected from a plurality of DMA register sets. The DMA register set used to configure the DMA engine can be selected in response to information in the header of the read data packet, or in response to the queue from which the data packet is read. Each DMA register set defines a corresponding buffer in system memory, to which the data packet is transferred. Each DMA register set also defines whether the corresponding buffer is accessed in a wrap mode or a stop mode, and whether doorbell signals are generated in response to transfers to the last address in the corresponding buffer. | 08-28-2008 |
20080205438 | Multi-Bus Structure For Optimizing System Performance Of a Serial Buffer - A serial buffer having a parser and multiple parallel processing paths is provided. The parser receives incoming packets, determines the type of each packet, and then routes each packet to a processing path that corresponds with the determined packet type. Packet types may include blocking priority packets (which implement bus slave operations), non-blocking priority packets (which access on-chip resources of the serial buffer) and data packets (which implement bus master operations). Because the different packet types are processed on parallel processing paths, the processing of one packet type does not interfere with the processing of other packet types. As a result, blocking conditions within the serial buffer are minimized. | 08-28-2008 |
20080205422 | Method And Structure To Support System Resource Access Of A Serial Device Implementing A Lite-Weight Protocol - On-chip resources of a serial buffer are accessed using priority packets of a Lite-weight protocol. A priority packet path is provided on the serial buffer to support priority packets. Normal data packets are processed on a normal data packet path, which operates in parallel with the priority packet path. The system resources of the serial buffer can be accessed in response to the priority packets, without blocking the flow of normal data packets. Thus, normal data packets may flow through the serial buffer with the maximum bandwidth supported by the serial interface. The Lite-weight protocol also supports read accesses to queues of the serial buffer (which reside on the normal data packet path). The Lite-weight protocol also supports doorbell commands for status/error reporting. | 08-28-2008 |