Innophase Inc. Patent applications |
Patent application number | Title | Published |
20150326230 | Polar Receiver with Reduced Amplitude-Phase Distortion - A receiver includes a harmonic injection-locked oscillator, which receives an RF modulated signal and provides an output to two parallel signal paths. A fundamental injection-locked oscillator is provided on one of the signal paths. A phase discriminator detects a phase difference between signals that have passed through the first and second signal paths. At least one of the signal paths includes an amplitude limiting circuit. One or more of the signal paths may include an adjustable delay circuit. | 11-12-2015 |
20150222286 | Apparatus and Method for Digital to Analog Conversion with Current Mirror Amplification - A DAC using current mirrors suitable for use in a modulator. Embodiments include a current-generating circuit to provide an information signal; a bias current source; a current mirror having a mirror input transistor connected to the current generating circuit and the bias current source, and being driven by the bias current and the varying current signal and having a corresponding varying voltage signal at a control terminal; a signal shaping filter interposed between the mirror input transistor and an output mirror transistor configured to limit a bandwidth of the varying voltage signal; the output mirror transistor configured to generate a band-limited varying current signal and a mirrored bias current; and, a mirrored bias current reduction circuit connected to the output mirror transistor configured to reduce the mirrored bias current. | 08-06-2015 |
20140270003 | Polar Receiver Architecture and Signal Processing Methods - Compressing a variable phase component of a received modulated signal with a second harmonic injection locking oscillator, and generating a delayed phase-compressed signal with a fundamental injection locking oscillator, and combining the phase-compressed signal and the delayed phase-compressed signal to obtain an estimated derivative of the variable phase component, and further processing the estimated derivative to recover data contained within the received modulated signal. | 09-18-2014 |
20140269999 | Polar Receiver Signal Processing Apparatus and Methods - A method of generating inphase and quadrature signals from a polar receiver providing a phase derivative signal and an envelope magnitude signal comprising receiving an estimated phase derivative signal; generating an estimated phase signal; mapping the estimated phase signal to an angular value; converting the estimated phase signal to an inphase signal and a quadrature signal based on the angular value; and, providing the inphase signal and quadrature signal to a demodulation circuit. | 09-18-2014 |
20140266480 | Digitally Controlled Injection Locked Oscillator - An injection locking oscillator (ILO) comprising a tank circuit having a digitally controlled capacitor bank, a cross-coupled differential transistor pair coupled to the tank circuit, at least one signal injection node, and at least one output node configured to provide an injection locked output signal; a digitally controlled injection-ratio circuit having an injection output coupled to the at least one signal injection node, configured to accept an input signal and to generate an adjustable injection signal applied to the at least one injection node; and, an ILO controller connected to the capacitor bank and the injection-ratio circuit configured to apply a control signal to the capacitor bank to adjust a resonant frequency of the tank circuit and to apply a control signal to the injection-ratio circuit to adjust a signal injection ratio. | 09-18-2014 |
20140266454 | LNA with Linearized Gain Over Extended Dynamic Range - A low noise amplifier including a variable gain amplifier stage configured to accept an input signal and to provide a load driving signal; a tunable bandpass filter connected as a load to the variable gain amplifier stage, wherein the bandpass filter includes a cross-coupled transistor pair, and at least one cross-coupled compensation transistor pair biased in a subthreshold region configured to add a transconductance component when the load driving signal is of a magnitude large enough to decreases a transconductance of the cross-coupled transistor pair; and, a controller circuit configured to tune the bandpass filter. The filter can be tuned in respect to the frequency and the quality factor Q. | 09-18-2014 |
20140185708 | Single-Bit Direct Modulation Transmitter - Single-bit transmitter modulator having a digital pulse shaping filter configured to shape data pulses of an inphase signal and quadrature signal; an upsampling filter configured to increase the sample rate of the inphase signal and quadrature signal; a sigma-delta modulator providing a one-bit inphase output signal and a one-bit quadrature output signal; an inphase low-order analog low pass filter coupling the one-bit inphase output signal to an inphase channel input of a quadrature modulator, and a quadrature low-order analog low pass filter coupling the one-bit quadrature output signal to a quadrature channel input of a quadrature modulator; and, wherein the quadrature modulator is connected to a carrier signal generator and is configured to generate an inphase and quadrature modulated carrier. | 07-03-2014 |
20140023163 | RECEIVER ARCHITECTURE AND METHODS FOR DEMODULATING BINARY PHASE SHIFT KEYING SIGNALS - A receiver is described. The receiver includes a first injection-locked oscillator having a first input configured to receive a BPSK signal and a second input configured to receive a first frequency reference. The receiver also includes a second injection-locked oscillator having a third input configured to receive the BPSK signal and a fourth input configured to receive a second frequency reference. Further, the receiver includes a first phase-locked loop coupled with the second input of the first injection-locked oscillator. The first phase-locked loop is configured to generate the first frequency reference. And, a second phase-locked loop is coupled with the fourth input of the second injection-locked oscillator. The second phase-locked loop is configured to generate the second frequency reference. | 01-23-2014 |
20130195224 | Receiver Architecture and Methods for Demodulating Quadrature Phase Shift Keying Signals - A receiver is described. The receiver includes a filter configured to receive a quadrature phase shift keying (“QPSK”) signal. Further, the receiver includes an amplifier coupled with the filter. And, a QPSK decomposition filter is coupled with the amplifier. The QPSK decomposition filter is configured to generate a first BPSK signal based on the QPSK signal and a second BPSK signal based on the QPSK signal. | 08-01-2013 |
20130195223 | Receiver Architecture and Methods for Demodulating Binary Phase Shift Keying Signals - A receiver is described. The receiver includes a first injection-locked oscillator having a first input configured to receive a BPSK signal and a second input configured to receive a first frequency reference. The receiver also includes a second injection-locked oscillator having a third input configured to receive the BPSK signal and a fourth input configured to receive a second frequency reference. Further, the receiver includes a first phase-locked loop coupled with the second input of the first injection-locked oscillator. The first phase-locked loop is configured to generate the first frequency reference. And, a second phase-locked loop is coupled with the fourth input of the second injection-locked oscillator. The second phase-locked loop is configured to generate the second frequency reference. | 08-01-2013 |
20130195157 | Transceiver Architecture and Methods for Demodulating and Transmitting Phase Shift Keying Signals - A transceiver is described. The transceiver includes a first injection-locked oscillator and a second injection-locked oscillator. The transceiver also includes a first phase-locked loop coupled with the first injection-locked oscillator. The first phase-locked loop is configured to generate a first frequency reference. Further, the transceiver includes a second phase-locked loop coupled the second injection-locked oscillator. The second phase-locked loop is configured to generate a second frequency reference. The transceiver includes a mixer configured to receive the first phase-locked loop output and configured to receive said second injection-locked oscillator output. The mixer is also configured to generate a carrier frequency signal based on the first injection-locked oscillator output and the second injection-locked oscillator output. And, the transceiver includes a modulator configured to receive said carrier frequency signal. | 08-01-2013 |