Global Foundries Singapore PTE. Ltd. Patent applications |
Patent application number | Title | Published |
20150037948 | METHODS FOR FABRICATING INTEGRATED CIRCUITS WITH A HIGH-VOLTAGE MOSFET - Methods for fabricating integrated circuits are disclosed. In an exemplary embodiment, a method for fabricating an integrated circuit includes forming a silicon material layer over a semiconductor substrate. The method further includes forming a capping layer over the silicon material layer and over the memory gate stack, removing the capping layer from over the memory array region and the high-voltage MOSFET region, forming a second silicon material layer over the capping layer and over the first silicon material layer, and removing the second silicon material layer. The method further includes removing the capping layer from over the first silicon material layer in the logic device region and removing the first and second silicon material layers from the high-voltage MOSFET region. Still further, the method includes forming a photoresist material layer over the memory array region and the logic device region and exposing the semiconductor substrate to an ion implantation process. | 02-05-2015 |
20140264762 | WAFER STACK PROTECTION SEAL - A semiconductor wafer stack and a method of forming a semiconductor device is disclosed. The method includes providing first and second wafers with top and bottom surfaces. The wafers include edge and non-edge regions, and the first wafer includes devices formed in the non-edge region. A first protection seal may be formed at the edge region of the first wafer. The first and second wafers may further be bonded to form a device stack. The protection seal in the device stack contacts the first and second wafers to form a seal, and protects the devices in subsequent processing. | 09-18-2014 |
20140247526 | FALSE-TRIGGERED IMMUNITY AND RELIABILITY-FREE ESD PROTECTION DEVICE - An acceptable voltage margin between a voltage level for triggering electrostatic current discharge and a voltage level for programming operation of an OTP device is determined. Activation of an ESD protection circuit is controlled in part in response to a false trigger prevention circuit. To avoid gate oxide breakdown that may occur with a MOSFET protection device used for higher voltage requirements of an OTP device, the ESD protection circuit employs a bipolar transistor. | 09-04-2014 |
20140151775 | CONTROL GATE - A method for forming a semiconductor device is disclosed. The method includes providing a substrate prepared with a second gate structure. An inter-gate dielectric is formed on the substrate and over the second gate. A first gate is also formed. The first gate is adjacent to and separated from the second gate by the inter-gate dielectric. The substrate is patterned to form a split gate structure with the first and second adjacent gates. The split gate structure is provided with an e-field equalizer adjacent to the first gate. The e-field equalizer improves uniformity of e-field across the first gate during operation. | 06-05-2014 |
20140048865 | NOVEL COMPACT CHARGE TRAP MULTI-TIME PROGRAMMABLE MEMORY - A method for enabling fabrication of memory devices requiring no or minimal additional mask for fabrication having a low cost, a small footprint, and multiple-time programming capability is disclosed. Embodiments include: forming a gate stack on a substrate; forming a source extension region in the substrate on one side of the gate stack, wherein no drain extension region is formed on the other side of the gate stack; forming a tunnel oxide liner on side surfaces of the gate stack and on the substrate on each side of the gate stack; forming a charge-trapping spacer on each tunnel oxide liner; and forming a source in the substrate on the one side of the gate stack and a drain in the substrate on the other side of the gate stack. | 02-20-2014 |
20140030958 | SINGLE GROOVED POLISHING PAD - A polishing pad, an apparatus for chemical mechanical polishing of semiconductor wafers and a method of making a device using the same are presented. The apparatus includes a first platform for mounting a semiconductor wafer; a second platform for mounting a polishing pad; a rotator for rotating the wafer against the polishing pad; and a diamond dresser for dressing the polishing pad. The polishing pad has a single groove of a width (w) surrounding the periphery of an undressed portion of the polishing pad thus eliminating contact of the undressed portion with the outer edge of the diamond dresser. | 01-30-2014 |
20130181259 | STEP-LIKE SPACER PROFILE - Interlayer dielectric gap fill processes are enhanced by forming gate spacers with a step-like or tapered profile. Embodiments include forming a gate electrode on a substrate, depositing a spacer material over the gate electrode, etching the spacer material to form a first spacer on each side of the gate electrode, and pulling back the first spacers to form second spacers which have a step-like profile. Embodiments further include depositing a second spacer material over the gate electrode and the second spacers, and etching the second spacer material to form a third spacer on each second spacer, the second and third spacers forming an outwardly tapered composite spacer. | 07-18-2013 |
20130084697 | SPLIT GATE MEMORY DEVICE WITH GAP SPACER - A method for forming a split gate device includes forming a first sidewall of a first conductive gate layer, wherein the semiconductor layer includes a tunnel region laterally adjacent the first sidewall, forming a dielectric layer along the first sidewall to provide for increased thickness of a gap spacer, forming a charge storage layer over a portion of a top surface of the first conductive layer and over the tunnel region, and forming a second conductive gate layer over the charge storage layer. | 04-04-2013 |
20120119293 | HIGH PERFORMANCE LDMOS DEVICE HAVING ENHANCED DIELECTRIC STRAIN LAYER - An LDMOS device includes a substrate having a surface and a gate electrode overlying the surface and defining a channel region in the substrate below the gate electrode. A drain region is spaced apart from the channel region by an isolation region. The isolation region includes a region of high tensile stress and is configured to induce localized stress in the substrate in close proximity to the drain region. The region of high tensile stress in the isolation region can be formed by high-stress silicon oxide or high-stress silicon nitride. In a preferred embodiment, the isolation region is a shallow trench isolation region formed in the substrate intermediate to the gate electrode and the drain region. | 05-17-2012 |