FARADAY TECHNOLOGY CORPORATION Patent applications |
Patent application number | Title | Published |
20150138869 | NON-VOLATILE MEMORY - A non-volatile memory includes a memory unit. The memory unit includes a first word line, a second word line, a control line, a logic circuit, a bit line, a first cell, and a second cell. The logic circuit has a first input terminal connected to the first word line, a second input terminal connected to the second word line, and an output terminal connected to the control line. The first cell has a control terminal connected to the first word line, a first terminal connected to the control line, and a second terminal selectively connected to the bit line. The second cell has a control terminal connected to the second word line, a first terminal connected to the control line, and a second terminal selectively connected to the bit line. | 05-21-2015 |
20150009197 | VIDEO OUTPUT SYSTEM AND LOAD DETECTING METHOD THEREFOR - A video output system at least includes a first video output terminal, a control circuit, a first digital-to-analog converter, and a first bias voltage generator. The first video output terminal is selectively connected with a first video input terminal of a display device through a signal cable. According to a constant detecting current generated by the first digital-to-analog converter, or the first bias voltage generator, the first video output terminal has a detecting voltage for indicating whether the video output system is connected with the display device. When the video output system is connected with the display device, the control circuit enables the first digital-to-analog converter but disables the first bias voltage generator. When the video output system is not connected with the display device, the control circuit disables the first digital-to-analog converter but enables the first bias voltage generator. | 01-08-2015 |
20140149628 | SUPER SPEED USB HUB AND TRAFFIC MANAGEMENT METHOD THEREOF - A super speed USB hub includes an upstream port, a plurality of device ports, a transaction dispatching unit, a downstream buffer, a hub local packet parser, a traffic control unit, and a forwarding unit. The transaction dispatching unit is used for receiving a plurality of packets from a USB hot, wherein the plurality of packets comprise a plurality of downstream packets and a hub command packet. If the hub command packet contains a traffic management command, the hub local packet parser generates a selected target and a control mode according to the traffic management command. The traffic control unit is used for managing a downstream packet corresponding to the selected target among the plurality of downstream packets in the downstream buffer according to the selected target and the control mode. | 05-29-2014 |
20130044397 | ESD PROTECTION CIRCUIT - ESD protection circuit including a resistor and at least one protection transistor; the resistor coupled between an I/O signal node and an internal node of internal circuit, the protection transistors serially coupled between the internal node and a voltage node with each protection transistor comprising a gate and a drain which is coupled to the gate. | 02-21-2013 |
20130039450 | METHOD AND ASSOCIATED APPARATUS OF DATA EXTRACTION - Method and associated apparatus of data extraction, including: sampling a signal and obtaining a plurality of sampled values, providing a reference sample quantity when the sampled values transit, providing a unit bit sample quantity according to the reference sample quantity, and corresponding each of the sampled values to each data bit of the signal according to the unit bit sample quantity. | 02-14-2013 |
20120275073 | ESD PROTECTION CIRCUIT - Electrostatic discharge (ESD) protection circuit including a first silicon controlled rectifier (SCR) and a trigger circuit; the trigger circuit including a first MOS transistor and a second transistor, triggering the first SCR and providing a second SCR shunt with the first SCR during ESD. | 11-01-2012 |
20120169303 | VOLTAGE REGULATOR - A voltage regulator includes a constant voltage power circuit and an overcurrent protection circuit. The constant voltage power circuit generates an output voltage, an output current and a divided voltage. The overcurrent protection circuit includes a current sensing unit, a first mirroring unit, a voltage to current converting unit, a second mirroring unit, and a pull up unit. The current sensing unit generates a sensing current according to the output current. The first mirroring unit generates a first mirroring current. The first mirroring current is proportional to the output current. The voltage to current converting unit is used for converting the divided voltage into a first current. | 07-05-2012 |
20120154960 | ESD PROTECTION CIRCUIT WITH EOS IMMUNITY - ESD protection circuit with EOS immunity is provided, which includes a first connection circuit, a first EOS control circuit formed by at least a diode, and an ESD clamp respectively coupled between a pad, a first clamp node, an I/O clamp node and a second source node. When the ESD clamp detects ESD through the I/O clamp node, it is triggered to conduct from the I/O clamp node to the second source node. When the pad receives EOS, the first EOS control circuit provides a cross voltage between the first clamp node and the I/O clamp node, such that a voltage of the I/O clamp node becomes less than a characteristic voltage of the ESD clamp to prevent the ESD clamp from reverse conducting. | 06-21-2012 |
20120044779 | DATA-AWARE DYNAMIC SUPPLY RANDOM ACCESS MEMORY - A Random Access Memory (RAM) with a plurality of cells is provided. In an embodiment, the cells of a same column are coupled to a same pair of bit-lines and are associated to a same power controller. Each cell has two inverters; the power controller has two power-switches. For the cells of the same column, the two power-switches respectively perform independent supply voltage controls for the two inverters in each cell according to data-in voltages of the bit-lines during Write operation. | 02-23-2012 |
20120033522 | VARIATION-TOLERANT WORD-LINE UNDER-DRIVE SCHEME FOR RANDOM ACCESS MEMORY - A Random Access Memory (RAM) is provided. The RAM includes a plurality of word-line drivers, at least a first tracking transistor and a second tracking transistor. Each word-line driver has an input node receiving a decoding signal, a power node receiving an operation voltage and a driving node driving a word-line. In an embodiment, the first tracking transistor has two channel terminal nodes respectively coupled to the driving node of one of the word-line driver and a channel terminal node of the second tracking transistor; wherein the first tracking transistor has electronic characteristics tracking those of a driving transistor of word-line driver, and the second tracking transistor has electronic characteristics tracking those of pass-gate transistor(s) in each cell of the RAM. | 02-09-2012 |
20110241914 | TEST SYSTEM AND METHOD FOR ANALOG-TO-DIGITAL CONVERTER - Test system and method for analog-to-digital converter (ADC) based on a loopback architecture are provided to test an M-bit ADC. In the invention, an N-bit digital-to-analog converter (DAC) converts a digital input to a basic test signal, a segmentation circuit scales the basic test signal and superposes it with segmentation DC levels for providing corresponding segmented test signals, such that the ADC converts the segmented test signals to reflect result of testing. With the invention, practical loopback architecture of low-cost can be adopted for testing. | 10-06-2011 |
20110235444 | SRAM WRITING SYSTEM AND RELATED APPARATUS - SRAM writing system and related apparatus are provided. The writing system of the invention has a dummy replica writing circuit, a negative pulse controller and at least a normal writing circuit; each normal writing circuit includes a write driver and a negative pulse supplier. While writing, the dummy replica writing circuit drives a dummy replica bit-line, such that the negative pulse controller generates a negative pulse control signal according to level of the dummy replica bit-line. In each writing circuit, when the write driver conducts to connect an associated bit-line to a bias end for driving a level transition, the negative pulse supplier switches the bias end from an operation voltage to a different negative pulse voltage according to the received negative pulse control signal. | 09-29-2011 |
20110156777 | CLOCK AND DATA RECOVERY CIRCUIT WITH PROPORTIONAL PATH - A clock and data recovery circuit includes a phase detector, a charge pump, a loop filter, a voltage-controlled oscillator and a frequency divider. The voltage-controlled oscillator includes a current mirror, a control circuit, a current modulation module and a current-controlled oscillator. The current mirror has a current-controlling path and a current-outputting path. The current-controlling path and the current-outputting path are in a proportional relationship. The control circuit is used for adjusting the current flowing through the current-controlling path according to the control voltage. The current modulation module is used for generating a differential current according to the judging signal. The current-controlled oscillator is used for adjusting the phase of the second output clock signal according to the sum of the differential current and the current flowing through the current-outputting path. | 06-30-2011 |
20110133836 | CLASS-D AMPLIFIER - Class D amplifier is provided. The class D amplifier includes at least a block; each block includes an input circuit, an integrator, a comparator, a driving circuit and two feedback circuits. The input circuit receives a digital input to provide a differential pair of a positive and a negative input signals. The integrator receives the positive and negative input signals and a pair of positive and negative feedback signals for providing a positive error signal according to the positive input signal and the negative feedback signal, and providing a negative error signal according to the negative input signal and the positive feedback signal. The comparator compares between the positive and the negative error signals such that the driving circuit generates a driving output signal according to comparison result. The two feedback circuits respectively providing said positive and negative feedback signals according to the driving output signal. | 06-09-2011 |
20100289834 | FIELD COLOR SEQUENTIAL DISPLAY CONTROL SYSTEM - Field color sequential (FCS) control system applied for an FCS display device is provided. The FCS control system includes an input system, a memory and an output system. The input system, including a plurality of buffers respectively corresponding to different color channels, receives different color channel components of pixels in parallel such that components of a same color channel are stored in a same buffer. The memory, including a plurality of partitions respectively corresponding to different color channels, stores components of a same color channel to a same partition in association with triggering of rising and falling edges of a clock, respectively. The output system sequentially buffers and outputs color channel components of corresponding partitions. | 11-18-2010 |
20100259552 | FIELD COLOR SEQUENTIAL IMAGING METHOD AND RELATED TECHNOLOGY - Field color sequential (FCS) imaging method and technology/apparatus based on FCS principle are provided. In an embodiment, while displaying a frame based on FCS principle, the invention includes: extracting at least a monochrome subfield value and at least a mixed subfield value from each color channel of each pixel of the frame, writing corresponding monochrome subfield value of each pixel in association with a single color channel, and writing corresponding mixed subfield value of each pixel in association with a mixed color which is mixed by at least two color channels. | 10-14-2010 |
20100237509 | IO CELL WITH MULTIPLE IO PORTS AND RELATED TECHNIQUES FOR LAYOUT AREA SAVING - An IO cell with multiple IO ports and related techniques are provided. The IO cell has a plurality of IO ports for transmitting signal of a same IO pin, and each IO port corresponds to a predetermined region for containing an IO pad, wherein at least one of the plural predetermined regions of the plural IO ports partially overlaps with active circuit layout region of the IO cell. In a chip, if a given IO cell has a predetermined region of an IO port overlapping an IO pad location of another adjacent IO cell, then a predetermined region of another IO port is selected for implementing an IO pad of the given IO cell, such that the IO cells can be arranged more compactly for chip layout area saving. | 09-23-2010 |
20100232079 | SMALL AREA IO CIRCUIT - A small area IO circuit is provided. The IO circuit has one or more parallel circuit unit(s) and an ESD protector set between a core circuit/pre-driver and an IO pad. Each circuit unit includes an off-chip driver and an output resistor, wherein the ESD protector protects ESD event occurred at the IO pad, and the resistor in each circuit unit acts as an ESD block circuit to block ESD current from corresponding off-chip driver. Therefore, transistors in each off-chip driver do not have to be restricted by strict ESD design rules, such that at least a transistor of the off-chip driver(s) is implemented in a single finger layout to lower equivalent capacitance of the off-chip driver(s), and layout areas of the off-chip driver(s) as well as the whole IO circuit can be reduced to achieve a small area IO circuit. | 09-16-2010 |
20100213965 | METHOD AND APPARATUS OF TESTING DIE TO DIE INTERCONNECTION FOR SYSTEM IN PACKAGE - Method and apparatus of testing die to die interconnection for system in package (SiP). For testing a die to die interconnection connected between two pads of two dice, an IO buffer, e.g., a bi-directional IO buffer, in one of the two dice coupled to one of the two pads is arranged. An oscillating feedback is formed between an output port and an input port of the IO buffer, such that a state, e.g., an open state, a short state or a normal state of the die to die interconnection is tested according to a timing characteristic, e.g., a frequency, of a signal of the IO buffer. | 08-26-2010 |
20100060345 | REFERENCE CIRCUIT FOR PROVIDING PRECISION VOLTAGE AND PRECISION CURRENT - A reference circuit for providing a precision voltage and a precision current includes a bandgap voltage reference circuit, a positive temperature coefficient calibrating circuit, a threshold voltage superposing circuit and precision current generator interconnected in cascade. From the bandgap voltage reference circuit, a bandgap voltage is outputted as the precision voltage, and a PTAT current is outputted to the positive temperature coefficient calibrating circuit along with the bandgap voltage for generating a PTAT voltage. In response to the PTAT voltage from the positive temperature coefficient calibrating circuit, the threshold voltage superposing circuit generates a first voltage which is equal to the PTAT voltage plus a threshold voltage. Then the precision current generator outputs a reference current as the precision current in response to the first voltage. | 03-11-2010 |
20100031206 | METHOD AND TECHNIQUE FOR ANALOGUE CIRCUIT SYNTHESIS - Method and technique for analogue circuit synthesis. An analogue circuit usually includes many circuit components, and characteristics and functions of each circuit component are controlled by many corresponding parameters. In the presented invention, selected key design parameters of selected critical circuit components, as well as optimization targets, design specification or/and design constraint, are transformed into an optimization plan, and an optimization engine iterates circuit level or system level numerical simulations by changing values of the selected key design parameters recorded in the optimization plan, so as to find optimized parameters and circuit components which allow the analogue circuit to match the design specification/constraint and to approach the optimization target. Thus a systematic automation for analogue circuit synthesis/design/optimization is achieved. | 02-04-2010 |
20100019774 | ISOLATION CELL WITH TEST MODE - An isolation cell having a test mode, connected between a first block and a second block, wherein the first block can operate in either a power-up mode or a power-down mode, comprises: an input terminal for receiving an input signal that is derived from the first block; an output terminal for outputting an output signal to the second block; a normal-sleep terminal for determining the isolation cell is operated in the power-up mode or in the power-down mode, and the logic level of the normal-sleep terminal is determined by the operation mode of the first block; and, a DFT-sleep terminal is for overwriting the logic level of the normal-sleep terminal when the isolation cell is in the test mode. | 01-28-2010 |
20090295481 | HIGH SPEED DIFFERENTIAL TO SINGLE ENDED CONVERTING CIRCUIT - A differential to single ended converting circuit includes a transconductance circuit having input terminals for receiving differential input voltages and having a first current output terminal for outputting a first current and a second current output terminal for outputting a second current; an offset cancellation circuit having a first controllable current source connected to the first current output terminal and a second controllable current source connected to the second current output terminal; a first transimpedance circuit having an input terminal connected to the first current output terminal and an output terminal for outputting a first voltage; a second transimpedance circuit having an input terminal connected to the second current output terminal and an output terminal for outputting a second voltage; and a first inverter having an input terminal connected to the output terminal of the first transimpedance circuit and an output terminal for outputting a first single ended output voltage. | 12-03-2009 |
20090268961 | COLOR-SATURATION CONTROL METHOD - For performing saturation control of one or more selected colors of the image, respective color values of the selected color(s) are pre-defined. Meanwhile, a specified pixel is selected from the image. Then distance(s) between the color space coordinate of the specified pixel and the color space coordinate(s) of the selected color(s) is (are) calculated. The color values of the specified pixel are thus adjusted depending on comparing results of the distance(s) with corresponding threshold distance(s). | 10-29-2009 |
20090257273 | 2T SRAM CELL STRUCTURE - A SRAM cell structure includes a first N type switch, a second N type switch, a first storage node, and a second storage node. The first N type switch has a control terminal connected to a word line and a first terminal connected to a bit line. The second N type switch has a control terminal connected to the word line and a first terminal connected to an inverted bit line. The first storage node has a first terminal connected to a second terminal of the first N type switch. The second storage node has a first terminal connected to a second terminal of the second N type switch. | 10-15-2009 |
20090251483 | METHOD AND RELATED CIRCUIT FOR COLOR DEPTH ENHANCEMENT OF DISPLAYS - Method and related circuit for color depth enhancement of displays is provided. In an embodiment of the invention, when emulating an interpolated color level between a first and a second color levels the display can display, a color channel component of the first color level and another color channel component of the second color level are selected for color dithering and color depth enhancement. | 10-08-2009 |
20090251185 | DATA RETENTION DEVICE FOR MULTIPLE POWER DOMAINS - A data retention device includes a first latch disposed between a data input terminal and a data output terminal for storing a data signal received from the data input terminal and transmitting the data signal through a data forward path to the data output terminal according to a clock signal in an operational mode; a second latch disposed in a branch of the data forward path between the first latch and the data output terminal for receiving the data signal in the operational mode and retaining the data signal in a sleep mode; and a first tri-state buffer disposed in the data forward path between the first latch and the branched second latch and enabled to conduct the data forward path in the operational mode and disabled to cut off the data forward path in the sleep mode according to a data retention signal. | 10-08-2009 |
20090201186 | CURRENT STEERING DAC AND VOLTAGE BOOSTER OF SAME - A digital-to-analog converter is coupled to a first voltage source and used for converting a digital input into an analog output. The DAC includes a voltage booster providing a first gate-source voltage and a second gate-source voltage to generate a voltage of a first level according to the first voltage source and the first gate-source voltage, and to generate a voltage of a second level according to the voltage of the first level and the second gate-source voltage; and a current-guiding circuit selectively receiving the voltage of the first level or the second level according to the digital input to generate the analog output. The first level and the second level vary with the first voltage source. | 08-13-2009 |
20090189670 | LEVEL SHIFTER WITH REDUCED POWER CONSUMPTION AND LOW PROPAGATION DELAY - A level shifter includes a Not gate coupled to a signal input and operable between a first high level and a low level; a first PMOS transistor coupled to a second voltage source and a control end; a first NMOS transistor coupled to the first PMOS transistor, a Not-gate output end and a reference voltage; and a control circuit coupled to the signal input, the Not-gate output end and the second voltage source. When the signal input and the Not-gate output end are at the first high level and the low level, respectively, the first PMOS transistor is turned on so that the signal output is at a second high level; and when the signal input and the Not-gate output end are switched contrarily, the first PMOS transistor is turned off and the signal output is at the low level. | 07-30-2009 |
20090189665 | SCHMITT-TRIGGER-BASED LEVEL DETECTION CIRCUIT - A Schmitt trigger includes A first PMOS transistors having the drains and sources thereof serially connected and coupled between a voltage source and an output end, and having gates thereof coupled to an input end; B first NMOS transistors having the drains and sources thereof serially connected and coupled between the output end and ground, and having gates thereof coupled to the input end; C second PMOS transistors, each being coupled between ground and a node between the drain and the source of the first PMOS transistors and having the gate thereof coupled to the output end; and D second NMOS transistors, each being coupled between the voltage source and a node between the drain and the source of the first NMOS transistors and having the gate thereof coupled to the output end. A is greater than 2 and C, and B is greater than 2 and D. | 07-30-2009 |
20090128203 | PLL-BASED TIMING-SIGNAL GENERATOR AND METHOD OF GENERATING TIMING SIGNAL BY SAME - A timing-signal generator includes a PLL circuit, one or more rising/falling edge generating unit and one or more timing-signal generating unit. In response to a reference signal with a frequency F | 05-21-2009 |
20090051342 | BANDGAP REFERENCE CIRCUIT - A bandgap reference circuit includes an input circuit having a first FET, a second FET, and a first resistor, wherein a first node is connected to the first FET having a first threshold voltage, the first resistor is connected between a second node and the second FET having a second threshold voltage; a mirroring circuit for controlling two output currents respectively derived from the first and second nodes, and maintaining the two output currents to a specific current ratio; and an operation amplifier connected to the first node, the second node of the input circuit, and the mirroring circuit, for controlling two voltages respectively at the first and second nodes of the input circuit to a specific voltage ratio; wherein the first FET and the second FET are both operating in the subthreshold region, the first threshold voltage is larger than the second threshold voltage, and the two output currents are independent of temperature. | 02-26-2009 |
20090051341 | BANDGAP REFERENCE CIRCUIT - A bandgap reference circuit includes a PTAT current generating circuit for generating a PTAT current; a CTAT circuit generating circuit for generating a CTAT current; a node for receiving the PTAT current and the CTAT current; and, a first resistor connected between the node and a ground, wherein a reference voltage is derived from the first resistor when a superposed current of the PTAT current and the CTAT current is flowing through the first resistor. | 02-26-2009 |
20090016450 | IN-LOOP DEBLOCKING-FILTERING METHOD AND APPARATUS APPLIED TO VIDEO CODEC - An in-loop deblocking-filtering method applied to a video CODEC is provided. The method includes steps of: receiving a macroblock of pixel values outputted from a motion-compensating unit; dividing the macroblock of pixel values into a plurality of block of pixel values, and executing a data-transpose procedure to the plurality of blocks of pixel values; storing the plurality of block of pixel values, which are processed by the data-transpose procedure, in a memory buffer; executing a horizontal deblocking-filtering procedure to the macroblock of pixel values, which are stored in the memory buffer, for updating a portion of the pixel values in the macroblock; executing the data-transpose procedure to the plurality of block of pixel values stored in the memory buffer; and executing a vertical deblocking-filtering procedure to the macroblock of pixel values, which are stored in the memory buffer, for updating a portion of the pixel values in the macroblock. | 01-15-2009 |
20080303573 | DATA-RETENTION LATCH FOR SLEEP MODE APPLICATION - A latch includes a data input terminal for receiving a data signal; a data output terminal for outputting the data signal; a first control terminal for receiving a control signal to set or reset the data signal derived from the data output terminal; a sleep signal input terminal for receiving a sleep signal to determine a sleep mode; a first logic circuit having input terminals coupled to the data input terminal, the first control terminal and the sleep signal input terminal and an output terminal coupled to the data output terminal; and a second logic circuit having input terminals coupled to the data output terminal, the first control terminal and the sleep signal input terminal and an output terminal coupled to the data input terminal; wherein the first logic circuit or the second logic circuit ignores the first control signal in response to the sleep signal when the latch is operated in the sleep mode. | 12-11-2008 |
20080303566 | SPREAD SPECTRUM CLOCK GENERATOR WITH LOW JITTER - A spread spectrum clock generator includes: a phase frequency detector, for generating a phase difference signal according to a frequency divided signal and a reference signal with a reference frequency; a charge pump, for receiving the phase difference signal and generating an output current according to the phase difference signal; a loop filter, for receiving the output current and converting the output current to a voltage-controlled signal; a voltage-controlled oscillator, for receiving the voltage-controlled signal and generating a plurality of voltage-controlled output signals, wherein the plurality of voltage-controlled signals have a specific phase difference and a same voltage-controlled frequency; a frequency dividing unit, for receiving the plurality of voltage-controlled output signal and generating the frequency divided signal; and a delta-sigma modulator, for controlling the frequency dividing unit to have an equivalent divided value of (N+b)S+(N−a)(P−S) through receiving the frequency divided signal and a control word; wherein N, P, and S are integers, and a, b are fractional numbers, and S can be adjusted by the delta-sigma modulator. | 12-11-2008 |
20080291598 | OUTPUT STAGE AND RELATED LOGIC CONTROL METHOD APPLIED TO SOURCE DRIVER/CHIP - Output stage and related method applied to source driver/chip of LCD panel. While performing dot polarization inversion for even/odd channels of LCD panel, n-channel and p-channel MOS transistors of symmetric layout are respectively adopted for alternately transmitting a positive polarization signal of higher swing range and a negative polarization signal of lower swing range from corresponding drivers of asymmetric layout to the even/odd channels, such that a layout area for alternating polarizations can be reduced. Also, the invention directly ties inputs of the output drivers to V | 11-27-2008 |
20080285196 | OVER-VOLTAGE INDICATOR AND RELATED CIRCUIT AND METHOD - Over-voltage indicator and related circuit and method. The over-voltage indicator can work with an I/O circuit of a chip for detecting over-voltage in an I/O pad and providing an indication signal accordingly. When over-voltage does not happen, the over-voltage indicator continues to detect a signal level of the I/O pad and keeps the indication signal low. Once over-voltage is detected, the over-voltage indicator pauses detecting, asserts a high level in the indication signal, and periodically resumes detecting until end of over-voltage is detected. With informing provided by the indication signal, a core cell of the chip can perform proper operation to reduce potential damage caused by over-voltage. | 11-20-2008 |
20080231336 | SCAN FLIP-FLOP CIRCUIT WITH EXTRA HOLD TIME MARGIN - The present invention is a scan flip-flop circuit with extra hold time margin. The scan flip-flop circuit includes a multiplexer, a sense amplifier and a latch. The latch includes a generation unit for generating an output signal in response to a first signal and a second signal outputted from the sense amplifier, and a storage unit receives the second signal and the output signal and maintains the output signal of the latch when the first signal and the second signal are non-activated. | 09-25-2008 |