CICLON SEMICONDUCTOR DEVICE CORP.
|CICLON SEMICONDUCTOR DEVICE CORP. Patent applications|
|Patent application number||Title||Published|
|20100176508||SEMICONDUCTOR DEVICE PACKAGE AND METHOD OF ASSEMBLY THEREOF - A semiconductor die package includes: an assembly including a semiconductor die, a clip structure attached to an upper surface of the semiconductor die, and a heat sink attached to an upper surface of the clip structure; and a molding material partially encapsulating the assembly, wherein an upper surface of the heat sink is exposed through the molding material.||07-15-2010|
|20100171543||PACKAGED POWER SWITCHING DEVICE - A packaged switching device for power applications includes at least one pair of power MOSFET transistor dies connected between upper and lower power source rail leads, a high side one of the pair of MOSFET transistor dies being connected to the upper power source rail lead and a low side one of the pair of MOSFET transistor dies being connected to the lower power source rail lead. At least one of the MOSFET transistor dies is configured for vertical current flow therethrough and has a source electrode at a backside thereof.||07-08-2010|
|20090267145||MOSFET DEVICE HAVING DUAL INTERLEVEL DIELECTRIC THICKNESS AND METHOD OF MAKING SAME - A method of forming a metal-oxide-semiconductor (MOS) device includes the following steps: forming a semiconductor layer of a first conductivity type having source and drain regions of a second conductivity type, a channel region and a lightly-doped drain region formed therein; forming a gate over the channel region proximate an upper surface of the semiconductor layer; after the forming steps, depositing a first dielectric layer having a first thickness over an upper surface of the semiconductor layer; etching the first dielectric layer in a region over the lightly-doped drain proximate to the gate to reduce its thickness; conformably depositing a second dielectric layer having a second thickness over the first dielectric layer, including in the etched region, the second thickness being less than the first thickness; and forming a shielding electrode over the second dielectric layer.||10-29-2009|
|20080246086||SEMICONDUCTOR DEVICES HAVING CHARGE BALANCED STRUCTURE - A laterally diffused metal-oxide-semiconductor transistor device includes a substrate having a first conductivity type with a semiconductor layer formed over the substrate. A source region and a drain extension region of the first conductivity type are formed in the semiconductor layer. A body region of a second conductivity type is formed in the semiconductor layer. A conductive gate is formed over a gate dielectric layer that is formed over a channel region. A drain contact electrically connects the drain extension region to the substrate and is laterally spaced from the channel region. The drain contact includes a highly-doped drain contact region formed between the substrate and the drain extension region in the semiconductor layer, wherein a topmost portion of the highly-doped drain contact region is spaced from the upper surface of the semiconductor layer. A source contact electrically connects the source region to the body region.||10-09-2008|
|20080197411||MOS TRANSISTOR DEVICE IN COMMON SOURCE CONFIGURATION - A semiconductor device includes a semiconductor substrate, a first p-channel laterally diffused metal oxide semiconductor (LDMOS) transistor formed over the semiconductor substrate and additional p-channel LDMOS transistors formed over the semiconductor substrate. First drain and gate electrodes are formed over the substrate and are coupled to the first LDMOS transistor. Additional drain and gate electrodes are formed over the substrate and are coupled to the second LDMOS transistor. A common source electrode for the first and second LDMOS transistors is also formed over the substrate.||08-21-2008|
Patent applications by CICLON SEMICONDUCTOR DEVICE CORP.