Atmel Rousset S.A.S. Patent applications |
Patent application number | Title | Published |
20130145063 | Microcontroller resource sharing - A system includes one or more master modules configured to execute instructions embedded in non-transitory machine-readable media and controllable by a processor. The system also includes one or more peripheral modules that are configured to execute instructions embedded in non-transitory machine-readable media and controllable by the processor. The system also includes a system bus with instructions embedded in a non-transitory machine-readable medium and configured to allow data transfer between the processor and the one or more peripheral modules. A data processing module of the one or more peripheral modules includes a master interface and a slave interface. Both master and slave interfaces are coupled to the system bus. | 06-06-2013 |
20130036246 | MICROCONTROLLER SYSTEM BUS SCHEDULING FOR MULTIPORT SLAVE MODULES - A system includes master modules, at least one multiport slave module, and a scheduler connected by a system bus. The scheduler is configured to provide scheduling information to the multiport slave module. The scheduling information includes master categorization information and anticipated burst information. The anticipated burst information is based on a scheduler determination for an anticipated bus access by an anticipated master module. The master categorization information categorizes the anticipated master. | 02-07-2013 |
20120267717 | ENHANCED HVPMOS - A p-channel LDMOS device with a controlled n-type buried layer (NBL) is disclosed. A Shallow Trench Isolation (STI) oxidation is defined, partially or totally covering the drift region length. The NBL layer, which can be defined with the p-well mask, connects to the n-well diffusion, thus providing an evacuation path for electrons generated by impact ionization. High immunity to the Kirk effect is also achieved, resulting in a significantly improved safe-operating-area (SOA). The addition of the NBL deep inside the drift region supports a space-charge depletion region which increases the RESURF effectiveness, thus improving BV. An optimum NBL implanted dose can be set to ensure fully compensated charge balance among n and p doping in the drift region (charge balance conditions). The p-well implanted dose can be further increased to maintain a charge balance, which leads to an Rdson reduction. | 10-25-2012 |
20120233232 | Variable Architecture for Random Number Generators - A variable architecture for random number generators is disclosed. In some implementations, the architecture of a random number generator may be varied based on microcontroller-specific data stored on the microcontroller. For example, a random number generator module may be embedded in a microcontroller circuit. The random number generator module may be designed to receive input from data sources in the circuit that contain microcontroller-specific data (e.g., a unique chip identifier, data carried in fuse bits). In some implementations, the architecture of the random number generator module may be adjusted or varied based on the microcontroller-specific data. | 09-13-2012 |
20120179931 | DATA PROCESSING MODULE PROVIDING UNIFORM POWER CONSUMPTION FOR DIGITAL LOGIC - A microcontroller that includes logic to provide a uniform overall power consumption current of parts of the microcontroller generated by sequential element switching is disclosed. For example, the number of sequential elements switching at the triggering edge of the clock is calculated to determine a number of switching elements. The number of switching elements is compared to the number of sequential elements of the circuitry. Additional sequential elements are added in the circuitry and are forced to switch so that the overall number of switching elements equals the number of sequential elements, excluding the additional sequential elements. | 07-12-2012 |
20120161873 | DIFFERENTIAL PAIR WITH CONSTANT OFFSET - A bias current is generated for an unbalanced differential pair that is proportional to the transconductance gain of the differential pair. When the transconductance gain varies (e.g., due to temperature variations), the bias current varies in proportion thereby maintaining a constant offset voltage. In some implementations, a voltage to current converter circuit generates the bias current from a constant reference voltage that is independent of temperature and voltage supply variations (e.g., a bandgap reference voltage). | 06-28-2012 |
20120059975 | PROCESSOR INDEPENDENT LOOP ENTRY CACHE - A memory controller is configured to receive read requests from a processor and return memory words from memory. The memory controller comprises an address comparator and a loop entry cache. The address comparator is configured to determine a difference between a previous read request address and a current read request address. The address comparator is also configured to determine whether the difference is positive and less than a certain address difference and, if so, indicate a limited backwards jump. The loop entry cache is configured to store a current memory word for the current read request address when the address comparator indicates a limited backwards jump. | 03-08-2012 |
20120032262 | ENHANCED HVPMOS - A p-channel LDMOS device with a controlled n-type buried layer (NBL) is disclosed. A Shallow Trench Isolation (STI) oxidation is defined, partially or totally covering the drift region length. The NBL layer, which can be defined with the p-well mask, connects to the n-well diffusion, thus providing an evacuation path for electrons generated by impact ionization. High immunity to the Kirk effect is also achieved, resulting in a significantly improved safe-operating-area (SOA). The addition of the NBL deep inside the drift region supports a space-charge depletion region which increases the RESURF effectiveness, thus improving BV. An optimum NBL implanted dose can be set to ensure fully compensated charge balance among n and p doping in the drift region (charge balance conditions). The p-well implanted dose can be further increased to maintain a charge balance, which leads to an Rdson reduction. | 02-09-2012 |
20110138141 | EXECUTE ONLY ACCESS RIGHTS ON A VON NEUMAN ARCHITECTURES - A microcontroller system, such as a system-on-a-chip integrated circuit, including a processor (e.g., a Von Neumann processor), memory, and a memory protection unit (MPU), where the MPU provides execute-only access rights for one or more protected areas of the memory. The MPU can allow instructions fetched from within a protected area to access data in the protected area while preventing instructions fetched from outside the protected area from accessing data in the protected area. | 06-09-2011 |
20110115560 | DIFFERENTIAL PAIR WITH CONSTANT OFFSET - A bias current is generated for an unbalanced differential pair that is proportional to the transconductance gain of the differential pair. When the transconductance gain varies (e.g., due to temperature variations), the bias current varies in proportion thereby maintaining a constant offset voltage. In some implementations, a voltage to current converter circuit generates the bias current from a constant reference voltage that is independent of temperature and voltage supply variations (e.g., a bandgap reference voltage). | 05-19-2011 |
20110016167 | RANDOMIZED MODULAR POLYNOMIAL REDUCTION METHOD AND HARDWARE THEREFOR - A cryptographically secure, computer hardware-implemented binary finite-field polynomial modular reduction method estimates and randomizes a polynomial quotient used for computation of a polynomial remainder. The randomizing error injected into the approximate polynomial quotient is limited to a few bits, e.g. less than half a word. The computed polynomial remainder is congruent with but a small random multiple of the residue, which can be found by a final strict binary field reduction by the modulus. In addition to a computational unit and operations sequencer, the computing hardware also includes a random or pseudo-random number generator for producing the random polynomial error. The modular reduction method thus resists hardware cryptoanalysis attacks, such as timing and power analysis attacks. | 01-20-2011 |