AMKOR TECHNOLOGY, INC. Patent applications |
Patent application number | Title | Published |
20160141229 | SEMICONDUCTOR PACKAGE WITH SEMICONDUCTOR DIE DIRECTLY ATTACHED TO LEAD FRAME AND METHOD - In one embodiment, a semiconductor package includes a semiconductor die having conductive pads. A lead frame is directly connected to the conductive pads using an electrochemically formed layer or a conductive adhesive layer thereby facilitating an electrical connection between the conductive pads of the semiconductor die and the lead frame without using separate wire bonds or conductive bumps. | 05-19-2016 |
20160118319 | SEMICONDUCTOR PACKAGE AND METHOD THEREFOR - In one embodiment, an electronic package structure includes a lead having a first width. An electronic chip having a conductive bump on a major surface, the conductive bump has a second width greater than the first width. The conductive bump is attached to the lead such that a portion of the conductive bump extends to at least partially surround a side surface of the lead. A molding compound resin encapsulates the electronic chip, the conductive bump, and at least a portion of the lead. The lead is configured so strengthen the joining force between the lead and conductive bump. | 04-28-2016 |
20150371933 | MICRO LEAD FRAME STRUCTURE HAVING REINFORCING PORTIONS AND METHOD - In one embodiment, a micro lead frame structure includes one or more stiffness reinforcing structures formed on leads and/or connecting structures. The stiffness reinforcing structures can be formed by leaving predetermined portions of the micro lead frame at full thickness including, for example, portions of an inner lead, portions of an outer lead, and portions of a connecting bar, combinations thereof, and other structures. The stiffness reinforcing structures are configured to reduce deformation defects and electrical short defects caused by assembly processes. | 12-24-2015 |
20150340332 | COPPER PILLAR SIDEWALL PROTECTION - Methods for copper pillar protection may include forming a metal post over a contact on a semiconductor die, where the metal post comprises a sidewall. A metal cap may be formed on the metal post and may be wider than the width of the metal post. A solder bump may be formed on the metal cap, and a conformal passivation layer may be formed on at least the sidewall of the metal post. The metal cap may be rounded shaped or rectangular shaped in cross-section. The metal post and the metal cap may comprise copper. The metal cap may comprise a copper layer and a nickel layer. The seed metal layer may comprise one or more of titanium, tungsten, and copper. The conformal passivation layer may comprise a nonwettable polymer. Horizontal portions of the conformal passivation layer may be removed utilizing an anisotropic etch such as a plasma etch. | 11-26-2015 |
20150332991 | METHOD OF FORMING A THIN SUBSTRATE CHIP SCALE PACKAGE DEVICE AND STRUCTURE - In one embodiment, a method for forming an electronic package structure includes providing a single unit leadframe having first terminals on a first or top surface. An electronic device is attached to the single unit leadframe and electrically connected to the first terminals. The leadframe, first terminals, and the electronic device are encapsulated with an encapsulating material. Second terminals are then formed by removing portions of a second or bottom surface of the leadframe. In one embodiment, the method can be used to fabricate a thin substrate chip scale package (“tsCSP”) type structure. | 11-19-2015 |
20150303170 | SINGULATED UNIT SUBSTRATE FOR A SEMICONDCUTOR DEVICE - A singulated substrate for a semiconductor device may include a singulated unit substrate comprising circuit patterns on a top surface and a bottom surface of the singulated unit substrate. A semiconductor die may be bonded to the top surface of the singulated unit substrate. An encapsulation layer may encapsulate the semiconductor die and cover the top surface of the singulated unit substrate. The side surfaces of the singulated unit substrate between the top surface and bottom surface of the singulated unit substrate may be coplanar with side surfaces of the encapsulation layer. The semiconductor die may be electrically coupled to the singulated unit substrate utilizing solder bumps. Solder balls may be formed on the circuit patterns on the bottom surface of the singulated unit substrate. An underfill material may be formed between the semiconductor die and the top surface of the singulated unit substrate. | 10-22-2015 |
20150279767 | LEAD FRAME PACKAGE AND METHOD FOR MANUFACTURING THE SAME - In one embodiment, a lead frame package structure includes a lead frame having sides that surround a die paddle and on which a plurality of leads are formed. An electronic chip is attached to the die paddle and a case is attached to the lead frame to seal the leads and the electronic chip. One or more discharge holes are formed on and extending through one or more specific leads and/or on and extending through a predetermined position of the die paddle. The discharge holes are configured to discharge air pressure that forms during the assembly process thereby improving the reliability of the packaged electronic chip. | 10-01-2015 |
20150221570 | THIN SANDWICH EMBEDDED PACKAGE - Methods and systems for a thin sandwich embedded package are disclosed and may include bonding a semiconductor die to a first surface of a substrate, dispensing a bond line on the first surface of the substrate and the die, and bonding an interposer to the substrate and die using the dispensed bond line. The bond line may fill the volume between the interposer and the substrate or may fill the volume between the interposer and the die but not between the interposer and the substrate. A cavity structure may be formed on the interposer and/or substrate, wherein the die may be situated within a cavity formed by the cavity structure when the interposer is bonded to the substrate and die. The cavity structure may comprise solder resist. Contacts may be formed on the cavity structure using low volume pad finish metals to electrically couple the interposer to the substrate. | 08-06-2015 |
20150137384 | SEMICONDUTOR DEVICE WITH THROUGH-SILICON VIA-LESS DEEP WELLS - Methods and systems for a semiconductor device with through-silicon via-less deep wells are disclosed and may include forming a mask pattern on a silicon carrier, etching wells in the silicon carrier, and forming metal contacts in the etched wells, wherein the metal contacts comprise a plurality of deposited metal layers. Redistribution layers may be formed on a subset of the contacts and a dielectric layer may be formed on the silicon carrier and formed redistribution layers. Vias may be formed through the dielectric layer to a second subset of the contacts and second redistribution layers may be formed on the dielectric layer. A semiconductor die may be electrically coupled to the second formed redistribution layers and formed vias. The semiconductor die and top surface of the dielectric layer may be encapsulated and the silicon carrier may be thinned to a thickness of the contacts or may be completely removed. | 05-21-2015 |
20150117654 | APPARATUS AND METHOD FOR TESTING SOUND TRANSDUCERS - In one embodiment, an apparatus for testing sound transducers includes a test socket having at least one acoustic generator and at least one sound monitoring device integrated therein. In one embodiment, the test socket includes a well for holding the sound transducer during test, the well being in communication with the at least one acoustic generator and the at least one sound receiving device. | 04-30-2015 |
20150049421 | ELECTRONIC DEVICE PACKAGE STRUCTURE AND METHOD FABRICATING THE SAME - In one embodiment, an electronic device package structure includes an electronic die having conductive pads on one surface. The one surface is further attached to at least one lead. A conductive layer covers at least one conductive pad and at least portion of the lead thereby electrically connecting the lead to the conductive pad. | 02-19-2015 |
20150021791 | SEMICONDUCTOR DEVICE - Various aspects of the present disclosure provide a semiconductor device and a method for manufacturing thereof, which can facilitate stacking of semiconductor die while saving manufacturing cost. In an example embodiment, the semiconductor device may comprise a first semiconductor die, a second semiconductor die bonded to a top surface of the first semiconductor die, and a redistribution layer electrically connecting the first semiconductor die to the second semiconductor die, wherein the redistribution layer is formed to extend along surrounding side portions of the second semiconductor die. | 01-22-2015 |
20150021751 | SEMICONDUCTOR DEVICE WITH PLATED PILLARS AND LEADS - A semiconductor device with plated pillars and leads is disclosed and may include a semiconductor die comprising a conductive pillar, a conductive lead electrically coupled to the conductive pillar, a metal plating layer covering the conductive lead and conductive pillar, and an encapsulant material encapsulating the semiconductor die and at least a portion of the plating layer. The pillar, lead, and plating layer may comprise copper, for example. The plating layer may fill a gap between the pillar and the lead. A portion of the metal plating layer may, for example, comprise an external lead. The metal plating layer may cover a side surface of the pillar and a top surface, side surface, and at least a portion of a bottom surface of the lead. The metal plating layer may cover side and bottom surfaces of the pillar and top, side, and at least a portion of bottom surfaces of the conductive lead. | 01-22-2015 |
20140327122 | MICRO LEAD FRAME STRUCTURE HAVING REINFORCING PORTIONS AND METHOD - In one embodiment, a micro lead frame structure includes one or more stiffness reinforcing structures formed on leads and/or connecting structures. The stiffness reinforcing structures can be formed by leaving predetermined portions of the micro lead frame at full thickness including, for example, portions of an inner lead, portions of an outer lead, and portions of a connecting bar, combinations thereof, and other structures. The stiffness reinforcing structures are configured to reduce deformation defects and electrical short defects caused by assembly processes. | 11-06-2014 |
20140291844 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - Provided are a semiconductor device having a stably formed structure capable of being electrically connected to a second electronic device without causing damage to the semiconductor device, and a manufacturing method thereof. In one embodiment, the semiconductor device may comprise a semiconductor die, an encapsulation part formed on lateral surfaces of the semiconductor die, a dielectric layer formed on the semiconductor die and the encapsulation part, a redistribution layer passing through a part of the dielectric layer and electrically connected to the semiconductor die, a plurality of conductive balls extending through other parts of the dielectric layer and electrically connected to the redistribution layer where the conductive balls are exposed to an environment outside of the semiconductor device, and conductive vias extending through the encapsulation part and electrically connected to the redistribution layer. | 10-02-2014 |
20140284785 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - Disclosed are a semiconductor device and a manufacturing method thereof, which can achieve miniaturization and improvement in the integration level by forming a substrate using a pattern layer implemented on a wafer in a semiconductor fabrication (FAB) process. In one exemplified embodiment, the manufacturing method of the semiconductor device includes preparing a first semiconductor die including a plurality of through electrodes and a plurality of first conductive pillars, mounting the first semiconductor die to connect the first conductive pillars to the pattern layer provided on a wafer, forming a first encapsulant to cover the pattern layer and the first semiconductor die, mounting a second semiconductor die to electrically connect second conductive pillars provided in the second semiconductor die to the plurality of through electrodes exposed to a second surface of the first semiconductor die, and removing the wafer from a first surface of the pattern layer. | 09-25-2014 |
20140147970 | SEMICONDUCTOR DEVICE USING EMC WAFER SUPPORT SYSTEM AND FABRICATING METHOD THEREOF - Provided are a semiconductor device using, for example, an epoxy molding compound (EMC) wafer support system and a fabricating method thereof, which can, for example, adjust a thickness of the overall package in a final stage of completing the device while shortening a fabricating process and considerably reducing the fabrication cost. An example semiconductor device may comprise a first semiconductor die that comprises a bond pad and a through silicon via (TSV) connected to the bond pad; an interposer comprising a redistribution layer connected to the bond pad or the TSV and formed on the first semiconductor die, a second semiconductor die connected to the redistribution layer of the interposer and positioned on the interposer; an encapsulation unit encapsulating the second semiconductor die, and a solder ball connected to the bond pad or the TSV of the first semiconductor die. | 05-29-2014 |
20140138817 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device including a relatively thin interposer excluding a through silicon hole and a manufacturing method thereof are provided. The method includes forming an interposer on a dummy substrate. The forming of the interposer includes, forming a dielectric layer on the dummy substrate, forming a pattern and a via on the dielectric layer, and forming a seed layer at the pattern and the via of the dielectric layer and forming a redistribution layer and a conductive via on the seed layer. A semiconductor die is connected with the conductive via facing an upper portion of the interposer, and the semiconductor die is encapsulated with an encapsulant. The dummy substrate is removed from the interposer. A bump is connected with the conductive via facing a lower portion of the interposer. | 05-22-2014 |
20140138788 | PACKAGE OF FINGER PRINT SENSOR AND FABRICATING METHOD THEREOF - Various aspects of the present disclosure provide a semiconductor device, for example comprising a finger print sensor, and a method for manufacturing thereof. Various aspects of the present disclosure may, for example, provide an ultra-slim finger print sensor having a thickness of 500 μm or less that does not include a separate printed circuit board (PCB), and a method for manufacturing thereof. | 05-22-2014 |
20140131848 | LAND STRUCTURE FOR SEMICONDUCTOR PACKAGE AND METHOD THEREFOR - In one embodiment, a method for forming a package substrate includes selectively removing portions of a lead frame to form cavities and filling the cavities with a resin layer to define an adhesion pad and a land structure. Top portions of the lead frame are selectively removed to isolate the adhesion pad and the land structure from each other, to expose a top surface of the resin layer, and to form at least one land having a part with a relatively greater size than the size of a respective lower part. | 05-15-2014 |
20140042605 | LEAD FRAME PACKAGE AND METHOD FOR MANUFACTURING THE SAME - In one embodiment, a lead frame package structure includes a lead frame having sides that surround a die paddle and on which a plurality of leads are formed. An electronic chip is attached to the die paddle and a case is attached to the lead frame to seal the leads and the electronic chip. One or more discharge holes are formed on and extending through one or more specific leads and/or on and extending through a predetermined position of the die paddle. The discharge holes are configured to discharge air pressure that forms during the assembly process thereby improving the reliability of the packaged electronic chip. | 02-13-2014 |
20130328192 | SEMICONDUCTOR PACKAGE AND METHOD FOR MANUFACTURING THE SAME - One embodiment provides a semiconductor package by forming a redistribution layer extending from a bonding pad of a semiconductor chip using a photoresist pattern plated with the seed layer. Fabrication of the semiconductor package is relatively simple thereby shortening a manufacturing time and reducing the manufacturing cost, and which can increase an adhered area of input/output terminals and can prevent delamination by connecting and welding the input/output terminals to a pair of redistribution layers. | 12-12-2013 |
20130277815 | METHOD OF FORMING A THIN SUBSTRATE CHIP SCALE PACKAGE DEVICE AND STRUCTURE - In one embodiment, a method for forming an electronic package structure includes providing a single unit leadframe having first terminals on a first or top surface. An electronic device is attached to the single unit leadframe and electrically connected to the first terminals. The leadframe, first terminals, and the electronic device are encapsulated with an encapsulating material. Second terminals are then formed by removing portions of a second or bottom surface of the leadframe. In one embodiment, the method can be used to fabricate a thin substrate chip scale package (“tsCSP”) type structure. | 10-24-2013 |
20130265486 | MOLDED IMAGE SENSOR PACKAGE HAVING LENS HOLDER - An image sensor package includes an image sensor, a window, and a molding, where the molding includes a lens holder extension portion extending upwards from the window. The lens holder extension portion includes a female threaded aperture extending from the window such that the window is exposed through the aperture. A lens is supported in a threaded lens support. The threaded lens support is threaded into the aperture of the lens holder extension portion. The lens is readily adjusted relative to the image sensor by rotating the lens support. | 10-10-2013 |
20130264694 | ELECTRONIC PACKAGE STRUCTURE HAVING EXPOSED LANDS AND METHOD - In one embodiment, a semiconductor device includes a leadframe structure. A semiconductor die is attached to a die pad. Land connect bars are spaced apart from the die pad and a plurality of lands are between the land connect bars and the die pad and are spaced apart therefrom. Insulation members are adhered to the land connect bars and the plurality of lands to hold the land connect bars and the plurality of lands together and to electrically isolate them. An encapsulant covers the semiconductor die and at least portions of the plurality of lands, the die pad, and the land connect bars and further fills spaces between the land connect bars and the plurality of lands. | 10-10-2013 |
20130214402 | SEMICONDUCTOR PACKAGE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor package improves reliability of heat emitting performance by maintaining a heat emitting lid stacked on a top surface of a semiconductor chip at a tightly adhered state. A highly adhesive interface material and a thermal interface material are applied to the top surface of the semiconductor chip. The highly adhesive interface material insures that the heat emitting lid is bonded to the top surface while the thermal interface material insures excellent heat transfer between the top surface and the heat emitting lid. | 08-22-2013 |
20130181335 | LEADFRAME AND SEMICONDUCTOR PACKAGE MADE USING THE LEADFRAME - Metal leadframes, semiconductor packages made using the leadframes, and methods of making the leadframes and packages are disclosed. In one embodiment, the leadframe includes a rectangular frame. A chip pad and a plurality of leads are within the frame. The lower side of the chip pad and the leads includes one or more vertically recessed horizontal surfaces. The upper side of the chip pad may include a groove around a chip mounting region. In a package, the chip pad supports a semiconductor chip electrically connected to the leads. The lower side of the chip pad and leads are exposed at an exterior surface of the package body. Encapsulant material underfills the recessed lower surfaces of the chip pad and leads, thereby locking them to the encapsulant material. A wire may be reliably bonded to the chip pad within the groove formed in the upper side thereof. | 07-18-2013 |
20130154066 | SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD THEREOF - A semiconductor package is presented which has a suitable structure for effectively shielding electromagnetic wave interference (EMI) in a cavity area to which a semiconductor chip is attached. The semiconductor package is assembled such that a lower substrate to which the semiconductor chip is attached is adhered to an EMI shielding & electric I/O body having various types of EMI shielding & electric I/O metal patterns by soldering. Further, the EMI shielding & electric I/O body is adhered to an upper substrate by soldering thereby simplifying assembling of the semiconductor package. | 06-20-2013 |
20130012015 | SEMICONDUCTOR DEVICE FOR IMPROVING ELECTRICAL AND MECHANICAL CONNECTIVITY OF CONDUCTIVE PILLERS AND METHOD THEREFOR - A semiconductor device has a semiconductor die having a first surface and a second surface wherein at least one bond pad is formed on the first surface. A passivation layer is formed on the first surface of the semiconductor device, wherein a central area of the at least one bond is exposed. A seed layer is formed on exposed portions of the bond pad and the passivation layer. A conductive pillar is formed on the seed layer. The conductive pillar has a base portion wherein the base portion has a diameter smaller than the seed layer and a stress relief portion extending from a lateral surface of a lower section of the base portion toward distal ends of the seed layer. A solder layer is formed on the conductive pillar. | 01-10-2013 |