ADVANTEST CORPORATION Patent applications |
Patent application number | Title | Published |
20160133438 | CHARGED PARTICLE BEAM EXPOSURE APPARATUS SUITABLE FOR DRAWING ON LINE PATTERNS, AND EXPOSURE METHOD USING THE SAME - There is provided a charged particle beam exposure apparatus which turns an array beam including a plurality of charged particle beams, being arranged side by side in a line in a direction intersecting line patterns, on and off at predetermined blanking timing, and thus performs irradiation when irradiated positions of the charged particle beams arrive at pattern positions. The charged particle beam exposure apparatus improves data processing control by segmenting a sample provided with line patterns into a plurality of exposure ranges each at a predetermined length in a direction of movement, and performing on-off control of the beams based on a point of time when the array beam passes on a reference position set in the exposure region. | 05-12-2016 |
20160116503 | ELECTRONIC DEVICE HANDLING APPARATUS AND ELECTRONIC DEVICE TESTING APPARATUS - Provided is an electronic device handling apparatus capable of increasing the number of simultaneous measurements while suppressing the increase in cost. An electronic device handling apparatus, which moves bare dies relative to a probe card, includes: a thermal head which includes a plurality of holding regions each of which holds the bare die and has openings; at least one lift unit which is movably held by the thermal head so as to correspond to the holding regions and is able to advance and retreat through the openings; a moving device which moves the thermal head; and a fixed arm which is able to support the one lift unit. | 04-28-2016 |
20160036684 | Method And Apparatus To Provide Both High Speed And Low Speed Signaling From The High Speed Transceivers On An Field Programmable Gate Array - A programmable logic device, such as a field programmable gate array (FPGA), is disclosed that allows for both high speed and low speed signal processing using the existing high speed transceiver. The programmable logic of the device may be programmed to include a sampling logic block that determines the low speed bit patterns from a device under test (DUT). The logic may further include a bit replication logic block that replicates bits such that the output of the device's high speed transceiver looks like a low speed signal to the DUT. The device, therefore, can communicate with the DUT at both the high and low speeds without the need for intermediate hardware. | 02-04-2016 |
20160033574 | Scan Speed Optimization of Input and Output Paths - Disclosed herein is a scan optimizer system and method designed to generate optimal ATE input/output timing with small margin but yielding stable results. Therefore the scan test time is greatly improved. | 02-04-2016 |
20160020765 | SEMICONDUCTOR SWITCH - A semiconductor switch is configured to conduct or cutoff a signal path from its first terminal to its second terminal. An enhancement-type first transistor is arranged between the first terminal and the second terminal. A first bias circuit is connected to apply a gate voltage V | 01-21-2016 |
20160003869 | TEST CARRIER - A test carrier includes a base member on which a first electronic device under test is able to be temporarily mounted, and a second electronic device which is configured to be used to test the first electronic device. The second electronic device is mounted on the base member, and the second electronic device is able to be electrically connected to the first electronic device. | 01-07-2016 |
20150372657 | Switchable Signal Routing Circuit - A switchable signal routing circuit for routing a signal between at least one input port and at least one output port is provided. The ports are connected via variable resistors to a common node, wherein the switchable signal routing circuit is configured to set resistance values of the variable resistors in dependence on a number of active ports. | 12-24-2015 |
20150370248 | System, Methods and Apparatus Using Virtual Appliances in a Semiconductor Test Environment - In one embodiment, a semiconductor test control system includes a computer system having a plurality of hardware resources; a hypervisor installed on the computer system; and a test floor controller installed on the computer system. The hypervisor virtualizes the hardware resources and provides each of at least one virtual appliance with access to a respective virtual set of hardware resources. Each virtual set of hardware resources places its respective virtual appliance in controlling communication with at least a first aspect of a semiconductor test system, thereby enabling the respective virtual appliance to test a respective type of semiconductor device. The test floor controller is in controlling communication with i) at least a second aspect of the semiconductor test system, and ii) each of the at least one virtual appliance. | 12-24-2015 |
20150323451 | DYNAMIC MEASUREMENT OF DENSITY USING TERAHERTZ RADIATION WITH REAL-TIME THICKNESS MEASUREMENT FOR PROCESS CONTROL - A method of determining a density of a roller compacted ribbon is disclosed. The method comprises compacting dry pharmaceutical powder between press rollers of a roller compactor to produce a compact ribbon. The method also comprises determining a thickness at a point on the compact ribbon in a non-invasive manner after it has rolled out from in between the press rollers. Further, the method comprises passing the compact ribbon through a gap in between the terahertz emitter and the terahertz detector. Next, the method comprises determining a refractive index at the point on the compact ribbon using a measurement value from the terahertz emitter and the terahertz detector and a measured value for the thickness at the point. Finally, the method comprises computing a density of the compact ribbon at the point using a value of the refractive index. | 11-12-2015 |
20150276862 | Handler Apparatus and Test Apparatus - Provided is a handler apparatus that conveys a device under test to a test socket, including: a socket for adjustment which, prior to fitting of a device holder holding the device under test to the test socket, fits the device holder; a socket-for-adjustment position detecting section that detects a relative position of the device under test with respect to the socket for adjustment, in a state in which the device holder fits the socket for adjustment; an actuator that adjusts a position of the device under test on the device holder, based on the detected relative position of the device under test; and a conveyer that conveys the device holder, in which a position of the device under test has been adjusted, to fit the test socket. | 10-01-2015 |
20150276858 | TEST APPARATUS AND CIRCUIT SUBSTRATE UNIT - A test apparatus that tests a device under test, comprising first and second test substrates facing each other; test circuits provided respectively on a first substrate surface of the first test substrate facing the second test substrate and a second substrate surface of the second test substrate facing the first test substrate; a first cooling section provided on the first substrate surface of the first test substrate to house the test circuit and to have a cooling medium introduced therein; and a second cooling section provided on the second substrate surface of the second test substrate to house the test circuit and to have a cooling medium introduced therein. The first and second cooling sections include respective contact portions in contact with each other, and each contact portion has a connection opening that connects inside of the first cooling section and inside of the second cooling section to each other. | 10-01-2015 |
20150262705 | STAGED BUFFER CACHING IN A SYSTEM FOR TESTING A DEVICE UNDER TEST - A system for testing a device under test (DUT) can include: a test controller unit that includes a first memory is operable to store a data pattern; a bridge circuit that includes a second memory that is smaller than the first memory, and a functional unit that includes a third memory that is smaller than the second memory. Portions of the data pattern can be selectively transferred from the first memory to the second memory during and for DUT testing operations. The functional circuit can interface with the DUT for testing. Portions of the data pattern can be selectively transferred from the second memory to the third memory for application to the DUT. | 09-17-2015 |
20150255176 | MEMORY TEST ECC AUTO-CORRECTION OF FAILING DATA - A method according to one embodiment of the present invention for evaluating test results for a memory module. The method comprises reviewing contents of a test data stream for one or more sections of the memory module. A first counter is incremented when a defective portion is encountered in the test data stream for a first section of the one or more sections of the memory module. Each defective portion of the first section is marked as good in the test data stream so long as a first counter value is equal to or below a first threshold value. Data from the test data stream identifying defective portions of the first section are stored in an error cache for each remaining defective portion of the first section identified after the first counter passes a first threshold value. | 09-10-2015 |
20150255175 | MEMORY TESTING AND FAILURE DATA FILTERING - A method for evaluating test results for a memory module. Contents of a data stream are reviewed for one or more sections of the memory module. A plurality of counters is incremented when a defective portion is encountered in the data stream for a first section of the memory module. Values of the plurality of counters are compared to corresponding threshold values. Provided two or more counter values are at or above their threshold values, the first section is marked as bad, all defective portions of the first section are removed from the test data stream, and a failure header indicating that the first section is bad is stored and because of which counters in an error cache, otherwise each defective portion of the first section is marked as good in the data stream provided an error correction counter value of the plurality of counter values is equal to or below a first threshold value. Data from the data stream identifying defective portions of the first section are stored in an error cache for each remaining defective portion of the first section identified after the error correction counter value passes the first threshold value. | 09-10-2015 |
20150253378 | DISTRIBUTED POWER SUPPLY ARCHITECTURE IN AUTOMATIC TEST EQUIPMENT - An apparatus for providing a distributed and scalable number of power supplies used in automatic test equipment. The apparatus includes at least one Pin Electronics (PE) module comprising a plurality of PE channels. The apparatus includes at least one programmable power supply (PPS) module comprising a plurality of programmable power supply channels, wherein the at least one PPS module is remote from the at least one PE module. That apparatus includes a test site controller executing a test program comprising a plurality of test instructions delivered over the plurality of Pin Electronics (PE) channels and the plurality of programmable power supply (PPS) channels in order to test a plurality of devices under test (DUTs) in parallel. | 09-10-2015 |
20150243482 | ELECTRON BEAM EXPOSURE METHOD - An electron beam exposure method includes the steps of: preparing an exposure mask having a plurality of opening patterns formed by dividing a drawing object pattern into exposable regions; and drawing the drawing object pattern by performing exposure with an electron beam passing through the opening patterns of the exposure mask. Each end portion serving as a joint in each opening pattern of the exposure mask is provided with a joining portion tapered in a width of the opening pattern. The exposure is performed in such a way that portions drawn through adjacent joining portions overlap each other. | 08-27-2015 |
20150243480 | CHARGED PARTICLE BEAM EXPOSURE APPARATUS AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - The invention relates to a charged particle beam exposure apparatus configured to expose cut patterns or via patterns on a substrate having a plurality of line patterns | 08-27-2015 |
20150243370 | TESTING MEMORY DEVICES WITH DISTRIBUTED PROCESSING OPERATIONS - ATE performs testing of memory devices with distributed processing operations. A redundancy analysis (RA) system has a first test site processor (TSP), operable for controlling a testing routine over multiple DUTs and analyzing redundancy data returned from a first of the DUTs. The RA has at least a second TSP, operable for analyzing redundancy data returned from a second of the DUTs. The RA may have one or more additional TSPs, each operable for analyzing redundancy data returned from an additional DUT. Controlling the testing routine includes directing the RA in each of the first and second (and any of the additional) TSPs. | 08-27-2015 |
20150243369 | TESTING MEMORY DEVICES WITH PARALLEL PROCESSING OPERATIONS - An ATE system performs RA over NAND flash memory DUTs. A first UBM captures fresh failure related data from a DUT. A second UBM transmits existing failure related data. A fail engine accesses the stored existing failure related data and generates a failure list based thereon. The storing and the accessing the existing failure related data, and/or the generating the failure list, are performed in parallel contemporaneously in relation to the capturing the fresh data. The generated failure list is queued. A failure processor, which may be operable for controlling the capturing, computes a redundancy analysis based on the queued failure list. The first and second UBMs then ping-pong operably. | 08-27-2015 |
20150241346 | LIGHT MEASUREMENT APPARATUS, METHOD, PROGRAM AND RECORDING MEDIUM - A light measurement apparatus includes a master laser, a slave laser, an illumination light pulse, and a signal-under-measurement generator. The master laser generates as an output a master laser light pulse, and the slave laser generates as an output a slave laser light pulse having a repetition frequency or a phase different from that of the master laser light pulse. The illumination light pulse generator receives the master laser light pulse and generates as an output an illumination light pulse, and the signal-under-measurement generator, at a point in time when receiving a light pulse under measurement obtained by illuminating the object under measurement with the illumination light pulse and further the slave laser light pulse, generates as an output a signal under measurement according to a power of the light pulse under measurement. The apparatus corrects an error in a measurement of the signal under measurement. | 08-27-2015 |
20150233967 | INTEGRATED COOLING SYSTEM FOR ELECTRONICS TESTING APPARATUS - Example features or aspects of the present invention are described in relation to a small, quiet integrated cooling system for an apparatus for testing electronic devices. Characteristics of the test apparatus including a low noise output, low power consumption and a compact size with a small spatial and volume footprint are selected for deployment and use in a an office like environment. The test apparatus comprises a chassis frame and a cooler frame disposed within the chassis frame and thus integrated within the test apparatus, which has a reduced form factor suitable for the in-office deployment. Embodiments offer the ability to maintain the working fluid at a constant temperature | 08-20-2015 |
20150203300 | ELECTRONIC COMPONENT TRANSFER SHUTTLE - There is provided an electronic device transfer apparatus which has an excellent capacity of transferring DUTs between trays. | 07-23-2015 |
20150200074 | CHARGED PARTICLE BEAM EXPOSURE APPARATUS - Provided is a charged particle beam exposure apparatus configured as follows. An electron beam emitted from an electron gun is deformed by an asymmetric illumination optical system to have an elongated section. The electron beam is then applied to a beam shaping aperture plate provided with a plurality of apertures arranged in a line, thereby generating a plurality of electron beams. Exposure of a predetermined pattern is performed on a semiconductor substrate by moving a stage device in a direction orthogonal to line patterns on the semiconductor substrate and turning the plurality of electron beams on or off in synchronization with the movement of the stage device by use of a blanker plate and a final aperture plate. | 07-16-2015 |
20150194956 | INTEGRATED RF MEMS ON ATE LOADBOARDS FOR SMART SELF RF MATCHING - In a testing device, a method for implementing automatic RF port testing. The method includes attaching a device under test having a plurality of RF pins to a load board, dynamically tuning a plurality of RF ports of the load board to the plurality of RF pins, and automatically matching the plurality of RF ports to the plurality of RF pins with respect to impedance. The method further includes implementing an RF port testing process on the device under test. | 07-09-2015 |
20150194786 | PULSE LIGHT SOURCE, AND METHOD FOR STABLY CONTROLLING PHASE DIFFERENCE BETWEEN PULSE LASER LIGHTS - A pulse light source includes: a master laser that outputs a master laser light pulse whose repetition frequency is controlled to a predetermined value; a slave laser that outputs a slave laser light pulse; a phase comparator that detects a phase difference between an electric signal having a frequency of the predetermined value, and an electric signal based on a light intensity of the slave laser light pulse; a loop filter; an adder that adds a repetition frequency control signal having a certain repetition cycle, to an output from the loop filter; and a phase comparator that measures a pulse phase difference which is a phase difference between the master laser light pulse and the slave laser light pulse. A magnitude of the repetition frequency control signal is controlled such that the measured pulse phase difference matches with a target value of the pulse phase difference. | 07-09-2015 |
20150180287 | WIRELESS POWER RECEIVING APPARATUS - A first switch is arranged between one end of a reception antenna and one end of a load. A second switch is arranged between the aforementioned one end of the reception antenna and the other end thereof. A switch control circuit controls switching on and off the first switch and the second switch. The switch control circuit is structured to change the ratio of the on time of the first switch with respect to the period of an electric power signal. | 06-25-2015 |
20150162891 | LUMPED ELEMENT RADIO FREQUENCY TUNING CALIBRATION PROCESS - A preferred method for efficiently tuning RF ports while avoiding conventional labor intensive, step-by-step processes is disclosed. The method may use at least three tuning blocks (comprised of capacitors and inductors) in a series topology and at least three tuning blocks in a shunt topology. These tuning blocks will yield two circles that can be charted on the Smith chart. Those circles may then be centered along the centerline of the Smith chart to adjust for latency, and then expanded to adjust for the losses. Once those circles have been expanded, the circle (either series or shunt) that encompasses one the Smith chart reference circles is used and the traditional Smith chart methodology can be used to tune the RF port. | 06-11-2015 |
20150153389 | SOCKET AND ELECTRONIC DEVICE TEST APPARATUS - A socket is electrically connected to a test carrier. The test carrier includes: a film-shaped first member on which at least one internal terminal, which contacts at least one electrode of an electronic device, is provided; and at least one external terminal which is electrically connected to the internal terminal. The socket includes: at least one contactor which contacts the external terminal; and a first pusher which pushes a portion of the first member where the internal terminal is provided and a portion of the first member surrounding the internal terminal. The first pusher has an elastic member which becomes softer in stages or gradually with distance to the first member. | 06-04-2015 |
20150153388 | SOCKET AND ELECTRONIC DEVICE TEST APPARATUS - A socket is electrically connected to a test carrier. The test carrier includes a film-shaped first member on which at least one internal terminal, which contacts at least one electrode of an electronic device, is provided; and at least one external terminal which is electrically connected to the internal terminal. The socket includes: at least one contactor which contacts the external terminal; and a first pusher which pushes a portion of the first member where the internal terminal is provided and a portion of the first member surrounding the internal terminal. The first pusher includes: a bag member which has a sealed space within the bag member; and a fluid which is housed in the sealed space. | 06-04-2015 |
20150137839 | FLEXIBLE TEST SITE SYNCHRONIZATION - A method for performing test site synchronization within automated test equipment (ATE) is presented. The method comprises controlling a plurality of test program controllers (TPCs) using a plurality of bridge controllers (BCs), wherein each TPC can initiate multiple asynchronous events. For an asynchronous event initiated by a TPC, raising a busy flag while the asynchronous event is not yet complete and de-asserting the busy flag when the asynchronous event is complete, wherein the asynchronous event corresponds to a task requiring an indeterminate amount of time. It also comprises generating a busy signal in the first BCs in response to receiving a busy flag from any of the plurality of TPCs, wherein the busy signal remains asserted while any of the plurality of TPCs asserts a busy flag. Finally, it comprises transmitting the busy signal to the plurality of TPCs, wherein the TPCs use the busy signal to synchronize operations. | 05-21-2015 |
20150135026 | SEAMLESS FAIL ANALYSIS WITH MEMORY EFFICIENT STORAGE OF FAIL LISTS - A method for testing memory devices under test (DUTs) using automated test equipment (ATE) is presented. The method comprises retrieving a portion of raw test data from a memory device under test (DUT). It also comprises comparing the portion of raw test data with expected test data to determine failure information, wherein the failure information comprises information regarding failing bits generated by the memory DUT. Next, the method comprises utilizing paging to transfer data comprising the failure information to a filtering module and filtering out the failure information from transferred data using the filtering module. Further, it comprises updating a fail list using the failure information, wherein the fail list comprises address information for respective failing bits within the memory DUT. Finally, it comprises repeating all the prior steps for the next block of raw test data. | 05-14-2015 |
20150130494 | TEST CARRIER - A test carrier includes a base member and a cover member. The base member includes a multi-layer board including a wiring line that is electrically connected to a die and a base film that supports the multi-layer board. The cover member includes a frame-shaped cover frame having an opening formed therein. The size of the multi-layer board is larger than the size of the die and is smaller than the size of the opening in a direction along a surface that is opposite to the die. | 05-14-2015 |
20150130493 | ELECTRONIC DEVICE TESTING APPARATUS, ELECTRONIC DEVICE HOUSING APPARATUS, ELECTRONIC DEVICE RETRIEVING APPARATUS, AND ELECTRONIC DEVICE TESTING METHOD - An electronic device testing apparatus includes a housing unit which disassembles an empty test carrier and assembles the test carrier while housing an untested die in the test carrier, a test unit which tests the die housed in the test carrier, and a retrieving unit which disassembles the test carrier, retrieves the tested die from the test carrier, and reassembles the empty test carrier. | 05-14-2015 |
20150130492 | TEST CARRIER - A test carrier includes a base member that holds a die and a cover member. The base member includes a board having a wiring line that is electrically connected to the die. The wiring line includes a wiring line and a resistive portion having a resistance value that is higher than the resistance value of the wiring line. | 05-14-2015 |
20150127986 | TEST PROGRAM AND TEST SYSTEM - A test program allows an information technology equipment connected to a tester hardware to control the tester hardware. The tester hardware is configured to be capable of changing at least a part of its functions according to configuration data stored in rewritable nonvolatile memory. The test program is configured as a combination of a control program and a test algorithm module. The test program comprises: a module that acquires the configuration data from the nonvolatile memory of the tester hardware and a module that judges whether or not a storage device holds a test algorithm module that can be used together with the configuration data. | 05-07-2015 |
20150122036 | PHOTOACOUSTIC WAVE MEASUREMENT DEVICE - A photoacoustic wave measurement device according to the present invention includes: an optical fiber that outputs pulsed light; an external spacer that is disposed between a pulsed-light output end of the optical fiber and a measurement object, and which is adapted to allow the pulsed light to pass therethrough; a piezoelectric element that receives a photoacoustic wave generated by the pulsed light from the measurement object and converts the photoacoustic wave into an electric signal; and a spacer that is disposed between the external spacer and the piezoelectric element, and which is adapted to allow the photoacoustic wave to pass therethrough. The piezoelectric element is farther from the measurement object than the pulsed-light output end. A part of the optical fiber is disposed within the spacer. | 05-07-2015 |
20150102832 | CARRIER DISASSEMBLING APPARATUS, ELECTRONIC DEVICE HOUSING APPARATUS, ELECTRONIC DEVICE RETRIEVING APPARATUS, AND ELECTRONIC DEVICE TESTING APPARATUS - A carrier disassembling apparatus which disassembles a test carrier including a base member and a cover member coming into close contact with each other, includes: a first reversing arm which sucks and holds the cover member; and a disassembly table which sucks and holds the base member. The first reversing arm can approach and separate from the disassembly table. The first reversing arm includes a first contract surface which comes into contact with the cover member. The first contract surface includes a protrusion which protrudes toward the cover member. | 04-16-2015 |
20150066417 | TEST SYSTEM - A server stores multiple configuration data. A tester hardware is configured to be capable of changing at least a part of its functions according to configuration data stored in rewritable nonvolatile memory, to supply a power supply voltage to a DUT, to transmit a signal to the DUT, and to receive a signal from the DUT. An information technology equipment is configured such that, (i) when the test system is set up, the information technology equipment acquires the configuration data from the server according to the user's input, and writes the configuration data to the nonvolatile memory. Furthermore, the information technology equipment is configured such that, (ii) when the DUT is tested, the information technology equipment executes a test program so as to control the tester hardware, and to process data acquired by the tester hardware. | 03-05-2015 |
20150061717 | TEST CARRIER, DEFECT DETERMINATION APPARATUS, AND DEFECT DETERMINATION METHOD - A test carrier that temporarily accommodates a die includes: a first wiring pattern that electrically connects an external terminal of the test carrier and a TSV of the die; and a second wiring pattern that electrically connects the TSVs. | 03-05-2015 |
20150058677 | DISTRIBUTED PIN MAP MEMORY - In a testing device, a method for implementing distributed pin mapping. The method includes receiving a request from a plurality of CPUs to access a pin map memory at each of a plurality of bridges, implementing accesses to the pin map memories locally at each of the plurality of bridges, and using pin map data from the accesses to the plurality of CPUs to enable access to testing device resources. | 02-26-2015 |
20150058671 | TEST PROGRAM - A test program allows an information technology equipment connected to a tester hardware to control the tester hardware. The tester hardware is configured to be capable of changing at least a part of its functions according to configuration data stored in rewritable nonvolatile memory. The test program is configured as a combination of a control program and a test algorithm module. The test program comprises: a module that receives a selection instruction for selecting a test item specified by the user from among test items that correspond to the test algorithm modules held by the storage device; a module that receives a test condition required to execute the selected test item; and a module that controls the tester hardware so as to supply a signal to a device under test according to the test algorithm and test condition, and to receive a signal from the device under test. | 02-26-2015 |
20150058670 | TEST PROGRAM - A test program allows an information technology equipment connected to a tester hardware to control the tester hardware. The tester hardware is configured to be capable of changing at least a part of its functions according to configuration data stored in rewritable nonvolatile memory. The test program comprises: an operation flow display control module that displays an operation flow on a display device of an information technology equipment in a form that allows the user to select a desired step, and an input screen display control module that displays an input screen on the display device according to the step selected from among the operation flow. | 02-26-2015 |
20150052409 | FLEXIBLE INTERRUPT GENERATION MECHANISM - In a testing device, a method for implementing efficient interrupt routing. The method includes receiving an interrupt from a plurality of interrupt causes, consulting an interrupt routing table to determine an output interrupt vector, and forwarding the output interrupt vector to one or more of a plurality of different CPUs in accordance with the interrupt routing table. | 02-19-2015 |
20150051863 | TEST SYSTEM - A server stores multiple configuration data. A tester hardware is configured to be capable of changing at least a part of its functions according to configuration data stored in rewritable memory, to supply a power supply voltage to a DUT, to transmit a signal to the DUT, and to receive a signal from the DUT. An information technology equipment is configured such that, (i) when the test system is set up, the information technology equipment acquires the configuration data from the server according to the user's input, and writes the configuration data to the memory. Furthermore, the information technology equipment is configured such that, (ii) when the DUT is tested, the information technology equipment executes a test program so as to control the tester hardware, and to process data acquired by the tester hardware. | 02-19-2015 |
20150028908 | HIGH SPEED TESTER COMMUNICATION INTERFACE BETWEEN TEST SLICE AND TRAYS - A tester system is disclosed. The tester system comprises a tester module operable to generate test signals for testing a plurality of DUTs. It also comprises a plurality of cables operable to communicatively couple the tester module with a tray comprising the plurality of DUTs through a thermal chamber wall interface. Further, it comprises a plurality of connectors in contact with the tray, wherein the plurality of connectors is operable to provide an interface between the plurality of cables and conductive traces on the tray, and further wherein each of the plurality of connectors is operable to pass a respective subset of the test signals to each DUT on the tray via the conductive traces. | 01-29-2015 |
20150028891 | IMPEDANCE MEASUREMENT APPARATUS - A measurement auxiliary circuit is configured to form a resonance circuit together with a detection target. An ATAC is coupled with the resonance circuit. A signal generator applies an AC probe signal V | 01-29-2015 |
20150015087 | WIRELESS POWER TRANSMITTING APPARATUS AND WIRELESS POWER SUPPLY SYSTEM - A wireless power transmitting apparatus transmits an electric power signal comprising any one from among an electric field, a magnetic field, and an electromagnetic field to a wireless power receiving apparatus. A reflector coil is arranged at a distance from a radiation coil. A driving power supply supplies a driving current to the radiation coil. A first phase control circuit controls the phase of the current that flows through the reflector coil so as to stabilize, to a predetermined value, the phase difference between the current that flows through the reflector coil and the current that flows through the radiation coil. | 01-15-2015 |
20140361790 | DRIVE CIRCUIT, SWITCH APPARATUS, AND TEST APPARATUS - Provided is a test apparatus, a switch apparatus, and a drive circuit comprising a current source having one end thereof connected to a reference potential; a first switch connected between the current source and a first voltage source that outputs a first power supply voltage; a first output terminal that outputs a voltage between the first switch and the first voltage source; a power supply section that outputs a second power supply voltage when the first switch is ON and outputs a third power supply voltage, which is lower than the second power supply voltage, when the first switch is OFF; a second switch connected between the power supply section and the current source; and a second output terminal that outputs a voltage between the second switch and the power supply section. | 12-11-2014 |
20140361636 | WIRELESS POWER RECEIVING APPARATUS - A wireless power transmitting apparatus transmits an electric power signal comprising any one from among an electric field, a magnetic field, and an electromagnetic field to a wireless power receiving apparatus. A transmission antenna includes a transmission coil. An automatic tuning assist circuit is coupled in series with the transmission antenna. A power supply applies an AC driving voltage across both terminals of a series circuit that comprises the transmission antenna and the automatic tuning assist circuit. A first controller switches on and off multiple switches in synchronization with the driving voltage. A voltage monitoring unit monitors the voltage that develops at an auxiliary capacitor. | 12-11-2014 |
20140359361 | TEST SYSTEM - A server stores multiple configuration data which respectively provide different functions to a test system. A tester hardware is configured to be capable of changing at least a part of its functions according to the configuration data stored in nonvolatile memory included in the tester hardware. A control program is installed on an information processing apparatus. The control program provides the information processing apparatus with (i) a function of displaying multiple configuration data candidates on a display when the test system is set up, and (ii) a function of writing the configuration data selected by the user to the nonvolatile memory of the tester hardware. | 12-04-2014 |
20140347084 | LOW OVERDRIVE PROBES WITH HIGH OVERDRIVE SUBSTRATE - A method for testing a semiconductor device is disclosed. The method comprises positioning a probe card comprising a plurality of probes above the semiconductor device and moving the probe card in a vertical direction towards the semiconductor device. The plurality of probes are moving in a vertical direction towards a plurality of electrical structures of the semiconductor device until each probe of the plurality of probes has made mechanical contact with a corresponding electrical structure of the plurality of electrical structures with a minimum quantity of force. The each probe of the plurality of probes absorbs a portion of vertical overdrive after contacting their corresponding electrical structures. The probe card absorbs any remaining vertical overdrive. The vertical overdrive is a continuing vertical movement of the plurality of probes after a first probe of the plurality of probes mechanically contacts a first corresponding electrical structure. | 11-27-2014 |
20140324378 | AUTOMATED GENERATION OF A TEST CLASS PRE-HEADER FROM AN INTERACTIVE GRAPHICAL USER INTERFACE - A method for performing tests using automated test equipment (ATE) is presented. The method comprises obtaining information concerning a test class using a graphical user interface. Further, it comprises generating a first header file automatically, wherein the first header file comprises the information concerning the test class. Next, it comprises importing the first header file into a test plan operable to execute using a tester operating system wherein the test plan comprises instances of the test class. It further comprises, generating a second header file from the first header file automatically, wherein the second header file is a header file for the test class. The method also comprises validating the test plan using the tester operating system. Finally, the method comprises loading the test plan and a compiled module onto the tester operating system for execution, wherein the compiled module is a compiled translation of the test class. | 10-30-2014 |
20140312926 | TESTING STACKED DEVICES - Testing stacked devices. In accordance with a first method embodiment, a primary circuit assembly is accessed from a first circuit assembly carrier. The primary circuit assembly is placed into a test fixture. A secondary circuit assembly is accessed from a second circuit assembly carrier. The secondary circuit assembly is placed into the test fixture on top of the primary circuit assembly. The primary circuit assembly is tested in conjunction with said secondary circuit assembly while coupled together. | 10-23-2014 |
20140312225 | DEFECT INSPECTION APPARATUS AND DEFECT INSPECTION METHOD - There is provided a defect inspection apparatus including: an electron scanning unit configured to scan a surface of a sample with an electron beam; a plurality of detectors arranged around an optical axis of the electron beam and configured to detect electrons emitted from the surface of the sample by scanning the electron beam; a signal processing unit configured to generate image data of the surface of the sample based on detection signals from the detectors; an analysis unit configured to detect a defect due to irregularities of the surface of the sample based on the image data; and a control unit configured to control a scanning speed of the electron beam depending on the type of the sample. | 10-23-2014 |
20140312224 | PATTERN INSPECTION METHOD AND PATTERN INSPECTION APPARATUS - A first differential image of a defect observation region including an observation target pattern is generated by a differential value between signals from electron detectors arranged in a direction of edges of the observation target pattern. A three-dimensional shape of a defect is obtained by subjecting the first differential image to integral process. Subsequently, a second differential image of a reference observation region, including a reference pattern having the same shape as the observation target pattern is generated by a differential value between signals from electron detectors arranged in a direction orthogonal to edges of the reference pattern. A three-dimensional shape of the reference pattern is obtained by subjecting the second differential image to the integral process. Then, a three-dimensional shape of the observation target pattern including the defect is obtained by combining the three-dimensional shapes of the defect and the reference pattern together. | 10-23-2014 |
20140310693 | IMPLEMENTING EDIT AND UPDATE FUNCTIONALITY WITHIN A DEVELOPMENT ENVIRONMENT USED TO COMPILE TEST PLANS FOR AUTOMATED SEMICONDUCTOR DEVICE TESTING - A method for debugging test procedures for automated device testing is disclosed. The method comprises receiving a command to update at least one modified test procedure modified during a first debugging session and saving state information for a test plan, wherein the state information comprises information regarding a breakpoint entry location, and wherein the modified test procedure is invoked within the test plan. The method subsequently comprises suspending execution of the test plan and unloading the modified test procedure. It also comprises compiling the modified test procedure to produce a compiled file and then reloading the test procedure into the test plan using the compiled file. Finally, it comprises resuming execution of the modified test procedure in a second debugging session and breaking the execution during the second debugging session at a breakpoint corresponding to the breakpoint entry location. | 10-16-2014 |
20140285367 | CURRENT COMPENSATION CIRCUIT - A first circuit operates in synchronization with a first clock having a first frequency, and generates N parallel data sets for every cycle period of the first clock. An interface circuit time-division multiplexes the N data sets received from the first circuit. A second circuit processes the N data set thus time-division multiplexed, in synchronization with a second clock having a second frequency which is N times the first frequency. A judgment unit judges whether or not the N data sets are effective data which instructs a flip-flop group, configured as a state holding element included in the second circuit, to generate an effective state transition. In a cycle period in which the N data sets are ineffective, a data replacement unit replaces at least a part of the N data sets with current compensation data D | 09-25-2014 |
20140253155 | ADAPTIVE THERMAL CONTROL - An adaptive thermal control system maintains and regulates an accurate and stable thermal environment for a device under test. The adaptive thermal control system includes (i) pre-trigger communications from automatic test equipment (ATE) to automatic thermal control (ATC) allowing slow-responding ATC to start responding to an imminent thermal change before the thermal change occurs, (ii) a control profile which indicates to the ATC, prior to anticipated thermal change, that a change is imminent and the nature of the change over time. The generation and fine-tuning of the control profile can be done by two different methods (i) with the semi-automatic approach the tester does some pre-tests in order to determine a typical response profile which the test program then adjusts using adaptive techniques, (ii) With the fully automatic adaptive circuitries same typical response profile is algorithmically adjusted and utilized to control the ATC. | 09-11-2014 |
20140244204 | TESTER WITH ACCELERATION FOR PACKET BUILDING WITHIN A FPGA BLOCK - A method for testing using an automated test equipment is presented. The method comprises transmitting instructions for performing an automated test from a system controller to a tester processor, wherein the instructions comprise parameters for a descriptor module. The method also comprises programming a reconfigurable circuit for implementing the descriptor module onto an instantiated FPGA block coupled to the tester processor. Further, the method comprises interpreting the parameters from the descriptor module using the reconfigurable circuit, wherein the parameters control execution of a plurality of test operations on a DUT coupled to the instantiated FPGA block. Additionally, the method comprises constructing at least one packet in accordance with the parameters, wherein each one of the at least one packet comprises a command for executing a test operation on the DUT. Finally, the method comprises performing a handshake with the DUT to route the at least one packet to the DUT. | 08-28-2014 |
20140237292 | GUI IMPLEMENTATIONS ON CENTRAL CONTROLLER COMPUTER SYSTEM FOR SUPPORTING PROTOCOL INDEPENDENT DEVICE TESTING - A method for performing tests using automated test equipment (ATE) is presented. The method comprises obtaining a protocol selection for programming a programmable tester module using a graphical user interface (GUI). Further, the method comprises configuring the programmable tester module with a communication protocol for application to at least one device under test (DUT), wherein the at least one DUT is communicatively coupled to the programmable tester module. Also the method comprises providing a menu of tests associated with the communication protocol using the GUI and obtaining a program flow using the GUI, wherein the program flow comprises a sequence of tests chosen from the menu of tests. Finally, the method comprises transmitting instructions to the programmable tester module for executing the program flow. | 08-21-2014 |
20140237291 | USING SHARED PINS IN A CONCURRENT TEST EXECUTION ENVIRONMENT - A method for using shared pins in a concurrent test execution environment is disclosed. The method relates to scheduling tests in concurrently executing test flows for automated test equipment (ATE) in a way so that resources can be shared between the test flows. The method comprises determining if any of a plurality of splits used by a first test contains at least one resource that is shared, wherein the first test and a second test are sequenced for execution in two separate concurrently executing test flows. The method further comprises determining if the first test should execute before the second test if the split is associated with resources required by both the second and first tests. Finally the method comprises reserving the split containing the at least one shared resource for access by the first test before beginning execution of the first test. | 08-21-2014 |
20140236526 | TESTER WITH MIXED PROTOCOL ENGINE IN A FPGA BLOCK - Automated test equipment capable of performing a high-speed test of semiconductor devices is presented. The automated test equipment comprises a system controller for controlling a test program, wherein the system controller is coupled to a bus. The tester system further comprises a plurality of modules also coupled to the bus, where each module is operable to test a plurality of DUTs. Each of the modules comprises a tester processor coupled to the bus and a plurality of configurable blocks communicatively coupled to the tester processor. Each of the configurable blocks is operable to communicate with an associated DUT and further operable to be programmed with a communication protocol for communicating test data to and from said associated device under test. | 08-21-2014 |
20140236525 | TEST ARCHITECTURE HAVING MULTIPLE FPGA BASED HARDWARE ACCELERATOR BLOCKS FOR TESTING MULTIPLE DUTS INDEPENDENTLY - Automated test equipment (ATE) capable of performing a test of semiconductor devices is presented. The ATE comprises a computer system comprising a system controller communicatively coupled to a tester processor. The system controller is operable to transmit instructions to the processor and the processor is operable to generate commands and data from the instructions for coordinating testing of a plurality of devices under test (DUTs). The ATE further comprises a plurality of FPGA components communicatively coupled to the processor via a bus. Each of the FPGA components comprises at least one hardware accelerator circuit operable to internally generate commands and data transparently from the processor for testing one of the DUTs. Additionally, the tester processor is configured to operate in one of several functional modes, wherein the functional modes are configured to allocate functionality for generating commands and data between the processor and the FPGA components. | 08-21-2014 |
20140236524 | TESTER WITH ACCELERATION ON MEMORY AND ACCELERATION FOR AUTOMATIC PATTERN GENERATION WITHIN A FPGA BLOCK - Automated test equipment capable of performing a high-speed test of semiconductor devices is presented. The automated test equipment apparatus comprises a computer system comprising a tester processor, wherein the tester processor is communicatively coupled to a plurality of FPGA components. Each of the plurality of FPGA components is coupled to a memory module and comprises: an upstream port operable to receive commands and data from the tester processor; a downstream port operable to communicate with a respective DUT from a plurality of DUTs; and a plurality of hardware accelerator circuits, wherein each of the accelerator circuits is configured to communicate with one of the plurality of DUTs. Each of the plurality of hardware accelerator circuits comprises a pattern generator circuit configurable to automatically generate test pattern data to be written to the one of the plurality of DUTs and a comparator circuit configured to compare data read from the one of the plurality of DUTs with test pattern data written to the one of the plurality of DUTs | 08-21-2014 |
20140197846 | DETECTING APPARATUS, WAFER AND ELECTRONIC DEVICE - Provided is a detection apparatus that detects process variation in a plurality of comparators that each output a comparison result obtained by comparing a signal level of an input signal to a reference level, the detection apparatus comprising a signal input section that inputs the input signal and the reference level in common to the comparators, and sequentially changes the signal level of the input signal; and a detecting section that detects, for each signal level, a number of comparison results that indicate a predetermined result, from among the comparison results of the comparators, and detects the process variation based on a distribution of the number of comparison results that indicate the predetermined result. | 07-17-2014 |
20140188436 | TEST APPARATUS AND TEST METHOD - Provided is a test apparatus that tests a device under test, comprising a plurality of comparators that each receive a signal under measurement output by the device under test, have a common reference level set therein, and compare a signal level of the signal under measurement to the reference level; and a signal processing section that generates a single result signal based on the plurality of comparison results output by the comparators. Also provided is a test method using the test apparatus. | 07-03-2014 |
20140184194 | MEASUREMENT APPARATUS AND ELECTRONIC DEVICE - Provided is a measurement apparatus that measures an input signal, comprising a plurality of first comparators that each receive the input signal, have a common first reference level set therein, and compare a signal level of the input signal to the first reference level; and a level-crossing timing detecting section that detects a level-crossing timing at which the signal level crosses the first reference level, based on comparison results of the first comparators. | 07-03-2014 |
20140183972 | WIRELESS POWER TRANSMITTER AND WIRELESS POWER RECEIVER - An automatic tuning assist circuit is coupled with a transmission antenna. The automatic tuning assist circuit injects a correction current into, or otherwise draws the correction current from, the transmission antenna. An H-bridge circuit is arranged between a first terminal and a second terminal coupled with the transmission antenna. The H-bridge circuit is switched on and off with a frequency that is equal to the frequency of a driving voltage. A third auxiliary coil is arranged between the output terminals of the H-bridge circuit. | 07-03-2014 |
20140183971 | WIRELESS POWER TRANSMITTER AND WIRELESS POWER RECEIVER - An automatic tuning assist circuit is coupled with a transmission antenna. The transmission antenna injects a first correction current into, or otherwise draws the first correction current from, the transmission antenna. In the first state, the first auxiliary coil is coupled with the transmission antenna. In this state, the first correction current I | 07-03-2014 |
20140168652 | REFLECTION MEASUREMENT APPARATUS - Provided is a light beam incident device including an off-axis parabolic mirror that receives parallel light beams and converges the parallel light beams at one point on an object to be measured, and an incident-side light reception surface of a mirror that feeds the parallel light beams to the off-axis parabolic mirror. An angle (incident angle) between the object to be measured and converged light beams obtained by converging the parallel light beams changes in accordance with a light reception portion at which the off-axis parabolic mirror receives the parallel light beams. The incident side light reception surface of the mirror can change the light reception portion by moving with respect to the off-axis parabolic mirror. | 06-19-2014 |
20140166893 | ELECTROMAGNETIC LENS FOR ELECTRON BEAM EXPOSURE APPARATUS - There is provided an electromagnetic lens which includes an electromagnetic coil wound to be rotationally symmetrical about an optical axis of an electron beam, and a pole piece covering the electromagnetic coil, in which: a gap is integrally formed in either one of an inner wall formed at an inner circumference side of the pole piece and a lower end wall formed in an end portion at an emission side of the electron beam, or a boundary portion between the two walls; the inner wall is formed to be thinnest at a portion close to the gap and to gradually become thicker as a distance from the gap increases; and the electromagnetic lens is formed such that a width in a radial direction thereof is more increased as being closer to the gap along with the change of the thickness of the inner wall. | 06-19-2014 |
20140160270 | CORRECTION APPARATUS, PROBE APPARATUS, AND TEST APPARATUS - In order to decrease the time needed to correct misalignment when holding an object with positional accuracy and transport the object, provided is a correction apparatus that corrects misalignment of a transported object at a transport destination, comprising a first sensor that is secured to a transporting section transporting the object; and a correction control section that detects a first offset between the transporting section and the first sensor, while the object transported to the transport destination is positioned at the transport destination, by using the first sensor to detect a position of a first reference point provided to correspond to a target position at the transport destination. Also provided is a probe apparatus and a test apparatus. | 06-12-2014 |
20140152119 | RELAY DEVICE OF WIRELESS POWER TRANSMISSION SYSTEM - A relay antenna includes a power relay coil. An automatic tuning assist circuit is coupled with the relay antenna. The automatic tuning assist circuit has first and second terminals coupled with the relay antenna. Multiple switches are arranged together with N (N represents an integer) auxiliary capacitors between the first terminal and the second terminal. A controller is configured to switch on and off each of the multiple switches in synchronization with an electric power signal transmitted from a wireless power supply apparatus. | 06-05-2014 |
20140145742 | PROBE APPARATUS AND TEST APPARATUS - A probe apparatus providing an electrical connection between a device under test and a test apparatus body, comprising a device-side terminal unit including a flexible sheet and device-side connection terminals passing through the sheet and connected to the device under test; an intermediate substrate provided on the test apparatus body side of the device-side terminal unit and including device-side intermediate electrodes electrically connected to the device-side connection terminals and tester-side intermediate electrodes electrically connected to the test apparatus body; a tester-side substrate that is provided on the test apparatus body side of the intermediate substrate and includes, on the intermediate substrate side thereof, tester-side electrodes electrically connected to the test apparatus body; and a contact section provided between the intermediate substrate and the tester-side substrate and including first pins connected to the tester-side intermediate electrodes and second pins connected to the tester-side electrodes. | 05-29-2014 |
20140132078 | WIRELESS POWER TRANSMITTER - A wireless power supply apparatus includes a resonance circuit and a multi-tone power supply, and is configured to transmit an electric power signal comprising at least one from among an electric field, a magnetic field, and an electromagnetic field. The resonance circuit includes a transmission coil and a resonance capacitor connected in series. The multi-tone power supply is configured to generate a multi-tone signal by superimposing multiple sine wave signals having respective frequencies, and to output the multi-tone signal thus generated to the resonance circuit. | 05-15-2014 |
20140131589 | ELECTRON BEAM EXPOSURE APPARATUS AND METHOD - An electron beam EB | 05-15-2014 |
20140120475 | ELECTRON BEAM EXPOSURE METHOD - An electron beam exposure method includes the steps of: preparing an exposure mask having a plurality of opening patterns formed by dividing a drawing object pattern into exposable regions; and drawing the drawing object pattern by performing exposure with an electron beam passing through the opening patterns of the exposure mask. Each end portion serving as a joint in each opening pattern of the exposure mask is provided with a joining portion tapered in a width of the opening pattern. The exposure is performed in such a way that portions drawn through adjacent joining portions overlap each other. | 05-01-2014 |
20140111235 | ELECTRONIC COMPONENT HANDLING APPARATUS, ELECTRONIC COMPONENT TESTING APPARATUS, AND ELECTRONIC COMPONENT TESTING METHOD - There is provided an electronic component handling apparatus which can be reduced in size or can improve the throughput when the number of contact arms is increased. A handler comprises: a plurality of contact arms which are arrayed along a first direction, each of the plurality of contact arms including a holding part which holds a DUT and including an adjustment unit which moves the holding part relative to a base part of each contact arm; an imaging unit capable of imaging the DUT and the holding part; an operation unit which operates the adjustment unit; and a moving unit which moves the imaging unit and the operation unit along an X direction. The adjustment unit adjusts the relative position of the holding part according to an operation of the operation unit. | 04-24-2014 |
20140091830 | TEST APPARATUS - A judgment unit judges the pass/fail of DUTs. A power supply circuit has changeable characteristics, and supplies a power supply signal to the DUTs. A condition setting unit performs a pilot test before a main test for the DUTs, and acquires a test condition to be used in the main test. The condition setting unit executes: (a) measuring a first device characteristic value for each of multiple pilot samples sampled from among the DUTs while emulating a power supply characteristic close to what is used in a user environment in which the DUT is actually used; (b) measuring a predetermined second device characteristic value for each of the multiple pilot sample devices while emulating a power supply characteristic close to what is used in a tester environment in which the main test is performed; and (c) determining the test condition based on the first and second device characteristic values. | 04-03-2014 |
20140091637 | WIRELESS POWER RECEIVER - An automatic tuning assist circuit is coupled with a transmission antenna. Multiple switches SW and a first auxiliary capacitor CA are arranged between a first terminal and a second terminal of the automatic tuning assist circuit. A first control unit is configured to switch on and off the multiple switches SW in synchronization with a driving voltage V | 04-03-2014 |
20140070831 | SYSTEM AND METHOD OF PROTECTING PROBES BY USING AN INTELLIGENT CURRENT SENSING SWITCH - An apparatus and method for protecting probes used in automated testing is disclosed. The apparatus comprises a probe operable to provide power to a device under test (DUT) from a device power source (DPS), wherein the probe is coupled to a contact point on the DUT and a probe protector circuit connected to the probe in series between the DPS and the DUT. The probe protector circuit further comprises a current sense module operable to monitor a flow of current from the DPS to the DUT to determine if the current flow is below a predetermined threshold current level and a switch for controlling the connection from the DPS to the DUT. The switch is coupled to the current sense module and is operable to be used in conjunction with the current sense module to limit the current flow if it exceeds the predetermined threshold current level. | 03-13-2014 |
20140064643 | X-Y CONSTRAINING UNIT, AND STAGE APPARATUS AND VACUUM STAGE APPARATUS INCLUDING THE SAME - Provided are X-Y constraining units having excellent yawing attitude precision as well as a stage apparatus and a vacuum stage apparatus, each including the X-Y constraining units. The X-Y constraining units | 03-06-2014 |
20140063111 | PATTERN PRINTING APPARATUS, PATTERN PRINTING METHOD, AND TEST APPARATUS - A pattern printing apparatus comprising an ink output section including a nozzle that drops ink and a heating section that heats a preheating target region; a driving section that moves the substrate relative to the ink output section; and a control section that controls the driving section. The control section causes the substrate to move relative to the ink output section such that the preheating target region is positioned in a progression path of the drawing target region and causes a pattern formed by the ink to be drawn, and when switching an extension direction of the pattern being drawn, the control section causes the preheating target region to move to an end portion of the pattern drawn before the switching and causing the preheating target region to be heated. | 03-06-2014 |
20140062455 | MEASUREMENT APPARATUS AND MEASUREMENT METHOD - To accurately measure a frequency characteristic of a waveform generating apparatus, provided is a measurement apparatus that measures a frequency characteristic of a waveform generating apparatus generating a signal having a waveform corresponding to waveform data, comprising a control section that causes a plurality of sine wave signals having different frequencies to be sequentially output from the waveform generating apparatus; a measuring section that measures each of the sine wave signals output from the waveform generating apparatus; and a calculating section that calculates a frequency characteristic of the waveform generating apparatus based on the measurement results of the measuring section. The control section causes trigger signals to be output from the waveform generating apparatus and causes the sine wave signals to be output in synchronization with the trigger signals, and the measuring section measures a phase of each sine wave signal with the corresponding trigger signal as a reference. | 03-06-2014 |
20140061465 | ELECTRON BEAM DETECTOR, ELECTRON BEAM PROCESSING APPARATUS, AND METHOD OF MANUFACTURING ELECTRON BEAM DETECTOR - There is provided an electron beam detector including an electron beam scatterer which is disposed at a predetermined distance below a shield including a plurality of openings formed therein, and a beam detection element disposed at a predetermined distance below the scatterer and configured to convert an electron beam into an electric signal. In the electron beam detector, the scatterer is disposed at an equal distance from any of the openings in the shield, and the beam detection element is disposed at an equal distance from any of the openings in the shield. Thus, the electron beam detector can suppress a variation in detection sensitivity depending on the position of the opening. | 03-06-2014 |
20140048720 | SAMPLE HOLDER OF ELECTRON BEAM EXPOSURE APPARATUS AND ELECTRON BEAM EXPOSURE METHOD USING THE SAME - A sample holder to be disposed between an electrostatic chuck and a sample smaller than the upper surface of the electrostatic chuck is provided, the sample holder including: a base plate formed in the same size as the upper surface of the electrostatic chuck; a sample placement portion located on the upper surface of the base plate, and designed to place the sample thereon; and a circumferential portion being a portion of the upper surface of the base plate other than the sample placement portion, and having a conductive material exposed to the outside. | 02-20-2014 |
20140002105 | SWITCH APPARATUS AND TEST APPARATUS | 01-02-2014 |
20130335101 | TEST APPARATUS - A test apparatus for testing a device under test, includes a low-speed comparator, a high-speed comparator that is operable faster than the low-speed comparator, and a switching section that switches, according to a signal output from the device under test, which one of the low-speed comparator and the high-speed comparator is used to measure a signal under measurement output from the device under test. The test apparatus may further include a termination resistance that is arranged in parallel with the high-speed comparator. | 12-19-2013 |
20130305000 | SIGNAL PROCESSING CIRCUIT - A memory controller is connected to memory, and has no ECC (Error Check and Correct) function. An embedded CPU is connected to the memory via the memory controller such that it can access the memory. A memory check circuit is connected to the memory via the memory controller such that it can access the memory, and configured to access the memory in the non-operating period of the embedded CPU, so as to check the data stored in the memory. | 11-14-2013 |
20130285505 | ACTUATOR APPARATUS, TEST APPARATUS, AND TEST METHOD - Provided is an actuator apparatus including: an actuator that is provided with a driving voltage at one end and a reference potential at the other end to enable driving; a first setting section that is connected to the one end of the actuator and sets an operating speed of the actuator; a second setting section that is provided between the one end of the actuator and the reference potential, and sets the driving voltage of the actuator. | 10-31-2013 |
20130284950 | ELECTROMAGNETIC WAVE EMISSION DEVICE - According to the present invention, an electromagnetic wave emission device includes a nonlinear crystal having an optical waveguide; and a prism including an electromagnetic wave input surface and an electromagnetic wave transmission surface. The electromagnetic wave transmission surface includes a rotation surface which is a trajectory of a tilted line segment rotated about a central axis of the electromagnetic wave input surface, the tilted line segment being tilted with respect to the central axis. The tilted line segment and the central axis are on the same plane. The central axis is in parallel to an extending direction of the optical waveguide. The central axis passes through a projection of the optical waveguide into the electromagnetic wave input surface. | 10-31-2013 |
20130284930 | MEASUREMENT DEVICE, METHOD, AND RECORDING MEDIUM - According to the present invention, a measurement device includes an electromagnetic wave detector, a phase measurement unit and a deriving unit. The electromagnetic wave detector detects an electromagnetic wave having a frequency equal to or more than 0.02 THz and equal to or less than 12 THz having traveled inside an object to be measured, which is an aggregation of particles. The phase measurement unit measures a change in phase of the electromagnetic wave generated by the travel inside the object to be measured based on a detection result by the electromagnetic wave detector. The deriving unit derives hardness or porosity of the object to be measured based on a measurement result by the phase measurement unit. | 10-31-2013 |
20130270449 | DA CONVERSION DEVICE AND ELECTRON BEAM EXPOSURE SYSTEM USING THE SAME - A DA conversion device includes a current output type DA converter, a high-speed operational amplifier operating at a low voltage and configured to generate a voltage corresponding to an output current from the DA converter, and a buffer amplifier connected to an output terminal of the high-speed operational amplifier and operating at a high voltage. The device also includes positive and negative floating power supplies separated from a power supply system and provided as power supplies for driving the DA converter and the high-speed operational amplifier. A midpoint between potentials at the floating power supplies is connected to an output terminal of the buffer amplifier to cause the DA converter and the high-speed operational amplifier to operate mainly based on an output voltage from the buffer amplifier. | 10-17-2013 |
20130264480 | PATTERN MEASUREMENT METHOD AND PATTERN MEASUREMENT APPARATUS - A pattern measurement method and a pattern measurement apparatus which use a scanning electron microscope are provided. SEM images of a measurement target pattern are respectively acquired at least two predetermined acceleration voltages. White band widths of the measurement target pattern are detected from the acquired SEM images. Then, an amount of change in the white band width between the predetermined acceleration voltages is calculated. A side wall angle of the measurement target pattern is calculated on the basis of a relation between an amount of change in a white band width and a side wall angle experimentally obtained in advance by using a sample with a known side wall angle. | 10-10-2013 |
20130254595 | COMMUNICATION SYSTEM AND TEST APPARATUS - An instruction is assuredly transmitted. A test apparatus that tests a device under test, includes a test unit that tests a device under test by exchanging a signal with the device under test, a control apparatus that controls the test unit; and a relay apparatus that relays communication between the test unit and the control apparatus, where the control apparatus transmits an instruction to be given to the test unit a plurality of times to the test unit, and the test unit receives the instruction transmitted the plurality of times from the control apparatus, and executes the instruction once. | 09-26-2013 |
20130249625 | SIGNAL GENERATION APPARATUS AND SIGNAL GENERATION METHOD - In order to output an accurate waveform in which quantization noise has been cancelled out, provided is a signal generating apparatus that outputs an output signal corresponding to a waveform data sequence expressing a waveform, the signal generating apparatus comprising a DA converting section that outputs an analog signal by sequentially performing digital/analog conversion on each piece of data included in the waveform data sequence, at a timing of a sampling clock; and a jitter injecting section that injects jitter decreasing a quantization noise component of the output signal, into the sampling clock supplied to the DA converting section. | 09-26-2013 |
20130249307 | WIRELESS COMMUNICATION APPARATUS AND WIRELESS COMMUNICATION SYSTEM - To realize a wireless communication apparatus with high transceiver coil mounting density, provided is a wireless communication apparatus comprising a plurality of differential coil pairs that respectively transmit and receive differential signals to and from a plurality of external differential coil pairs, through magnetic coupling, wherein one coil in a first differential coil pair among the differential coil pairs is provided at a distance from each of two coils of a second differential coil pair among the differential coil pairs that is less than or equal to a distance between the two coils of the second differential coil pair, and the other coil of the first differential coil pair is provided at a distance from each of the two coils of the second differential coil pair that is greater than the distance between the two coils of the second differential coil pair. | 09-26-2013 |
20130244568 | COMMUNICATION SYSTEM AND TEST APPARATUS - A test apparatus ensures to establish communication. A test apparatus including a first communication apparatus and a second communication apparatus, where the transmitting section of the first communication apparatus transmits the first linkup code to the receiving section of the second communication apparatus, the transmitting section of the second communication apparatus transmits, instead of the first linkup code, the second linkup code in response to communication having being established between the receiving section of the second communication apparatus and the transmitting section of the first communication apparatus, and the receiving section of the first communication apparatus starts communicating with the transmitting section of the relay apparatus, in response to communication having being established with the transmitting section of the relay apparatus and reception of the second linkup code from the transmitting section of the relay apparatus. | 09-19-2013 |
20130240736 | ELECTROMAGNETIC WAVE MEASURING APPARATUS, MEASURING METHOD, PROGRAM, AND RECORDING MEDIUM - An electromagnetic wave measurement device includes an electromagnetic wave outputter that outputs an electromagnetic wave having a frequency equal to or more than 0.01 THz and equal to or less than 100 THz toward a device under test. An electromagnetic wave detector detects the electromagnetic wave which has transmitted through the device under test. A relative position changer changes a relative position of an intersection of an optical path of the electromagnetic wave transmitting through the device under test and the device under test, with respect to the device under test, so that the intersection is at a predetermined relative position due to the refraction of the electromagnetic wave by the device under test. A characteristic value deriver derives a characteristic value of the electromagnetic wave based on a detection result of the electromagnetic wave detector, the characteristic value being associated with the predetermined relative position. | 09-19-2013 |
20130238262 | MEASUREMENT APPARATUS, MEASUREMENT METHOD, AND PROGRAM - A measurement apparatus comprising an IQ error measuring section that measures a frequency characteristic of an IQ error of a device under measurement; and an error amount calculating section that calculates EVM based on a constellation error, at each of a plurality of frequencies, between an ideal signal to be output in response to input of a predetermined signal into a model of the device under measurement that does not include an IQ error and a prediction signal that is to be output in response to the input of the predetermined signal into a model of the device under measurement that includes the IQ error measured by the IQ error measuring section, wherein the error amount calculating section corrects a signal component at each of the frequencies in the prediction signal according to a channel characteristic, and calculates the constellation error. | 09-12-2013 |
20130234748 | TRANSFERRING ELECTRONIC PROBE ASSEMBLIES TO SPACE TRANSFORMERS - Transferring electronic probe assemblies to space transformers. In accordance with a first method embodiment, a plurality of probes is formed in a sacrificial material on a sacrificial substrate via microelectromechanical systems (MEMS) processes. The tips of the plurality of probes are formed adjacent to the sacrificial substrate and the remaining structure of the plurality of probes extends outward from the sacrificial substrate. The sacrificial material comprising the plurality of probes is attached to a space transformer. The space transformer includes a plurality of contacts on one surface for contacting the plurality of probes at a probe pitch and a corresponding second plurality of contacts on another surface at a second pitch, larger than the probe pitch, wherein each of the second plurality of contacts is electrically coupled to a corresponding one of the plurality of probes. The sacrificial substrate is removed, and the sacrificial material is removed, leaving the plurality of probes intact. | 09-12-2013 |
20130234747 | FINE PITCH PROBE ARRAY FROM BULK MATERIAL - Fine pitch probe array from bulk material. In accordance with a first method embodiment, an article of manufacture includes an array of probes. Each probe includes a probe tip, suitable for contacting an integrated circuit test point. Each probe tip is mounted on a probe finger structure. All of the probe finger structures of the array have the same material grain structure. The probe fingers may have a non-linear profile and/or be configured to act as a spring. | 09-12-2013 |
20130234746 | SHIELDED PROBE ARRAY - Shielded probe array. In accordance with a first embodiment, an article of manufacture includes a plurality of rows of electronic probes. Each row of probes is substantially in a plane. Each probe includes a metal signal layer and a ground layer, separated by an insulator. The article of manufacture also includes a space transformer for mechanically supporting the plurality of rows of electronic probes. The space transformer also provides an electrical path from each of the probe metal signal layers and the probe ground layers to a higher level electronic assembly. Each of the plurality of rows of electronic probes may include a handle including a substrate for handling the row of electronic probes. | 09-12-2013 |
20130231888 | TEST APPARATUS AND TEST MODULE - Provided is a test apparatus that tests a device under test, comprising a test module that communicates with the device under test to test the device under test; and a control apparatus that executes a plurality of test programs, causes the test module to perform tests corresponding respectively to the test programs, receives test results from the test module, and performs predetermined result processes on the test results. The control apparatus stores an execution order of the test programs, and executes at least a portion of the result processes in an order indicated by the stored execution order. | 09-05-2013 |
20130231887 | TEST APPARATUS AND TEST MODULE - A test apparatus that tests a device under test, comprising a control apparatus sequentially executing a plurality of test programs and controlling testing of the device under test; and a test module controlled by the control apparatus to test the device under test by communicating with the device under test and to transmit a test result of each test program to the control apparatus. The test module includes memories that store the test results of the test programs, and starts a subsequent test such that at least a portion of a result processing time period of a current test, from when a test result stored in a first memory begins being transmitted to the control apparatus to when processing of the test result by the control apparatus ends, overlaps with at least a portion of a test execution period in which the subsequent test is executed using a second memory. | 09-05-2013 |
20130231886 | TEST APPARATUS AND TEST MODULE - In order to efficiently test a plurality of types of devices under test, provided is a test apparatus that tests a device under test, comprising one or more test modules that each include a plurality of testing sections testing the device under test by exchanging signals with the device under test; and a plurality of control apparatuses that control operation of the testing sections. In each of the one or more test modules, the plurality of testing sections are each allocated to one of the plurality of control apparatuses, and each of the control apparatuses is capable of executing a test program managed by a different user, and controls operation of the testing sections allocated thereto. | 09-05-2013 |
20130231885 | TEST APPARATUS AND TEST MODULE - In order to shorten testing time, provided is a test apparatus that tests a device under test, comprising one or more test modules that each include a plurality of testing sections testing the device under test by exchanging signals with the device under test; and a control apparatus that controls operation of the testing sections. The control apparatus executes in parallel a plurality of test programs for testing the device under test, to control in parallel the operation of the testing sections assigned respectively to the test programs, and the testing sections test the device under test by exchanging signals in parallel with the device under test. | 09-05-2013 |
20130229197 | TEST APPARATUS - A main power supply is arranged such that its output terminal Po is connected to a power supply terminal of a DUT via a power supply line, and is configured to feedback control an output voltage V | 09-05-2013 |
20130202245 | WAVELENGTH CONVERSION APPARATUS, LIGHT SOURCE APPARATUS, AND WAVELENGTH CONVERSION METHOD - In order to create a stable non-linear optical effect with high efficiency for a plurality of input lights having different wavelengths, according to a first aspect of the present invention, provided is a wavelength conversion apparatus comprising an input section into which input light is input; a wavelength converting section that includes a polarity inverting structure whose polarity inverts periodically and that, in response to the input of light having a wavelength corresponding to the period with which the polarity inverts, converts the wavelength of the light; and a direction changing section that changes a progression direction in which the input light passes through the polarity inverting structure, according to the wavelength of the input light, without changing relative positions of the input section and the polarity inverting structure. Also provided are a light source apparatus and a wavelength converting method. | 08-08-2013 |
20130199310 | CONTACT PRESSURE DETECTION APPARATUS AND CONTACT POINT PRESSURE MEASUREMENT APPARATUS - To measure contact pressure of each of a plurality of small protrusions arranged at a narrow pitch and contacting a flat surface, provided is a contact pressure detection apparatus comprising a sensor section that is contacted by a target and has pressure applied thereto by the target; a light source section that radiates light with a wavelength causing Raman scattering in the sensor section to which the pressure is applied; and a detecting section that receives light from the sensor section and detects the pressure between the sensor section and the target. Also provided is a contact point pressure measurement apparatus that measures contact pressure of an electrode of a device under test, comprising: a fixing section that has the device under test mounted thereon and fixes the electrode of the device under test in a manner to press against the sensor section; and the contact pressure detection apparatus. | 08-08-2013 |
20130189866 | CONNECTOR AND SEMICONDUCTOR TEST DEVICE - A connector includes a signal terminal, an insulating member, a ground terminal and an enclosure. The signal terminal has a main body extending in one direction, and a contact arm provided on each side of the main body for contacting another conductor. The insulating member encloses the main body. The ground terminal has a cylindrical main body enclosing the insulating member, and a contact arm provided on each side of the cylindrical main body for contacting another conductor. The cylindrical main body includes first and second semi-cylindrical parts, each having semi cylindrical shapes. The semi-cylindrical parts make a cylindrical shape as a whole by both end parts of the circumferential direction being assembled so as to mutually overlap. An insertion hole is formed in the enclosure where an assembly of the signal element, the insulating member and the ground terminal are inserted. | 07-25-2013 |
20130182530 | CONVERTER AND MEASURING APPARATUS - Provided is a converter that converts sound waves into electrical signals, comprising a piezoelectric section including a plurality of piezoelectric elements that each convert a sound wave detected by a detection surface into one of the electrical signals; and a multilayer substrate to which the piezoelectric section is fixed. The multilayer substrate includes a plurality of signal wires that correspond respectively to the piezoelectric elements and each transmit the electrical signal output by the corresponding piezoelectric element; and a shield portion that electromagnetically shields at least a portion of the signal wires. The piezoelectric section is fixed to the multilayer substrate such that a surface of the multilayer substrate on which the piezoelectric elements are fixed is inclined with respect to the detection surfaces of the piezoelectric elements. | 07-18-2013 |
20130181735 | HANDLER AND TEST APPARATUS - A handler for conveying DUTs to a socket for a test that can reduce a test time includes: a test section including the socket; a heat applying section into which a tray having plural DUTs placed on its surface is conveyed and that controls the temperature of the DUTs to a predetermined test temperature and conveys the tray into the test section; and a device image capturing section that includes imaging elements arranged along a first direction the number of which is equal to DUTs arranged along the first direction and that in the heat applying section, captures images of the DUTs by moving the imaging elements relative to the surface of the tray in a second direction non-parallel with the first direction; and a position adjusting section that adjusts the positions of the DUTs relative to the socket based on their images captured by the device image capturing section. | 07-18-2013 |
20130181734 | HANDLER AND TEST APPARATUS - A handler for conveying a plurality of devices under test to a socket for a test that can reduce a test time includes: a test section provided with the socket; a heat applying section into which a tray having a plurality of devices under test placed on its surface is conveyed and that controls the temperature of the devices under test to a predetermined test temperature and conveys the tray into the test section; a device image capturing section that in the heat applying section, captures images of the respective devices under test by moving with respect to the surface of the tray in two non-parallel directions of a first direction and a second direction; and a position adjusting section that adjusts the positions of the devices under test with respect to the socket based on the images of the devices under test captured by the device image capturing section. | 07-18-2013 |
20130181733 | HANDLER APPARATUS AND TEST METHOD - Provided is a handler apparatus which can connect devices under test to sockets of a test apparatus quickly and with low power consumption. The handler apparatus for conveying and connecting a plurality of devices under test to a plurality of sockets provided on a test head of a test apparatus, includes a position adjusting section that moves each of the plurality of devices under test on the test tray and adjusts the position thereof to a corresponding one of the plurality of sockets; and a device mounting section that mounts the plurality of devices under test whose positions have been adjusted by the position adjusting section, to the plurality of sockets | 07-18-2013 |
20130181146 | ELECTROMAGNETIC WAVE EMISSION DEVICE - An electromagnetic wave emission device includes a nonlinear crystal which receives exciting light Lp having two wavelength components λ | 07-18-2013 |
20130179121 | CALCULATING APPARATUS, MEASURING APPARATUS, ELECTRONIC DEVICE, PROGRAM, RECORDING MEDIUM AND CALCULATING METHOD - A calculating apparatus for calculating a probability density function representing a probability density of a pre-set random variable, from a cumulative probability distribution function representing a cumulative probability distribution of the random variable, includes: a probability density function calculating section that calculates the probability density of each value of the random variable of the probability density function, based only on a value of the cumulative probability distribution function corresponding to the value of the random variable, from among values of the cumulative probability distribution function corresponding to values of the random variable. | 07-11-2013 |
20130170583 | TRANSMITTING SYSTEM, RECEIVING SYSTEM, TRANSMITTING METHOD, AND RECEIVING METHOD - Provided are a transmitting system including a pulse amplitude modulator section that pulse amplitude modulates an input signal into a set of first and second pulse amplitude modulated signals, a first frequency signal output section that outputs a first frequency signal, a first amplitude shift keying modulator section that amplitude shift keying modulates, using the first frequency signal, the first pulse amplitude modulated signal into an amplitude shift keying modulated signal, an adder section that adds together the amplitude shift keying modulated signal and the second pulse amplitude modulated signal to generate a transmission signal, and a transmitter section that transmits the transmission signal, a transmitting method, a receiving system for receiving the signal transmitted from the transmitting system and a receiving method. | 07-04-2013 |
20130169304 | PITCH CHANGING APPARATUS, ELECTRONIC DEVICE HANDLING APPARATUS, AND ELECTRONIC DEVICE TESTING APPARATUS - There is provided a pitch changing apparatus which can change a pitch of DUTs when the DUTs are transferred between trays by a shuttle revolving system. | 07-04-2013 |
20130169303 | ELECTRONIC DEVICE TESTING APPARATUS - There is provided an electronic device testing apparatus which can effectively use a space in an electronic device handling apparatus since a preciser is not necessary. | 07-04-2013 |
20130168203 | ELECTRONIC DEVICE TRANSFER APPARATUS, ELECTRONIC DEVICE HANDLING APPARATUS, AND ELECTRONIC DEVICE TESTING APPARATUS - There is provided an electronic device transfer apparatus which has an excellent capacity of transferring DUTs between trays. | 07-04-2013 |
20130158905 | TEST APPARATUS AND TEST METHOD - A synchronization pattern generating unit generates a synchronization pattern required for a clock recovery unit which has been built into a DUT to maintain a link with an external circuit. A gate signal generating unit generates a gate signal which is asserted in a period in which a vector pattern is to be supplied to the DUT. In a first mode, a pattern selecting unit is configured such that it outputs the vector pattern during a period in which the gate signal is asserted and outputs a fixed output level during a period in which the gate signal is negated. In a second mode, the pattern selecting unit is configured such that it outputs the vector pattern during a period in which the gate signal is asserted and outputs the synchronization pattern during a period in which the gate signal is negated. | 06-20-2013 |
20130147499 | TEST APPARATUS AND TEST METHOD - A pattern generator generates a pattern signal which represents a test signal to be supplied to a DUT. A driver generates a test signal having a level that corresponds to the pattern signal, and outputs the test signal thus generated to the DUT. A voltage modulator changes, in a predetermined voltage range, the voltage level of the test signal output from the driver DR. | 06-13-2013 |
20130141266 | ANALOG TO DIGITAL CONVERTER AND DIGITAL TO ANALOG CONVERTER - To decrease the burden of digital processing, provided is an AD conversion apparatus comprising a pattern generating section that, for each target bit specified one bit at a time moving downward in the output data, generates a pattern signal having a pulse width or number of pulses corresponding to a weighting of the target bit; an integrating section that integrates the pattern signals according to a judgment value for judging a value of the target bit each time a pattern signal is generated, and outputs a reference signal obtained by accumulating the integrated value of each pattern signal; a comparing section that, each time generation of a pattern signal is finished, compares the input signal to the reference signal; and an output section that outputs the output data to have values corresponding to the comparison results obtained after each generation of a pattern signal corresponding to a bit is finished. | 06-06-2013 |
20130139004 | TEST MODULE GENERATION APPARATUS, TEST PROCEDURE GENERATION APPARATUS, GENERATION METHOD, PROGRAM, AND TEST APPARATUS - Provided is a test module generation apparatus that generates a test module executed on a test apparatus for testing a device under test. The apparatus includes a condition file generating section in which a test condition is input and that generates a condition file specifying the input test condition, a test method storing section that stores a test method, a test method selecting section that receives, from a user, a selection instruction of the test method adapted to the test module to be generated, a condition file selecting section that receives, from a user, a selection instruction of the condition file corresponding to a parameter which the selected test method requires, and a test module generating section that generates the test module in which a test according to the selected test method is executed with a parameter specified by the condition file. | 05-30-2013 |
20130126736 | SPREAD ANALYSIS DEVICE FOR LUBRICANT, METHOD, AND RECORDING MEDIUM - An electromagnetic wave output device outputs an electromagnetic wave. An optical element has a total reflection surface for totally reflecting the electromagnetic wave, and causes the device under test to receive an evanescent wave generated from the total reflection surface. An electromagnetic wave detector detects the electromagnetic wave, and a spectrum deriver derives a reflectance of the electromagnetic wave on the total reflection surface or a value based on the reflectance based on a detection result by the electromagnetic wave detector while the reflectance or the value based on the reflectance is associated with the frequency of the electromagnetic wave and a manufacturing condition of the particle or the device under test. A characteristic extractor extracts a characteristic based on the manufacturing condition from a derived result by the spectrum deriver. | 05-23-2013 |
20130115723 | Method of manufacturing semiconductor device and semiconductor manufacturing system - In a method of manufacturing a semiconductor device using an electron beam lithography apparatus configured to emit an electron beam to perform lithography of a pattern, processing including pattern formation with the electron beam lithography apparatus is performed on a wafer, and an electric characteristic of the thus manufactured semiconductor devices is measured by a semiconductor testing apparatus. Then, electron beam lithography data to be used by the electron beam lithography apparatus is adjusted based on a result of measurement of the electric characteristic so as to reduce a variation in the electric characteristic of the semiconductor device within a surface of the wafer. | 05-09-2013 |
20130106450 | DRIVE CIRCUIT AND TEST APPARATUS | 05-02-2013 |
20130105691 | PATTERN MEASUREMENT APPARATUS AND PATTERN MEASUREMENT METHOD | 05-02-2013 |
20130093453 | CONNECTING DEVICE, SEMICONDUCTOR WAFER TEST APPARATUS COMPRISING SAME, AND CONNECTING METHOD - A connecting device electrically connects a performance board which has PB terminals and a test head, and includes a sub board which is electrically connected to the test head and has sub terminals which face the PB terminals, a sealing mechanism which forms a sealed space between the sub board and the performance board, and a pressure reducing device which reduces the pressure of the sealed space. The pressure reducing device reduces the pressure of the sealed space so that the performance board and the sub board approach each other and the PB terminals and the sub terminals contact. | 04-18-2013 |
20130086423 | TEST APPARATUS AND TEST METHOD - Provided is a test apparatus including: an address generator that generates an address of a memory under test; a selector that selects whether to perform bit inversion on the address generated by the address generator before supplying the address to the memory under test; an inversion processing section that outputs the address generated by the address generator after performing bit inversion on the address if the selector has selected in the affirmative, and outputs the address generated by the address generator without performing any bit inversion on the address if the selector has selected in the negative; and a supply section that supplies, to the memory under test, the address having undergone inversion control outputted from the inversion processing section and an inversion cycle signal that indicates whether the address outputted from the inversion processing section is bit inverted or not. | 04-04-2013 |
20130082727 | WAFER TRAY, SEMICONDUCTOR WAFER TEST APPARATUS, AND TEST METHOD OF SEMICONDUCTOR WAFER - A wafer tray which holds a semiconductor wafer includes a wafer set plate on which the semiconductor wafer is set, a tray body which supports the wafer set plate to be able to finely move, and a vibration actuator which imparts vibration to the wafer set plate. | 04-04-2013 |
20130075612 | CARRIER AND ADHESION AMOUNT MEASURING APPARATUS, AND MEASURING METHOD, PROGRAM, AND RECORDING MEDIUM OF THE SAME - A carrier includes attachment holes to which a catalyst attaches, and non-attachment holes to which the catalyst does not attach. An attachment quantity measurement device includes an electromagnetic wave output device that outputs a terahertz wave toward the carrier, an electromagnetic wave detector that detects the terahertz wave which has transmitted through the carrier, a reference value obtainer that obtains, based on a result detected by the electromagnetic wave detector, any one of an absorption rate, a group delay, and a dispersion of the terahertz wave in the non-attachment holes, and an attachment quantity obtainer that obtains, based on the result detected by the electromagnetic wave detector and the result obtained by the reference value obtainer, a weight or a density of the catalyst present in the attachment holes. | 03-28-2013 |
20130075597 | ELECTROMAGNETIC WAVE DETECTION DEVICE - According to the present invention, an electromagnetic wave detection device includes an optical waveguide, an electromagnetic wave input unit, and a phase difference measurement unit. According to the thus constructed electromagnetic wave detection device, an optical waveguide is a nonlinear crystal, and includes a branching portion for receiving a probe light pulse, and causing the probe light pulse to branch into two beams of branching light, and two branching light transmission portions for receiving the branching light from the branching portion, and transmitting the branching light. An electromagnetic wave input unit inputs an electromagnetic wave having a frequency equal to or more than 0.01 [THz] and equal to or less than 100 [THz] tilted by an angle generating Cherenkov phase matching with respect to a travel direction of the branching light into one of the two branching light transmission portions. | 03-28-2013 |
20130068971 | ELECTROMAGNETIC WAVE EMISSION DEVICE - An electromagnetic wave emission device includes a nonlinear crystal, a prism, and a cylindrical lens. The nonlinear crystal has an optical waveguide, receives exciting light having at least two wavelength components, and outputs an electromagnetic wave having a frequency equal to or more than 0.01 [THz] and equal to or less than 100 [THz] by means of the Cherenkov phase matching. The prism includes an electromagnetic wave input surface receiving the electromagnetic wave from the optical waveguide and an electromagnetic wave transmission surface through which the electromagnetic wave which has entered from the electromagnetic wave input surface passes. The cylindrical lens has two bottom surfaces opposed to each other, a flat surface intersecting with the two bottom surfaces, and a curved surface intersecting with the two bottom surfaces and the flat surface, wherein the flat surface is in contact with the electromagnetic wave transmission surface. | 03-21-2013 |
20130038345 | PROBE STRUCTURE, PROBE APPARATUS, PROBE STRUCTURE MANUFACTURING METHOD, AND TEST APPARATUS - Probes are arranged precisely and at a narrow pitch. Provided is a probe structure receiving and transmitting an electric signal from/to a device. The probe structure includes a contact point that transmits an electric signal, a probe on which the contact point is formed, a probe pad section that is electrically coupled to the contact point, and an insulating section that is provided on the probe and that insulates a bonding wire connected to the probe pad section from the probe. A probe apparatus, a manufacturing method of a probe structure, and a test apparatus are also provided. | 02-14-2013 |
20130038340 | MEASURING APPARATUS AND MEASURING METHOD - A measurement apparatus comprising a serial resistor in series with an element under measurement; a switching section that sequentially selects ends of a serial circuit including the element under measurement and the serial resistor, and ends of the serial resistor; an applying section that applies an application voltage or application current corresponding to a preset setting value, to each of the sequentially selected ends; a measuring section that, for each of the sequentially selected ends, measures current when the applying section applies the application voltage corresponding to the setting value and measures voltage when the applying section applies the application current corresponding to the setting value; and a resistance calculating section that calculates the resistance value of the element under measurement, based on either the setting values set sequentially in the applying section or measured values measured sequentially by the measuring section for each of the sequentially selected ends. | 02-14-2013 |
20130038335 | SWITCHING APPARATUS AND TEST APPARATUS - Provided is a switching apparatus comprising a contact point section that includes a first contact point; an actuator that includes a second contact point and moves the second contact point to contact or move away from the first contact point; and a control section that controls a first drive voltage. The actuator includes a first piezoelectric film that expands and contracts according to the first drive voltage and a support layer disposed on the first piezoelectric film. The control section causes the first piezoelectric film to contract by causing a change from a voltage that applies an electric field that is less than a first coercive electric field to a voltage that applies an electric field that exceeds the first coercive electric field, and causes the first piezoelectric film to expand by outputting a voltage that applies an electric field that is less than a second coercive electric field. | 02-14-2013 |
20130037395 | SWITCHING APPARATUS AND TEST APPARATUS - A switching apparatus comprising a contact point section including a first contact point; an actuator including a first piezoelectric film that expands and contracts according to a first drive voltage and a second piezoelectric film provided in parallel with the first piezoelectric film and expands and contracts according to a second drive voltage, and a control section that controls the first drive voltage and the second drive voltage is provided. The actuator moves a second contact point to contact or move away from the first contact point according to the contraction and expansion of the first piezoelectric film and the second piezoelectric film. When switching from a contact state to a separated state, the control section stops supplying the first drive voltage and applies the second drive voltage causing the second piezoelectric film to contract to the second piezoelectric film, such that the actuator is biased to return. | 02-14-2013 |
20130027057 | SWITCHING APPARATUS, SWITCHING APPARATUS MANUFACTURING METHOD, TRANSMISSION LINE SWITCHING APPARATUS, AND TEST APPARATUS - A package of a switching apparatus that houses an actuator having a movable contact point and in which a fixed contact point, which is electrically connected to or disconnected form the movable contact point, is accurately formed. Provided is a switching apparatus comprising a first substrate provided with a via that electrically connects a top surface thereof and a bottom surface thereof, while maintaining an air-tight state between the top surface and the bottom surface; a second substrate provided on the first substrate and in which is formed a through-hole that houses an actuator; and a third substrate provided on the second substrate and supporting the actuator, which has a moveable contact point. | 01-31-2013 |
20130026021 | ACTUATOR MANUFACTURING METHOD, SWITCHING APPARATUS, TRANSMISSION LINE SWITCHING APPARATUS, AND TEST APPARATUS - To manufacture a switching apparatus that includes a piezoelectric actuator with increased lifespan, provided is a method for manufacturing a bimorph actuator, comprising first piezoelectric element layer formation of forming a first piezoelectric element layer on a substrate; support layer formation of forming a support layer made of an insulator on the first piezoelectric element layer; second piezoelectric element layer formation of forming a second piezoelectric element layer on the support layer; and removal of removing a portion of the substrate to form an actuator that includes the first piezoelectric element layer, the support layer, and the second piezoelectric element layer. | 01-31-2013 |
20130018262 | FATTY TISSUE IMAGE DISPLAY DEVICEAANM Matsunaka; ToshiyukiAACI TokyoAACO JPAAGP Matsunaka; Toshiyuki Tokyo JPAANM Horinaka; HiromichiAACI OsakaAACO JPAAGP Horinaka; Hiromichi Osaka JPAANM Morikawa; HiroyasuAACI OsakaAACO JPAAGP Morikawa; Hiroyasu Osaka JPAANM Ogawa; TomohiroAACI OsakaAACO JPAAGP Ogawa; Tomohiro Osaka JP - Provided is a fatty tissue image display device capable of displaying an index indicating the degree of progress of fatty change. The fatty tissue image display device is provided with a light source ( | 01-17-2013 |
20130015873 | CABLE ASSEMBLY, CONNECTOR AND SEMICONDUCTOR TESTERAANM Suzuki; TeruhitoAACI YamatoAACO JPAAGP Suzuki; Teruhito Yamato JPAANM Sakiyama; ShinAACI TokyoAACO JPAAGP Sakiyama; Shin Tokyo JP - In a cable assembly, when auxiliary ground conductor is provided so as to face the lower surface of supporting insulating member, elastically-deformed piece in an elastically deformed status comes in contact with the tip of ground terminal protruding from the lower surface of supporting insulating member. | 01-17-2013 |
20120331346 | TEST APPARATUS AND TEST METHOD - A test apparatus that tests a device under test outputting a data signal and a clock signal indicating a timing at which the data signal is to be sampled, the test apparatus comprising a buffer section that buffers the data signal; a pattern generating section that, for each test period of the test apparatus, generates a control signal and an expected value of the data signal; a reading control section that, for each test period, reads the data signal from the buffer section on a condition that the control signal instructs the reading control section to read data from the buffer section; and a judging section that compares the data signal read by the reading control section to the expected value generated by the pattern generating section. | 12-27-2012 |
20120328228 | OPTICAL DEVICE AND OPTICAL MODULATION APPARATUS - To achieve high-speed optical modulation using a crystal having a complicated refractive index characteristic with respect to applied electric field, provided is an optical device comprising a substrate; a dielectric film that is formed on the substrate and includes a first optical waveguide and a second optical waveguide that run parallel to each other; a transmission line that is formed on the dielectric film and includes a signal line arranged between the first optical waveguide and the second optical waveguide, a first bias electrode, and a second bias electrode, the first bias electrode and the second bias electrode arranged respectively in a first region that is on a side of the first optical waveguide opposite the second optical waveguide and a second region on a side of the second optical waveguide opposite the first optical waveguide; and a drive circuit section that respectively applies a first bias voltage and a second bias voltage differing from each other to the first bias electrode and the second bias electrode, and applies a control voltage that is between the first bias voltage and the second bias voltage to the signal line. | 12-27-2012 |
20120328227 | OPTICAL DEVICE AND OPTICAL MODULATION APPARATUS - Provided is an optical modulator that modulates input light with a high frequency and low half-wave voltage. An optical device comprises a substrate; a dielectric film that is formed on the substrate and includes a first optical waveguide and a second optical waveguide that run parallel to each other; an insulating film formed on the dielectric film; a coplanar line that is formed on the insulating film and includes a signal line arranged between the first optical waveguide and the second optical waveguide, a first ground line arranged in a first region, and a second ground line arranged in a second region; and auxiliary electrodes that are arranged in the first region and the second region, are formed in contact with the dielectric film or within the insulating film, and apply bias voltages to the first optical waveguide and the second optical waveguide. | 12-27-2012 |
20120327990 | SIGNAL MEASUREMENT DEVICE, SIGNAL MEASUREMENT METHOD, AND RECORDING MEDIUM - In a signal measurement device, a plurality of mixers output a signal having a frequency equal to a difference between two input frequencies, and a single local signal source feeds a common local signal input to the plurality of mixers. A difference measurement unit measures a level and a phase difference between outputs of the plurality of mixers if a common correction signal input is fed to the plurality of mixers, and a level/phase measurement unit measures the level and the phase of the output of the plurality of mixers if inputs of signal to be measured common in frequency are fed to the plurality of mixers. A difference correction unit corrects a measurement result of the level/phase measurement unit based on a measurement result of the difference measurement unit if a common input of signal to be measured is fed to the plurality of mixers. | 12-27-2012 |
20120323519 | TEST APPARATUS - A pattern generator PG generates control data which specifies a threshold voltage to be compared with a signal under test input to an I/O terminal, and generates expected value data which represents an expected value for the comparison result between the signal under test and the threshold voltage. A threshold voltage generator generates the threshold voltage having a voltage level that corresponds to the control data at every setting timing indicated by a first timing signal. A level comparator compares the voltage level of the signal under test with its corresponding threshold voltage. A timing comparator latches the output of the level comparator at a strobe timing indicated by a second timing signal so as to generate a comparison signal. A timing adjustment unit adjusts the phase of the first timing signal. | 12-20-2012 |
20120320527 | BOARD ASSEMBLY, ELECTRONIC DEVICE TEST APPARATUS AND WATER JACKET - A board assembly which enables reduction of the size of an electronic device test apparatus is provided. A test module | 12-20-2012 |
20120319855 | SIGNAL DISPLAY DEVICE, METHOD, AND RECORDING MEDIUM - According to the present invention, a signal display device includes: a first characteristic value measurement unit, a display unit, a second characteristic value measurement unit, and a display form changing unit. The first characteristic value measurement unit measures any one of characteristic values of a signal to be measured, and the display unit displays the characteristic value measured by the first characteristic value measurement unit while the characteristic value is associated with time. The second characteristic value measurement unit measures any one of the characteristic values of the signal to be measured, and the display form changing unit changes a display form on the display unit according to the characteristic value measured by the second characteristic value measurement unit. | 12-20-2012 |
20120319794 | TEST APPARATUS FOR DIGITAL MODULATED SIGNAL - A test apparatus includes digital modulators provided in increments of multiple channels. A baseband signal generator performs retiming of data input as a modulation signal for the in-phase (quadrature) component, using a timing signal the timing of which can be adjusted, thereby generating a baseband signal. A driver generates a multi-value digital signal having a level that corresponds to the baseband signal output from the baseband signal generator. A multiplier amplitude-modulates a carrier signal with the multi-value digital signal. An adder sums the output signals of the multipliers. | 12-20-2012 |
20120304009 | TEST APPARATUS AND TEST METHOD - A test apparatus that tests a device under test outputting a data signal and a clock signal indicating a timing at which the data signal is to be sampled, comprising an acquiring section that acquires the data signal output by the device under test, at a timing corresponding to the clock signal; a buffer section that includes a plurality of entries, buffers the data signal acquired by the acquiring section at the timing corresponding to the clock signal sequentially in the entries, and outputs the data signal buffered in the entries at a timing of a timing signal generated according to a test period of the test apparatus; and a judging section that judges pass/fail of the device under test based on a result of a comparison between the data signal output from the buffer section and an expected value. | 11-29-2012 |
20120300826 | TEST APPARATUS AND TEST METHOD - A test apparatus that tests a device under test exchanging a data signal and a clock signal, the test apparatus comprising a test signal supplying section that supplies the device under test with a data signal and a clock signal, as a test signal; a data acquiring section that acquires the data signal output by the device under test, at a timing corresponding to the clock signal output by the device under test; a judging section that judges pass/fail of the device under test based on a comparison result of a comparison between the data signal acquired by the data acquiring section and an expected value; and an adjusting section that, when performing an adjustment, adjusts a delay amount of the clock signal used to generate the timing at which the data signal is acquired. | 11-29-2012 |
20120299606 | TEST APPARATUS AND TEST METHOD - Provided is a test apparatus that tests a device under test outputting a data signal and a clock signal indicating a timing at which the data signal is to be sampled, the test apparatus comprising a data acquiring section that acquires the data signal output by the device under test, at a timing corresponding to the clock signal output by the device under test; a masking section that masks the acquisition of data by the data acquiring section, while the device under test is not outputting the clock signal; and a judging section that judges pass/fail of the device under test based on a result of a comparison between the data signal acquired by the data acquiring section and an expected value. | 11-29-2012 |
20120299600 | TEST APPARATUS AND TEST METHOD - A test apparatus that tests a device under test outputting a data signal and a clock signal indicating a timing at which the data signal is to be sampled, the test apparatus comprising a data acquiring section that acquires the data signal output by the device under test, at a timing corresponding to a sampling clock corresponding to the clock signal output by the device under test or a timing of a timing signal corresponding to a test period of the test apparatus; a judging section that judges pass/fail of the device under test, based on a result of a comparison between the data signal acquired by the data acquiring section and an expected value; and a designating section that designates whether the data acquiring section acquires the data signal at the timing corresponding to the sampling clock or at the timing corresponding to the timing signal. | 11-29-2012 |
20120286801 | MANUFACTURING METHOD, SWITCHING APPARATUS, TRANSMISSION LINE SWITCHING APPARATUS, AND TEST APPARATUS - An actuator is manufactured that includes piezoelectric film that does not suffer physical damage. Provided is a manufacturing method comprising first insulating layer deposition of depositing a first insulating layer on a substrate using an insulating material; first annealing of annealing the first insulating layer; first electrode layer deposition of depositing a first electrode layer on the first insulating layer using a conductive material; first piezoelectric film deposition of depositing a first piezoelectric film on the first electrode layer by applying a sol-gel material on the first electrode layer and annealing the sol-gel material; second electrode layer deposition of depositing a second electrode layer on the first piezoelectric film using a conductive material; second insulating layer deposition of depositing a second insulating layer on the second electrode layer using an insulating material; and second annealing of annealing the second insulating layer. | 11-15-2012 |
20120286797 | ELECTROMAGNETIC WAVE MEASUREMENT DEVICE, MEASUREMENT METHOD, AND RECORDING MEDIUM - According to the present invention, an electromagnetic wave measurement device includes an electromagnetic wave output device, an electromagnetic wave detector and a measurement unit. The electromagnetic wave output device outputs an electromagnetic wave having a frequency equal to or more than 0.01 [THz] and equal to or less than 100 [THz] toward a device under test including at least two layers, and the electromagnetic wave detector detects reflected electromagnetic waves which are the electromagnetic waves reflected by the respective at least two layers. The measurement unit measures the device under test based on one or both of extreme values of electric fields of the respective reflected electromagnetic waves and a time difference between timings in which the electric fields of the respective reflected electromagnetic waves take the extreme values. | 11-15-2012 |
20120280707 | BOARD MOUNTING APPARATUS, TEST HEAD, AND ELECTRONIC DEVICE TEST APPARATUS - A board mounting apparatus includes: a guide mechanism which guides a pin electronic card along a horizontal direction to an inside of a test head; and an insert mechanism which moves a pin electronic card guided into the test head along a vertical direction so that the pin electronic card is electrically connected through connectors to a back board. | 11-08-2012 |
20120280705 | TEST HEAD, TEST BOARD AND TEST APPARATUS - A test board can be inserted to a test head and removed from the test head while the connecting section for mounting thereon devices under test is mounted on the upper portion of the test head. A test head for retaining therein at least one test board for testing devices under test, includes: a casing provided with, on one side surface thereof, an opening through which the at least one test board is inserted and removed, the casing retaining therein the at least one test board with an upper side thereof oriented towards an upper surface of the casing; and a mounting member that guides a lower side of the at least one test board through the opening to a pre-set position, imposes an upward force to the lower side of the at least one test board, thereby mounting the at least one test board to the casing. | 11-08-2012 |
20120269521 | LIGHT SOURCE, OPTICAL SIGNAL GENERATOR, AND ELECTRICAL SIGNAL GENERATOR - To efficiently apply jitter to an optical signal using a simple configuration, provided is an optical signal generating apparatus that outputs an optical pulse pattern signal including jitter, the optical signal generating apparatus comprising a light source section that outputs laser light having an optical frequency corresponding to a frequency control signal, an optical modulation section that modulates an optical signal output by the light source section, according to a designated pulse pattern, and an optical jitter generating section that delays an optical signal passed by the optical modulation section according to the optical frequency, to apply jitter to the optical signal. | 10-25-2012 |
20120268157 | TEST CARRIER AND BOARD ASSEMBLY - A test carrier | 10-25-2012 |
20120268156 | TEST CARRIER - A test carrier | 10-25-2012 |
20120268138 | TEST APPARATUS - To detect whether energy accumulated in an inductive load section has been discharged. Provided is a test apparatus that tests a device under test, comprising a power supply section that generates a power supply voltage to be supplied to the device under test; an inductive load section that is provided in a path between the power supply section and the device under test; a housing section that houses a substrate that includes at least the inductive load section; and a lock maintaining section that keeps an opening/closing section, which allows an operator to access the substrate within the housing section, in a locked state when a voltage at a predetermined position on the substrate is greater than a set voltage. | 10-25-2012 |
20120268102 | SWITCHING APPARATUS AND TEST APPARATUS - To restrict a bowing amount of a piezoelectric actuator, provided is a switching apparatus comprising a contact point section including a first contact point; and an actuator that moves a second contact point to contact or move away from the first contact point. The actuator includes a first piezoelectric film that expands and contracts according to a drive voltage to change a bowing amount of the actuator, and a second piezoelectric film that is provided in parallel with the first piezoelectric film and restricts bowing of the actuator when the drive voltage is not being supplied to the first piezoelectric film. | 10-25-2012 |
20120267961 | WIRELESS POWER SUPPLY APPARATUS - A resonance circuit includes a transmission coil and a resonance capacitor connected in series. A multi-tone power supply is capable of selecting arbitrary frequency components from among multiple discrete frequency components, and outputs, to the resonance circuit, a multi-tone signal obtained by superimposing sine wave signals of the respective frequency components thus selected. In a measurement mode, a frequency control circuit sets all the frequency components for the multi-tone power supply, and selects at least one frequency component at which the electric power transmission efficiency is high in the state in which a multi-tone signal is generated by superimposing the sine wave signals of all the frequencies. In a power supply mode, the aforementioned at least one frequency component thus selected in the measurement mode is set for the multi-tone power supply. | 10-25-2012 |
20120262321 | ANALOG TO DIGITAL CONVERTER AND DIGITAL TO ANALOG CONVERTER - To decrease the burden of digital processing, provided is an AD conversion apparatus comprising a pattern generating section that, for each target bit specified one bit at a time moving downward in the output data, generates a pattern signal having a pulse width or number of pulses corresponding to a weighting of the target bit; an integrating section that integrates the pattern signals according to a judgment value for judging a value of the target bit each time a pattern signal is generated, and outputs a reference signal obtained by accumulating the integrated value of each pattern signal; a comparing section that, each time generation of a pattern signal is finished, compares the input signal to the reference signal; and an output section that outputs the output data to have values corresponding to the comparison results obtained after each generation of a pattern signal corresponding to a bit is finished. | 10-18-2012 |
20120262215 | TIMING GENERATOR AND TEST APPARATUS - A timing generator that outputs a timing signal obtained by delaying an input signal, comprising first and second period delay sections that each output a rate signal obtained by delaying the input signal by a delay amount corresponding to an integer multiple of a period of an operation clock supplied thereto; a first high-accuracy delay section that outputs the timing signal obtained by delaying a signal input thereto by a delay amount that is less than the period of the operation clock; and a mode switching section that switches between a low-speed mode, in which the rate signal output by the first period delay section is input to the first high-accuracy delay section, and a high-speed mode, in which a signal obtained by interleaving the rate signals output by the first period delay section and the second period delay section is input to the first high-accuracy delay section. | 10-18-2012 |
20120257467 | MEMORY REPAIR ANALYSIS APPARATUS, MEMORY REPAIR ANALYSIS METHOD, AND TEST APPARATUS - A memory repair analysis apparatus that performs a repair analysis on a memory under test, comprising a row-oriented fail number storage section that stores the number of fail cells in each row; a column-oriented fail number storage section that stores the number of fail cells in each column; a row-weighting storage section that, for each row, stores the total number of fail cells in each column containing a fail cell included in the row; a column-weighting storage section that, for each column, stores the total number of fail cells in each row containing a fail cell included in the column; and a determining section that determines which of spare row regions and spare column regions are to replace the fail cells. | 10-11-2012 |
20120249157 | TEST APPARATUS - Provided is a test apparatus that tests a memory under test including a plurality of repair regions for repairing fails in a memory region, the test apparatus comprising a testing section that sequentially tests each of a plurality of portions of the memory region of the memory under test; a repair solution memory that stores a repair solution indicating which repair region replaces a fail portion of the memory under test; and an updating section that, during testing, in response to a new fail portion being detected by the testing section, updates the repair solution stored in the repair solution memory to be a repair solution that also repairs the newly detected fail portion. | 10-04-2012 |
20120235699 | TEST CARRIER - A test carrier includes a base member and a cover member between which a die is interposed. The base film of the base member has: first interconnect patterns which are formed in advance; and a printing region where second interconnect patterns which electrically connect to the first interconnect patterns are to be formed by printing. | 09-20-2012 |
20120235043 | MEASUREMENT APPARATUS AND MEASUREMENT METHOD - There is provided a measuring apparatus including a space arrangement structure that includes space regions surrounded by conductors in a plane, an electromagnetic wave emitter that emits electromagnetic waves towards an object held by the space arrangement structure, and an electromagnetic wave detector that measures the electromagnetic waves that have passed through the space arrangement structure. Here, characteristics of the object are measured by measuring the electromagnetic waves that have passed through the space arrangement structure. The electromagnetic waves emitted from the electromagnetic wave emitter towards the space arrangement structure are incident on the plane containing the space regions at an angle, and the electromagnetic waves that have passed through the space arrangement structure are measured. | 09-20-2012 |
20120229314 | TEST APPARATUS AND TEST METHOD FOR A/D CONVERTER - A test apparatus configured to test an N-bit (N represents an integer) A/D converter is provided. A voltage generating unit outputs a 2 | 09-13-2012 |
20120228955 | TRANSMISSION COIL FOR WIRELESS POWER TRANSMISSION - A transmission coil is mounted in a wireless power supply apparatus, and is configured to transmit an electric power signal including any one from among an electric field, a magnetic field, and an electromagnetic field. The transmission coil includes a loop coil and a magnetic member. The magnetic member is configured to cover a particular portion of the loop coil. For example, the loop coil may be configured to have a shape in which a first side and a second side are substantially in parallel with each other. The magnetic member may be configured to cover the first side of the loop coil. | 09-13-2012 |
20120226951 | TEST APPARATUS - Provided is a test apparatus comprising a plurality of pattern output sections. In a high-speed mode, each pattern output section outputs, as pattern data corresponding to at least one of a plurality of partial periods, the pattern data corresponding to an input pattern input to the pattern output section and the pattern data corresponding to input patterns input to other pattern output sections. | 09-06-2012 |
20120218004 | POWER SUPPLY APPARATUS FOR TEST APPARATUS - A first A/D converter converts an analog observed value, which corresponds to a power supply signal supplied to a power supply terminal of a DUT, into a digital observed value. By means of digital calculation processing, a digital signal processing circuit generates a control value that is adjusted such that the digital observed value matches a predetermined reference value. A first D/A converter supplies, via a power supply line to the power supply terminal of the DUT, an analog power supply signal obtained by performing digital/analog conversion of the control value. A load estimating unit applies a test signal containing a predetermined frequency component via the power supply line to a node via which the power supply terminal is to be connected, and generates a control parameter for the digital signal processing circuit according to the test signal and the observed signal. | 08-30-2012 |
20120217985 | TEST APPARATUS AND TEST METHOD - There is provided a test apparatus that is capable of applying, to a device under test, a current that rises within a short period. A test apparatus for testing a device under test, includes a current source that supplies the device under test with a current, a dummy load that has an electrical characteristic corresponding to an electrical characteristic of the device under test, and a switching section that switches whether the current source is connected to the dummy load or the device under test. Here, after connecting the current source to the dummy load, the switching section disconnects the current source from the dummy load and connects the current source to the device under test when a voltage applied to the dummy load reaches a voltage within a predetermined range. | 08-30-2012 |
20120216086 | TEST APPARATUS - A test apparatus comprising a first buffer section and a second buffer section that each buffers fail data and address data; an address fail memory section that writes the fail data buffered in the first buffer section to an address of an internal memory indicated by the address data corresponding to the fail data, using an RMW process; and a control section that, in a state in which the fail data and address data output from the testing section are supplied to the first buffer section, when unused capacity of the first buffer section becomes less than or equal to a predetermined first threshold value, supplies the fail data and address data output from the testing section to the second buffer section instead of to the first buffer section. | 08-23-2012 |
20120214261 | TEST APPARATUS, TEST METHOD AND MANUFACTURING METHOD - Provided is a test apparatus for testing a device under test, comprising a dicing section that dices a wafer on which a plurality of devices under test are formed to separate each of the devices under test; a test packaging section that packages each of the devices under test resulting from the dicing by the dicing section in an individual test package; a testing section that tests the devices under test packaged in the test packages; a removing section that removes the devices under test that have been tested from the test packages; and a commercial packaging section that packages the devices under test removed from the test packages in commercial packages. | 08-23-2012 |
20120212247 | TEST APPARATUS AND TEST METHOD - Provided is a test apparatus for testing a plurality of devices under test formed on a semiconductor wafer, including: a probe card to be connected to respective contacts of the plurality of the devices under test on a connection surface to be overlapped on the semiconductor wafer, the probe card being provided with a plurality of corresponding contacts on a rear surface of the connection surface; and a test head that tests the plurality of devices under test on the semiconductor wafer by sequentially connecting to each part of the plurality of contacts of the probe card. | 08-23-2012 |
20120205143 | MANUFACTURING APPARATUS, MANUFACTURING METHOD AND PACKAGED DEVICE - It is an objective of the present invention to eliminate wafer testing. Provided is a manufacturing apparatus comprising a detecting section that detects a position of a device terminal of a device; a generating section that generates a substrate-side terminal, which connects to the device terminal, on a substrate at a position corresponding to the device terminal; and a mounting section that mounts the device on the substrate and connects the device terminal to the substrate-side terminal. The detecting section captures an image of the device and detects the position of the device terminal based on the captured image, and the generating section prints a pattern of the substrate-side terminal on the substrate at a position corresponding to the device terminal. | 08-16-2012 |
20120201284 | MULTI-VALUED DRIVER CIRCUIT - A multi-valued driver circuit selectively outputs, to a transmission line, one from among multiple voltages according to a selection signal. A memory circuit stores setting data which define the respective levels of the multiple voltages. According to the selection signal, a selector circuit selects one from among the multiple setting data stored in the memory circuit. A Thevenin termination circuit outputs a voltage that corresponds to the upper M bits of the data thus selected by the selector circuit. An R-2R ladder circuit outputs a voltage that corresponds to the lower Nl bits of the data thus selected by the selector circuit. | 08-09-2012 |
20120198292 | TEST APPARATUS AND TEST METHOD - Provided is a test apparatus that tests a memory under test, comprising a testing integrated circuit device that tests the memory under test and includes an internal memory storing test information including at least one of a test result and test data for a partial memory region of the memory under test; an external memory that stores the test information for an entire memory region of the memory under test; and a memory controller that is connected to the external memory and transmits test information for a memory region of a test target between the external memory and the internal memory. Also provided is a test method. | 08-02-2012 |
20120194374 | DIGITAL TO ANALOG CONVERTER - N upper-side resistors and N lower-side resistors are severally associated with respective bits of a digital input code. Each resistance value is weighted in an essentially binary manner according to the corresponding bit. N upper-side switches are each arranged in parallel with a corresponding upper-side resistor, and each is configured such that its on/off state is controlled according to the corresponding bit. N lower-side switches are each arranged in parallel with a corresponding lower-side resistor, and each is configured such that its on/off state is controlled according to logical inversion of the corresponding bit. | 08-02-2012 |
20120194251 | RECEIVING APPARATUS, TEST APPARATUS, RECEIVING METHOD AND TEST METHOD - Provided is a receiving apparatus that receives a data signal and a clock signal indicating a reference timing to acquire the data signal. The receiving apparatus includes a multi-strobe generating section that generates, based on a pulse of the recovered clock, a plurality of strobes of which phases are different from each other, a first detecting section that detects a position of an edge of the clock signal relative to the strobes based on values of the clock signal that are acquired at respective timings of the strobe, a first adjusting section that adjusts a phase of the recovered clock according to the edge position of the clock signal, and a second adjusting section that adjusts the timing to acquire the data signal according to a phase adjustment amount of the recovered clock made by the first adjusting section. | 08-02-2012 |
20120194206 | Measuring Apparatus - A test for connecting a transmitter and a receiver of a device under test with each other is carried out by a measurement device. The measurement device | 08-02-2012 |
20120188108 | High Speed, High Resolution, High Precision Voltage Source/AWG System for ATE - A method for compensating a linearity error of a dual digital-to-analog converter, including the steps of receiving a digital data signal which include a plurality of bits, the digital data signal indicating a voltage signal to be generated, the plurality of bits representing a set of consecutive bits being confined within a highest bit and a lowest bit, applying a high-bit-array to a first digital-to-analog converter, the high-bit-array being composed of a consecutive sub-set of the plurality of bits of the digital data signal, the sub-set including the highest bit of the digital data signal, using at least a part of a correction data of a look-up-table for manipulating at least a part of a low-bit-array, being composed of a consecutive sub-set of the plurality of bits of the digital data signal, where the sub-set includes the lowest bit of the digital data signal. | 07-26-2012 |
20120188003 | LEAKAGE COMPENSATED ELECTRONIC SWITCH - An electronic circuit for switching purposes comprises a set of at least four electronic switches. A first subset and a second subset comprise at least two electronic switches of said set, respectively. Said at least two electronic switches of said first subset are arranged in a serial connection. Said at least two electronic switches of said second subset are arranged in a serial connection. The electronic circuit comprises a first buffer connected to a first electronic switch of said first subset and a second buffer connected to a second electronic switch of said second subset. Said first buffer minimises a potential drop across said first electronic switch when in open state, and said second buffer minimises a potential drop across said second electronic switch when in open state. The electronic circuit further comprises a switched connection towards ground arranged in between the two subsets. | 07-26-2012 |
20120187973 | TEST APPARATUS - An existing test head is made best use of and a capital investment is reduced. A test apparatus for testing a plurality of devices under test includes: a plurality of test heads for retaining therein at least one test board to test devices under test; a connecting section mounted on upper surfaces of the plurality of test heads and is independently fixed to each of the plurality of test heads; and a DUT board on which the plurality of devices under test are mounted, the DUT board being mounted to the connecting section, where the at least one test board is mountable and removable through a side surface of each of the plurality of test heads while the connecting section is mounted to the test head. | 07-26-2012 |
20120187968 | TEST APPRATUS - Provided is a test apparatus that tests a device under test, comprising a power supply section that supplies the device under test with power; a comparing section that detects a characteristic value indicating a state of the device under test and compares the characteristic value to a predetermined threshold value; a cutoff section that cuts off the power supplied from the power supply section to the device under test, based on a result of the comparison by the comparing section; and a control section that changes at least one of the threshold value of the comparing section and a detection timing at which the characteristic value is detected. | 07-26-2012 |
20120182031 | Test apparatus and test method - Provided is a test apparatus that tests a device under test, comprising an inductance load section that is provided in a path through which test current flows to the device under test and that has an inductance component; a switching section that switches whether the test current is supplied to the device under test from the inductance load section; a cut-off control section that severs the path by switching the switching section according to a state of the device under test; and a voltage control section that controls voltage of the path between the inductance load section and the switching section to be no greater than a predetermined clamp voltage. | 07-19-2012 |
20120182026 | CLOCK GENERATING APPARATUS, TEST APPARATUS AND CLOCK GENERATING METHOD - There is provided a clock generating apparatus for generating a recovered clock by recovering a clock from an edge of a received signal, including a recovered clock generating section that generates the recovered clock, a multi-strobe generating section that generates a plurality of strobes with different phases, in accordance with a pulse of the recovered clock, a detecting section that detects a position of an edge of the received signal relative to the strobes, by referring to values of the received signal obtained at respective timings of the strobes, and an adjusting section that adjusts a phase of the recovered clock, in accordance with the position of the edge of the received signal. | 07-19-2012 |
20120177363 | OPTICAL SIGNAL OUTPUT APPARATUS, ELECTRICAL SIGNAL OUTPUT APPARATUS, AND TEST APPARATUS - To efficiently apply jitter to an optical signal using a simple configuration, provided is an optical signal output apparatus that outputs an optical pulse pattern signal including jitter, the optical signal generating apparatus comprising a light source section that outputs an optical signal having an optical frequency corresponding to a frequency control signal; an optical modulation section that modulates the optical signal output by the light source section, according to a designated pulse pattern; and an optical jitter generating section that delays an optical signal passed by the optical modulation section according to the optical frequency, to apply jitter to the optical signal. | 07-12-2012 |
20120176260 | ANALOG-DIGITAL CONVERTING METHOD AND ANALOG-DIGITAL CONVERTING APPARATUS - An analog-digital converting method comprising measuring, in advance, frequency characteristics of each of a plurality of ADCs; intra-group correction of, for each of a plurality of groups obtained by dividing a plurality of measurement signals, generating measurement signals that would be obtained when the frequency characteristics of the corresponding ADCs are ideal by multiplying the measurement signals by a correction coefficient that is based on the frequency characteristics of all the ADCs in the group; and inter-group correction of correcting and combining the frequency characteristics of the groups based on a difference in the frequency characteristics between the groups formed during the intra-group correction, to generate a frequency spectrum of the digital signal. | 07-12-2012 |
20120176143 | SAMPLING APPARATUS AND TEST APPARATUS - A sampling apparatus that converts an analog target signal in which the same waveform repeats into a digital value by sampling the target signal at each of a plurality of phases, and outputs the digital value. The sampling apparatus comprises a designating section that sequentially designates bits in the digital value as target bits, beginning with the most significant bits; a generating section that, for each designated target bit, generates a threshold value for determining a value of the target bit based on a determined value of a bit that is higher-order than the target bit in the digital value at each of the phases; and a converting section that, for each designated target bit, determines the value of the target bit in the digital value at each phase by comparing the target signal to an analog comparison signal corresponding to the threshold value at each phase. | 07-12-2012 |
20120163404 | REPETITION FREQUENCY CONTROL DEVICE - According to the repetition frequency control device, a master laser outputs a master laser light pulse the repetition frequency of which is controlled to a predetermined value. A slave laser outputs a slave laser light pulse. A reference comparator compares a voltage of a reference electric signal the repetition frequency of which is the predetermined value and a predetermined voltage with each other, thereby outputting a result thereof. A measurement comparator compares a voltage based on a light intensity of the slave laser light pulse and the predetermined voltage with each other, thereby outputting a result thereof. A phase difference detector detects a phase difference between the output from the reference comparator and the output from the measurement comparator. A loop filter removes a high-frequency component of an output from the phase difference detector. | 06-28-2012 |
20120161840 | SR FLIP-FLOP - An input priority determination circuit is configured such that: (i) when a set signal S is asserted and a reset signal R is negated, an intermediate set signal S′ is asserted and an intermediate reset signal R′ is negated; (ii) when the set signal S is negated and the reset signal R is asserted, the intermediate set signal S′ is negated, and the intermediate reset signal R′ is asserted; (iii) when a control signal P indicates a set priority mode, and when the set signal S and the reset signal R are both asserted, the intermediate set signal S′ is asserted and the intermediate reset signal R′ is negated; and (iv) when the control signal P indicates a reset priority mode, and when the set signal S and the reset signal R are both asserted, the intermediate set signal S′ is negated and the intermediate reset signal R′ is asserted. | 06-28-2012 |
20120161806 | PROBE MANUFACTURING METHOD, PROBE STRUCTURE, PROBE APPARATUS, AND TEST APPARATUS - Minute probes are created to correspond to the alignment of the input/output terminals of a device under test. A probe manufacturing method of manufacturing a probe, includes: forming a contact section on a probe main body; and shaping at least one of the contact section and the probe main body by cutting by means of a cutting tool. The contact section is formed on a substrate that is to become the probe main body, and the probe manufacturing method further includes: after shaping at least one of the contact section and the substrate that is to become the probe main body, removing the portion of the substrate excluding the probe main body thereby forming a probe. | 06-28-2012 |
20120161800 | MEASUREMENT CIRCUIT AND TEST APPARATUS - Provided is a measurement circuit that measures a signal under measurement input thereto, comprising a level comparing section that outputs a logic value according to a comparison result between a signal level of the signal under measurement and a set threshold level; a logic comparing section that acquires the logic value output by the level comparing section at a comparison timing input thereto; and a timing adjusting section that adjusts relative phases of a signal output by the level comparing section and the comparison timing, based on the expected value pattern of the signal under measurement and the threshold level. | 06-28-2012 |
20120158348 | TIMING GENERATOR - A delay setting data generator generates delay setting data based on rate data. A variable delay circuit delays the test pattern data by a delay time determined by the delay setting data with reference to a predefined unit amount of delay. First rate data designates the period of the test pattern data with a precision determined by the unit amount of delay. Second rate data designates the period of the test pattern data with a precision higher than that determined by the unit amount of delay. The delay setting data generator outputs a first value and a second value in a time division manner at a ratio determined by the second rate data, the first and second values being determined by the first rate data. | 06-21-2012 |
20120155500 | REPETITION FREQUENCY CONTROL DEVICE - A repetition frequency control device includes a slave photoelectric conversion unit which converts a slave laser light pulse into a slave electrical signal, a master photoelectric conversion unit which converts a master laser light pulse into a master electrical signal, a frequency change unit which changes the repetition frequency of the master electric signal by a predetermined value, a phase comparator which detects a phase difference between the slave electric signal and the output from the frequency change unit, and a loop filter which removes a high frequency component of an output from the phase comparator, where the repetition frequency of the master laser does not undergo control based on one or both of the master electric signal and the slave electric signal. | 06-21-2012 |