Patent application title: METHOD FOR SELECTIVELY FORMING SYMMETRICAL OR ASYMMETRICAL FEATURES USING A SYMMETRICAL PHOTOMASK DURING FABRICATION OF A SEMICONDUCTOR DEVICE AND ELECTRONIC SYSTEMS INCLUDING THE SEMICONDUCTOR DEVICE
Hongbin Zhu (Boise, ID, US)
Hongbin Zhu (Boise, ID, US)
Jeremy Madsen (Meridian, ID, US)
MICRON TECHNOLOGY, INC.
IPC8 Class: AH01L23485FI
Class name: Active solid-state devices (e.g., transistors, solid-state diodes) physical configuration of semiconductor (e.g., mesa, bevel, groove, etc.)
Publication date: 2011-10-13
Patent application number: 20110248385
A method for patterning a material during fabrication of a semiconductor
device provides for the selective formation of either asymmetrical
features or symmetrical features using a symmetrical photomask, depending
on which process flow is chosen. The resulting features which are
fabricated use spacers formed around a patterned material. If one
particular etch is used to remove a base material, symmetrical features
result. If two particular etches are used to remove the base material,
asymmetrical features remain.
1. A structure, comprising: a structure to be etched, comprising: a
polysilicon material; a tungsten silicide material overlying the
polysilicon material; a dielectric material overlying the tungsten
silicide material; a transparent carbon (TC) material overlying the
dielectric material; and an antireflective material overlying the TC
material; and a plurality of paired cross sectional mask material spacers
overlying the antireflective material.
2. The structure of claim 18, further comprising: the polysilicon material being about 750 angstroms (Å) and contacting the tungsten silicide material; the tungsten silicide material being about 900 Å and contacting the dielectric material; the dielectric material being a tetraethyl orthosilicate (TEOS) material about 1,400 Å and contacting the TC material; the transparent carbon layer being about 2,000 Å and contacting the antireflective material; and the antireflective material being a deposited antireflective coating (DARC) from about 200 Å to about 260 Å.
3. The structure of claim 19 further comprising: the plurality of paired cross sectional mask material spacers having a uniform distance between adjacent paired spacers and between adjacent pairs of spacers, wherein the distance between adjacent paired spacers is about equal to the distance between adjacent pairs of spacers; a plurality of first openings at a level below the plurality of paired cross sectional mask material spacers, with one first opening located between each paired spacer; and a plurality of second openings at a level below the plurality of paired cross sectional mask material spacers, with one second opening located between each pair of spacers, wherein a volume of each first opening is substantially less than a volume of each second opening.
4. A semiconductor device, comprising: a plurality of first features with a rectangular profile; a plurality of second features with an angular profile, wherein the plurality of first features are a different volume than the plurality of the second features; and the plurality of the first and second features are formed simultaneously.
5. The semiconductor device of claim 4, wherein the first and second features are formed simultaneously via an anisotropic etch.
CROSS REFERENCE TO RELATED APPLICATION
 This application is a divisional of U.S. patent application Ser. No. 11/766,931, filed on Jun. 22, 2007.
 Various embodiments of the present invention relate to the field of semiconductor manufacture. More particularly, embodiments of the present invention disclose a method for selectively forming symmetrical or asymmetrical features using a symmetrical photomask.
 During the formation of a semiconductor device, many features such as conductive lines, contacts, dielectric isolation, and other features are commonly formed over and within a semiconductor wafer. A goal of semiconductor device engineers is to form as many of these features in a given area as possible to increase yields, decrease manufacturing costs, and to miniaturize devices. The formation of these structures typically requires the use of lithography. Optical lithography, the lithographic method most used in leading-edge wafer processing, comprises projecting coherent light of a given wavelength, typically 248 nanometers (nm) or 193 nm, from an illumination source (illuminator) through a quartz photomask or reticle having a chrome pattern representative of features to be formed, and imaging that pattern onto a wafer coated with photoresist. The light chemically alters the photoresist and enables the exposed photoresist (if positive resist is used) or the unexposed photoresist (if negative resist is used) to be rinsed away using a developer.
 Semiconductor device processing often requires the formation of symmetrical features having uniform sizes, and asymmetrical features having different sizes. To form symmetrical features, a reticle having a regular chrome pattern is used to expose the photoresist. The formation of asymmetrical features, features having two (or more) different shapes and/or electrical properties, typically requires the use of two (or more) reticles, with one reticle defining the pattern of each feature.
 The manufacture of reticles is time consuming and expensive due to the complexity of a typical reticle used in semiconductor device fabrication. A photolithography method which provides for the selective formation of either symmetrical features or asymmetrical features using a single reticle would be desirable.
BRIEF DESCRIPTION OF THE DRAWINGS
 FIGS. 1-2 are cross sections depicting a starting structure for various embodiments of the present invention;
 FIGS. 3-8 are cross sections depicting a first embodiment of the present invention;
 FIGS. 9-13 are cross sections depicting a second embodiment of the present invention;
 FIG. 14 is an isometric depiction of various components which may be manufactured using devices formed with an embodiment of the present invention; and
 FIG. 15 is a block diagram of an embodiment of the invention to form part of a memory device having a storage transistor array.
 It should be emphasized that the drawings herein may not be to exact scale and are schematic representations. The drawings are not intended to portray the specific parameters, materials, particular uses, or the structural details of the invention, which can be determined by one of skill in the art by examination of the information herein.
DETAILED DESCRIPTION OF THE ILLUSTRATED EMBODIMENTS
 The term "wafer" is to be understood as a semiconductor-based material including silicon, silicon-on-insulator (SOI) or silicon-on-sapphire (SOS) technology, doped and undoped semiconductors, epitaxial layers of silicon supported by a base semiconductor foundation, and other semiconductor structures. Furthermore, when reference is made to a "wafer" in the following description, previous process steps may have been utilized to form regions or junctions in or over the base semiconductor structure or foundation. Additionally, when reference is made to a "substrate assembly" in the following description, the substrate assembly may include a wafer with materials including dielectrics and conductors and features such as transistors formed thereover, depending on the particular stage of processing. In addition, the semiconductor need not be silicon-based, but may be based on silicon-germanium, silicon-on-insulator, silicon-on-sapphire, germanium, or gallium arsenide, among others. Further, in the discussion and claims herein, the term "on" used with respect to two materials, one "on" the other, means at least some contact between the materials, while "over" means the materials are in close proximity, but possibly with one or more additional intervening materials such that contact is possible but not required. Neither "on" nor "over" implies any directionality as used herein. The term "conformal" describes a coating material in which angles of the underlying material are preserved by the conformal material. The term "about" indicates that the value listed may be altered, as long as the alteration does not result in nonconformance of the process or structure in question to the illustrated embodiment of the present invention. A "spacer" indicates a material, typically dielectric, formed as a conformal material over uneven topography then anisotropically etched to remove horizontal portions of the material and leaving vertical portions of the material.
 An embodiment of the present invention provides for the selective formation of either symmetrical features or asymmetrical features using a single reticle having a regular feature pattern. A process which results in the formation of a pattern of asymmetrical features is depicted by FIGS. 1-8, and a process which results in the formation of a pattern of symmetrical features is depicted by FIGS. 1, 2, and 9-13.
 FIG. 1 depicts a portion of a semiconductor wafer substrate assembly comprising polysilicon 10 about 750 angstroms (Å) thick; tungsten silicide (WSix) 12 about 900 Å thick; tetraethyl orthosilicate (TEOS) 14 about 1,400 Å thick; transparent carbon (TC) 16 about 2,000 Å thick; dielectric antireflective coating (DARC) 18 from about 200 Å to about 360 Å thick; photoresist (resist) 20 having uniform dimensions from about 40 Å to about 70 Å in horizontal width, from about 1,200 Å to about 2,000 Å in vertical height, with the resist features having a regular pitch (i.e. a uniform distance between analogous points of adjacent resist features) of from about 170 Å to about 200 Å; and conformal spacer material 22, for example comprising silicon nitride (Si3N4) from about 300 Å to about 500 Å thick. Individually, each of these materials and their formation is known in the art. The resist provides a first mask material which will be used to define spacers, and the spacer material will provide a second mask which will be used to define the underlying material.
 It will be appreciated from the description below that materials other than those specified may be used for each of the materials, depending on the use of the invention. In this embodiment, the several materials depicted in FIG. 1 may be used to form a NAND flash memory device. In an alternate embodiment, each of materials 10-18 may be replaced by a single dielectric material such as borophosphosilicate glass (BPSG) to form another type of device, or to form other features on a NAND flash device. Further, if the depicted materials are used, the thicknesses may vary over a wide range beyond the values listed in the preceding paragraph, but these materials and thicknesses are believed sufficient for use during NAND flash device formation with current technology. The thickness variation of the DARC material, however, may be limited by photolithography constraints, and any variation in resist and spacer width may be limited by feature pitch.
 The conformal spacer material 22 of FIG. 1 is etched using a vertical anisotropic etch to form a plurality of spacers 22 as depicted in FIG. 2. This etch removes spacer material selective to patterned material 20 and DARC material 18 (i.e. it will remove spacer material 22 while minimizing etching of patterned material 20 and DARC 18). FIG. 2 depicts paired cross sectional spacers contacting each mask feature 20.
 After etching spacers 22 as depicted in FIG. 2, DARC 18 is etched selective to patterned material 20 and spacers 22 using an anisotropic etch which has some isotropic properties to result in the FIG. 3 structure. This etch will preferably stop on or in TC 16, and may comprise tetrafluoromethane (CF4) at a flow rate of from about 60 sccm to about 160 sccm, difluoromethane (CH2F2) at a flow rate of from about 5 sccm to about 60 sccm, and trifluoromethane (CHF3) at a flow rate of about 100 sccm. During the etch, chamber pressure may be maintained to between about 5 millitorr and about 20 millitorr, and power in the range of about 600 watts to about 1,200 watts. While some undercutting of the dielectric under the spacer may occur, undercutting is preferably minimized. This etch forms one or more sloped recesses within DARC 18 resulting from the slope of the spacers 22, the pitch of adjacent spacers, and the qualiÅ to about 360 Å.
 After etching the sloped recesses as depicted in FIG. 3, the patterned material 20 is removed selective to spacers 22, DARC 18, and any exposed TC 16 using any appropriate etch to result in the FIG. 4 structure. One preferred etch comprises a mixture of sulfur dioxide (SO2) at a flow rate of about 120 sccm and oxygen (O2) at a flow rate of about 80 sccm. This etch may comprise the use of about 800 watts power, 8 mT pressure, and a bias voltage of 400 V. Another sufficient etch would comprise the use of hydrogen bromide (HBr), O2, and nitrogen (N2) optimized for the etch. Locations 40 depict openings between spacers 22 where the patterned material 20 has been removed to expose DARC 18. These regions of exposed DARC 18 have a horizontal profile. Locations 42 depict the sloped recesses within DARC 18 between spacers 22. Regions 42 of exposed DARC 18 have a more vertically oriented profile than the exposed horizontal portions 40 where patterned material 20 has been removed.
 Subsequently, DARC 18, TC 16, TEOS 14, and WSix 12 are etched using a vertical anisotropic etch which is selective to spacers 22 and which stops on or in polysilicon 10 to result in the structure of FIG. 5. Various known etches may be used to remove each of these materials to transfer the initial pattern to the underlayers. As depicted in FIG. 5, a lesser volume of material has been removed from materials 12-18 to form openings 42 than to form openings 40. Locations 40 of the depicted materials etch more quickly than locations 42, which may be due to the higher impact energy of the etchant as it contacts the horizontal bottom of the various materials at location 40, while the etchant may be deflected by the sloped sidewalls of spacers 22 at locations 42. Thus FIG. 5 depicts regions 40 which have a rectangular profile, which etch deeper than regions 42 which have a "V" shaped profile.
 After forming the FIG. 5 structure, spacers 22 may be removed selective to the exposed materials to result in the FIG. 6 structure. FIG. 6 depicts openings at location 40 which are asymmetrical with respect to openings at location 42. These openings 40, 42 have been formed using the symmetrical patterned material 20 as depicted in FIG. 1, and may result from the difference in slope between the two vertically oriented sides of each spacer. As depicted in FIG. 4, for example, the side of each spacer which physically contacts patterned material 20 is linear and generally vertical (i.e. has a vertical or near-vertical profile), while the side of each spacer which does not contact patterned material 20 is more sloped and has a more rounded profile.
 While various continuing processes may be completed with the FIG. 6 structure, one use is depicted in FIGS. 7 and 8. A blanket dielectric material 70 and a blanket conductive material 72 may be formed over the surface of the FIG. 6 structure to fill the openings at locations 40 and 42 as depicted in FIG. 7. Next, a planarizing process such as mechanical planarization, for example chemical-mechanical planarization (CMP), is performed on material 70 to result in the FIG. 8 structure. FIG. 8 depicts conductive features 80 having a first cross section and features 82 having a second cross section different from the first cross section. Features 80 may have different electrical properties than features 82, particularly if the features are generally uniform along their length. For example, the resistance of features 80 may be lower than features 82 due to the larger cross sectional area features 82. Further, the two features 80, 82 may form two different isolation lines, particularly with a doped substrate and oxide or another dielectric filling the trenches.
 In another embodiment of the invention, symmetrical features using the same reticle used to form the patterned material 20 of FIG. 1 is depicted in FIGS. 1, 2, and 9-13. In this embodiment, the structures of FIGS. 1 and 2 are formed in accordance with the embodiment described above.
 After forming the structure of FIG. 2, patterned material 20 is removed selective to DARC 18 and spacers 22 to result in the structure of FIG. 9. Next, DARC 18, TC 16, TEOS 14, and WSix 12 are etched selective to spacers 22 using an isotropic etch to result in the structure of FIG. 10. The DARC may be etched using an isotropic etch such as CF4/CH2F2, where the CF4:CH2F2 ratio is at least 4. TC may be etched with SO2/O2 as discussed with the previous embodiment. TEOS may be etched with CF4 at a flow rate of about 75 sccm and O2 at a flow rate of about 45 sccm, a chamber pressure of 5 mT, and a power of 1,500 watts, and a bias voltage of 300 V. Tungsten silicide may be etched with nitrogen trifluoride (NF3) and chlorine (Cl2) each at a flow rate of about 40 sccm, a power of about 15 mT, a power of about 400 watts, and an bias voltage of about 150 V, although other etch processes may be used.
 Subsequently, spacers 22 may be removed selective to the exposed materials to result in the FIG. 11 structure, which depicts symmetrical openings 110 etched into DARC 18, TC 16, TEOS 14, and WSi, 12. These symmetrical openings are formed using the patterned material 20 of FIG. 2, which was used to form the asymmetrical openings of the previous embodiment. Thus either symmetrical or asymmetrical features may be formed using the same symmetrical pattern.
 As with the previous embodiment, the structure of FIG. 11 may have various functions. One such function is depicted in FIGS. 12 and 13. In FIG. 12, a blanket dielectric 120 and a blanket conductive material 122 have been formed over the FIG. 11 structure and within openings 110. Dielectric 120 and conductive material 122 may then be planarized using mechanical planarization, such as CMP, to result in the structure of FIG. 13. These features may be used as conductive lines, or may have other uses. As depicted in FIG. 13, each conductive feature 122 would have similar cross sections and electrical properties which may differ because of processing variances.
 The actual structures represented by FIGS. 8 and 13 may have other features depending on the intended use of the embodiments of the present invention which are not immediately germane to the present processes and structures, and which have not been described or depicted for simplicity of explanation. Various uses for the processes and structures are likely, such as for use for vertical transistors or capacitors, hard masks, shallow trench isolation, and for other device features in the array and periphery.
 As depicted in FIG. 14, a semiconductor device 140 formed in accordance with an embodiment of the disclosed invention may be attached along with other devices such as a microprocessor 142 to a printed circuit board 144, for example to a computer motherboard or as a part of a memory module used in a personal computer, a minicomputer, or a mainframe 146. FIG. 14 may also represent use of device 140 in other electronic devices comprising a housing 146, for example devices comprising a microprocessor 142, related to telecommunications, the automobile industry, semiconductor test and manufacturing equipment, consumer electronics, or virtually any piece of consumer or industrial electronic equipment.
 The process and structure described herein can be used to manufacture a number of different structures comprising a metal material formed according to the inventive process to result in a densified metal material having decreased resistance and reduced contamination compared with conventional materials. FIG. 15, for example, is a simplified block diagram of a device such as a dynamic random access memory which may comprise conductive interconnects and other features which may be formed using an embodiment of the present invention. The general operation of such a device is known to one skilled in the art. FIG. 15 depicts a processor 142 coupled to a memory device 140, and further depicts the following basic sections of a memory integrated circuit: control circuitry 150; row address buffer 152 and column address buffer 154; row decoder 156 and column decoder 158; sense amplifiers 160; memory array 162; and data input/output 164.
 While this invention has been described with reference to illustrative embodiments, this description is not meant to be construed in a limiting sense. Various modifications of the illustrative embodiments, as well as additional embodiments of the invention, will be apparent to persons skilled in the art upon reference to this description. It is therefore contemplated that the appended claims will cover any such modifications or embodiments as fall within the true scope of the invention.
Patent applications by Hongbin Zhu, Boise, ID US
Patent applications by Jeremy Madsen, Meridian, ID US
Patent applications by MICRON TECHNOLOGY, INC.
Patent applications in class PHYSICAL CONFIGURATION OF SEMICONDUCTOR (E.G., MESA, BEVEL, GROOVE, ETC.)
Patent applications in all subclasses PHYSICAL CONFIGURATION OF SEMICONDUCTOR (E.G., MESA, BEVEL, GROOVE, ETC.)